1 /* 2 * Copyright (c) 2012-2016 The Linux Foundation. All rights reserved. 3 * 4 * Previously licensed under the ISC license by Qualcomm Atheros, Inc. 5 * 6 * 7 * Permission to use, copy, modify, and/or distribute this software for 8 * any purpose with or without fee is hereby granted, provided that the 9 * above copyright notice and this permission notice appear in all 10 * copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 13 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 14 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 15 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 16 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 17 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 18 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 19 * PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* 23 * This file was originally distributed by Qualcomm Atheros, Inc. 24 * under proprietary terms before Copyright ownership was assigned 25 * to the Linux Foundation. 26 */ 27 28 #ifndef __TARGADDRS_H__ 29 #define __TARGADDRS_H__ 30 31 #if defined(ATH_TARGET) 32 #include "soc_addrs.h" 33 #endif 34 35 #if !defined(ATH_TARGET) 36 #include "athstartpack.h" 37 #endif 38 39 /* 40 * SOC option bits, to enable/disable various features. 41 * By default, all option bits are 0. 42 * AR6004: These bits can be set in LOCAL_SCRATCH register 0. 43 * AR9888: These bits can be set in soc_core register SCRATCH_0. 44 */ 45 #define SOC_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */ 46 #define SOC_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */ 47 #define SOC_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */ 48 #define SOC_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */ 49 #define SOC_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */ 50 #define SOC_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */ 51 #define SOC_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */ 52 #define SOC_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */ 53 54 /* 55 * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the 56 * host_interest structure. It must match the address of the _host_interest 57 * symbol (see linker script). 58 * 59 * Host Interest is shared between Host and Target in order to coordinate 60 * between the two, and is intended to remain constant (with additions only 61 * at the end) across software releases. 62 * 63 * All addresses are available here so that it's possible to 64 * write a single binary that works with all Target Types. 65 * May be used in assembler code as well as C. 66 */ 67 #define AR6002_HOST_INTEREST_ADDRESS 0x00500400 68 #define AR6003_HOST_INTEREST_ADDRESS 0x00540600 69 #define AR6004_HOST_INTEREST_ADDRESS 0x00400800 70 #define AR9888_HOST_INTEREST_ADDRESS 0x00400800 71 #define AR900B_HOST_INTEREST_ADDRESS 0x00400800 72 #define AR6320_HOST_INTEREST_ADDRESS 0x00400800 73 #define QCA9377_HOST_INTEREST_ADDRESS 0x00400800 74 #define AR6004_SOC_RESET_ADDRESS 0X00004000 75 #define AR6004_SOC_RESET_CPU_INIT_RESET_MASK 0X00000800 76 #if defined(AR6006_MEMORY_NEW_ARCH) 77 #define AR6006_HOST_INTEREST_ADDRESS 0x00428800 78 #else 79 #define AR6006_HOST_INTEREST_ADDRESS 0x00400800 80 #endif 81 #define AR6006_SOC_RESET_ADDRESS 0X00004000 82 #define AR6006_SOC_RESET_CPU_INIT_RESET_MASK 0X00000800 83 #define QCA9984_HOST_INTEREST_ADDRESS 0x00400800 84 #define IPQ4019_HOST_INTEREST_ADDRESS 0x00400800 85 #define QCA9888_HOST_INTEREST_ADDRESS 0x00400800 86 87 88 #define HOST_INTEREST_MAX_SIZE 0x200 89 90 #if !defined(__ASSEMBLER__) 91 struct register_dump_s; 92 struct dbglog_hdr_s; 93 94 /* 95 * These are items that the Host may need to access 96 * via BMI or via the Diagnostic Window. The position 97 * of items in this structure must remain constant 98 * across firmware revisions! 99 * 100 * Types for each item must be fixed size across 101 * target and host platforms. 102 * 103 * More items may be added at the end. 104 */ 105 PREPACK64 struct host_interest_s { 106 /* 107 * Pointer to application-defined area, if any. 108 * Set by Target application during startup. 109 */ 110 A_UINT32 hi_app_host_interest; /* 0x00 */ 111 112 /* Pointer to register dump area, valid after Target crash. */ 113 A_UINT32 hi_failure_state; /* 0x04 */ 114 115 /* Pointer to debug logging header */ 116 A_UINT32 hi_dbglog_hdr; /* 0x08 */ 117 118 /* Save SW ROM version */ 119 A_UINT32 hi_sw_rom_version; /* 0x0c */ 120 121 /* 122 * General-purpose flag bits, similar to SOC_OPTION_* flags. 123 * Can be used by application rather than by OS. 124 */ 125 volatile A_UINT32 hi_option_flag; /* 0x10 */ 126 127 /* 128 * Boolean that determines whether or not to 129 * display messages on the serial port. 130 */ 131 A_UINT32 hi_serial_enable; /* 0x14 */ 132 133 /* Start address of DataSet index, if any */ 134 A_UINT32 hi_dset_list_head; /* 0x18 */ 135 136 /* Override Target application start address */ 137 A_UINT32 hi_app_start; /* 0x1c */ 138 139 /* Clock and voltage tuning */ 140 A_UINT32 hi_skip_clock_init; /* 0x20 */ 141 A_UINT32 hi_core_clock_setting; /* 0x24 */ 142 A_UINT32 hi_cpu_clock_setting; /* 0x28 */ 143 A_UINT32 hi_system_sleep_setting; /* 0x2c */ 144 A_UINT32 hi_xtal_control_setting; /* 0x30 */ 145 A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ 146 A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ 147 A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */ 148 A_UINT32 hi_clock_info; /* 0x40 */ 149 150 /* Host uses BE CPU or not */ 151 A_UINT32 hi_be; /* 0x44 */ 152 153 A_UINT32 hi_stack; /* normal stack */ /* 0x48 */ 154 A_UINT32 hi_err_stack; /* error stack */ /* 0x4c */ 155 A_UINT32 hi_desired_cpu_speed_hz; /* 0x50 */ 156 157 /* Pointer to Board Data */ 158 A_UINT32 hi_board_data; /* 0x54 */ 159 160 /* 161 * Indication of Board Data state: 162 * 0: board data is not yet initialized. 163 * 1: board data is initialized; unknown size 164 * >1: number of bytes of initialized board data (varies with board type) 165 */ 166 A_UINT32 hi_board_data_initialized; /* 0x58 */ 167 168 A_UINT32 hi_dset_RAM_index_table; /* 0x5c */ 169 170 A_UINT32 hi_desired_baud_rate; /* 0x60 */ 171 A_UINT32 hi_dbglog_config; /* 0x64 */ 172 A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */ 173 A_UINT32 hi_mbox_io_block_sz; /* 0x6c */ 174 175 A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */ 176 A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */ 177 178 A_UINT32 hi_refclk_hz; /* 0x78 */ 179 A_UINT32 hi_ext_clk_detected; /* 0x7c */ 180 A_UINT32 hi_dbg_uart_txpin; /* 0x80 */ 181 A_UINT32 hi_dbg_uart_rxpin; /* 0x84 */ 182 A_UINT32 hi_hci_uart_baud; /* 0x88 */ 183 A_UINT32 hi_hci_uart_pin_assignments; /* 0x8C */ 184 /* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */ 185 A_UINT32 hi_hci_uart_baud_scale_val; /* 0x90 */ 186 A_UINT32 hi_hci_uart_baud_step_val; /* 0x94 */ 187 188 A_UINT32 hi_allocram_start; /* 0x98 */ 189 A_UINT32 hi_allocram_sz; /* 0x9c */ 190 A_UINT32 hi_hci_bridge_flags; /* 0xa0 */ 191 A_UINT32 hi_hci_uart_support_pins; /* 0xa4 */ 192 /* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */ 193 A_UINT32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */ 194 /* 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high 195 * [31:16]: wakeup timeout in ms 196 */ 197 /* Pointer to extended board Data */ 198 A_UINT32 hi_board_ext_data; /* 0xac */ 199 A_UINT32 hi_board_ext_data_config; /* 0xb0 */ 200 /* 201 * Bit [0] : valid 202 * Bit[31:16: size 203 */ 204 /* 205 * hi_reset_flag is used to do some stuff when target reset. 206 * such as restore app_start after warm reset or 207 * preserve host Interest area, or preserve ROM data, literals etc. 208 */ 209 A_UINT32 hi_reset_flag; /* 0xb4 */ 210 /* indicate hi_reset_flag is valid */ 211 A_UINT32 hi_reset_flag_valid; /* 0xb8 */ 212 A_UINT32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */ 213 /* 0xbc - [31:0]: idle timeout in ms 214 */ 215 /* ACS flags */ 216 A_UINT32 hi_acs_flags; /* 0xc0 */ 217 A_UINT32 hi_console_flags; /* 0xc4 */ 218 A_UINT32 hi_nvram_state; /* 0xc8 */ 219 volatile A_UINT32 hi_option_flag2; /* 0xcc */ 220 221 /* If non-zero, override values sent to Host in WMI_READY event. */ 222 A_UINT32 hi_sw_version_override; /* 0xd0 */ 223 A_UINT32 hi_abi_version_override; /* 0xd4 */ 224 225 /* Percentage of high priority RX traffic to total expected RX traffic - 226 * applicable only to ar6004 */ 227 A_UINT32 hi_hp_rx_traffic_ratio; /* 0xd8 */ 228 229 /* test applications flags */ 230 A_UINT32 hi_test_apps_related ; /* 0xdc */ 231 /* location of test script */ 232 A_UINT32 hi_ota_testscript; /* 0xe0 */ 233 /* location of CAL data */ 234 A_UINT32 hi_cal_data; /* 0xe4 */ 235 236 /* Number of packet log buffers */ 237 volatile A_UINT32 hi_pktlog_num_buffers; /* 0xe8 */ 238 239 /* wow extension configuration */ 240 A_UINT32 hi_wow_ext_config; /* 0xec */ 241 A_UINT32 hi_pwr_save_flags; /* 0xf0 */ 242 243 /* Spatial Multiplexing Power Save (SMPS) options */ 244 A_UINT32 hi_smps_options; /* 0xf4 */ 245 246 /* Interconnect-specific state */ 247 A_UINT32 hi_interconnect_state; /* 0xf8 */ 248 249 /* Coex configuration flags */ 250 A_UINT32 hi_coex_config; /* 0xfc */ 251 252 /* Early allocation support */ 253 A_UINT32 hi_early_alloc; /* 0x100 */ 254 255 /* FW swap field */ 256 /* Bits of this 32bit word will be used to pass specific swap 257 instruction to FW */ 258 /* Bit 0 -- AP Nart descriptor no swap. When this bit is set 259 FW will not swap TX descriptor. Meaning packets are formed 260 on the target processor.*/ 261 /* Bit 1 -- TBD */ 262 263 A_UINT32 hi_fw_swap; /* 0x104 */ 264 265 /* global arenas pointer address, used by host driver debug */ 266 A_UINT32 hi_dynamic_mem_arenas_addr; /* 0x108 */ 267 268 /* allocated bytes of DRAM use by allocated */ 269 A_UINT32 hi_dynamic_mem_allocated; /* 0x10C */ 270 271 /* remaining bytes of DRAM */ 272 A_UINT32 hi_dynamic_mem_remaining; /* 0x110 */ 273 274 /* memory track count, configured by host */ 275 A_UINT32 hi_dynamic_mem_track_max; /* 0x114 */ 276 277 /* minidump buffer */ 278 A_UINT32 hi_minidump; /* 0x118 */ 279 280 /* bdata's sig and key addr */ 281 A_UINT32 hi_bd_sig_key; /* 0x11c */ 282 283 } POSTPACK64; 284 285 /* bitmap for hi_test_apps_related */ 286 #define HI_TEST_APPS_TESTSCRIPT_LOADED 0x00000001 287 #define HI_TEST_APPS_CAL_DATA_AVAIL 0x00000002 288 289 /* Bits defined in hi_option_flag */ 290 #define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */ 291 #define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */ 292 #define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */ 293 #define HI_OPTION_MAC_ADDR_METHOD 0x08 /* MAC addr method 0-locally administred 1-globally unique addrs */ 294 #define HI_OPTION_FW_BRIDGE 0x10 /* Firmware Bridging */ 295 #define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */ 296 #define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */ 297 #define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */ 298 #define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */ 299 #define HI_OPTION_NUM_DEV_LSB 0x200 300 #define HI_OPTION_NUM_DEV_MSB 0x800 301 #define HI_OPTION_DEV_MODE_LSB 0x1000 302 #define HI_OPTION_DEV_MODE_MSB 0x8000000 303 #define HI_OPTION_NO_LFT_STBL 0x10000000 /* Disable LowFreq Timer Stabilization */ 304 #define HI_OPTION_SKIP_REG_SCAN 0x20000000 /* Skip regulatory scan */ 305 #define HI_OPTION_INIT_REG_SCAN 0x40000000 /* Do regulatory scan during init before 306 * sending WMI ready event to host */ 307 #define HI_OPTION_SKIP_MEMMAP 0x80000000 /* REV6: Do not adjust memory map */ 308 309 #define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3 310 311 /* 2 bits of hi_option_flag are used to represent 3 modes */ 312 #define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */ 313 #define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */ 314 #define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */ 315 #define HI_OPTION_FW_MODE_BT30AMP 0x3 /* BT30 AMP Mode */ 316 317 /* 2 bits of hi_option flag are usedto represent 4 submodes */ 318 #define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */ 319 #define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */ 320 #define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */ 321 #define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */ 322 323 /* Num dev Mask */ 324 #define HI_OPTION_NUM_DEV_MASK 0x7 325 #define HI_OPTION_NUM_DEV_SHIFT 0x9 326 327 /* firmware bridging */ 328 #define HI_OPTION_FW_BRIDGE_SHIFT 0x04 329 330 /* Fw Mode/SubMode Mask 331 |-------------------------------------------------------------------------------| 332 | SUB | SUB | SUB | SUB | | | | | 333 | MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0] | 334 | (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) | 335 |-------------------------------------------------------------------------------| 336 */ 337 #define HI_OPTION_FW_MODE_BITS 0x2 338 #define HI_OPTION_FW_MODE_MASK 0x3 339 #define HI_OPTION_FW_MODE_SHIFT 0xC 340 #define HI_OPTION_ALL_FW_MODE_MASK 0xFF 341 342 #define HI_OPTION_FW_SUBMODE_BITS 0x2 343 #define HI_OPTION_FW_SUBMODE_MASK 0x3 344 #define HI_OPTION_FW_SUBMODE_SHIFT 0x14 345 #define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00 346 #define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8 347 348 349 /* hi_option_flag2 options */ 350 #define HI_OPTION_OFFLOAD_AMSDU 0x01 351 #define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */ 352 #define HI_OPTION_ENABLE_RFKILL 0x04 /* RFKill Enable Feature*/ 353 #define HI_OPTION_RADIO_RETENTION_DISABLE 0x08 /* Disable radio retention */ 354 #define HI_OPTION_EARLY_CFG_DONE 0x10 /* Early configuration is complete */ 355 356 #define HI_OPTION_RF_KILL_SHIFT 0x2 357 #define HI_OPTION_RF_KILL_MASK 0x1 358 359 #define HI_OPTION_HTT_TGT_DEBUG_TX_COMPL_IDX 0x20 360 361 #define HTT_TGT_DEBUG_TX_COMPL_IDX_VALUE() \ 362 ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_HTT_TGT_DEBUG_TX_COMPL_IDX)) 363 364 /* AR9888 1.0 only. Enable/disable CDC max perf support from host */ 365 #define HI_OPTION_DISABLE_CDC_MAX_PERF_WAR 0x20 366 #define CDC_MAX_PERF_WAR_ENABLED() \ 367 (!(HOST_INTEREST->hi_option_flag2 & HI_OPTION_DISABLE_CDC_MAX_PERF_WAR)) 368 #define HI_OPTION_USE_EXT_LDO 0x40 /* use LDO27 for 1.1V instead of PMU. */ 369 #define HI_OPTION_DBUART_SUPPORT 0x80 /* Enable uart debug support */ 370 #define HI_OPTION_BE_LATENCY_OPTIMIZE 0x100 /* This bit is to enable BE low latency for some customers. The side effect is TCP DL will be 8Mbps decreased (673Mbps -> 665Mbps).*/ 371 #define HT_OPTION_GPIO_WAKEUP_SUPPORT 0x200 /* GPIO wake up support */ 372 373 /* 374 * If both SDIO_CRASH_DUMP_ENHANCEMENT_HOST and SDIO_CRASH_DUMP_ENHANCEMENT_FW 375 * flags are set, then crashdump upload will be done using the BMI host/target 376 * communication channel. 377 */ 378 #define HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST 0x400 /* HOST to support using BMI dump FW memory when hit assert */ 379 #define HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_FW 0x800 /* FW to support using BMI dump FW memory when hit assert */ 380 381 /* USB_RESET_RESUME 382 * The host will set this flag, based on platform configuration specs. 383 * The target will check this flag at the time USB becomes suspended. 384 * If the flag is set, the target will invoke its reset / resume code. 385 * If the flag is not set, the target will do nothing, other than wait. 386 */ 387 #define HI_OPTION_USB_RESET_RESUME 0x1000 388 #define USB_RESET_RESUME() \ 389 (HOST_INTEREST->hi_option_flag2 & HI_OPTION_USB_RESET_RESUME) 390 391 #define GPIO_WAKEUP_ENABLED() \ 392 (HOST_INTEREST->hi_option_flag2 & HT_OPTION_GPIO_WAKEUP_SUPPORT) 393 394 395 /* hi_reset_flag */ 396 #define HI_RESET_FLAG_PRESERVE_APP_START 0x01 /* preserve App Start address */ 397 #define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02 /* preserve host interest */ 398 #define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04 /* preserve ROM data */ 399 #define HI_RESET_FLAG_PRESERVE_NVRAM_STATE 0x08 400 #define HI_RESET_FLAG_PRESERVE_BOOT_INFO 0x10 401 #define HI_RESET_FLAG_WARM_RESET 0x20 402 403 /* define hi_fw_swap bits */ 404 #define HI_DESC_IN_FW_BIT 0x01 405 406 #define HI_RESET_FLAG_IS_VALID 0x12345678 /* indicate the reset flag is valid */ 407 408 #define ON_RESET_FLAGS_VALID() \ 409 (HOST_INTEREST->hi_reset_flag_valid == HI_RESET_FLAG_IS_VALID) 410 411 #define RESET_FLAGS_VALIDATE() \ 412 (HOST_INTEREST->hi_reset_flag_valid = HI_RESET_FLAG_IS_VALID) 413 414 #define RESET_FLAGS_INVALIDATE() \ 415 (HOST_INTEREST->hi_reset_flag_valid = 0) 416 417 #define ON_RESET_PRESERVE_APP_START() \ 418 (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_APP_START) 419 420 #define ON_RESET_PRESERVE_NVRAM_STATE() \ 421 (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_NVRAM_STATE) 422 423 #define ON_RESET_PRESERVE_HOST_INTEREST() \ 424 (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_HOST_INTEREST) 425 426 #define ON_RESET_PRESERVE_ROMDATA() \ 427 (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_ROMDATA) 428 429 #define ON_RESET_PRESERVE_BOOT_INFO() \ 430 (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_BOOT_INFO) 431 432 #define ON_RESET_WARM_RESET() \ 433 (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_WARM_RESET) 434 435 /* host CPU endianness */ 436 #define HOST_ON_BE_CPU() \ 437 (HOST_INTEREST->hi_be) 438 439 /* AP nart no swap descriptor flag. Decsriptors are created on the target processor. */ 440 #define DESC_IN_FW() \ 441 (HOST_INTEREST->hi_fw_swap & HI_DESC_IN_FW_BIT) 442 443 444 /* redefine for hi_acs_flags since no product ever use it 445 * NOTE: 446 * This flag was only used in AR6004 for a customer project that has 447 * been canceled, we are reusing it to avoid extending the Host interest 448 * area. 449 * BIT Range Meaning 450 * --------- ---------------------------------- 451 * 0 HOST wants to swap MBOX usage 452 * 1 HOST supports HTT reduced tx completion 453 * 2 HOST supports HTT alternate credit size for data frames 454 * 15..3 reserved for HOST 455 * 16 FW set it before sending HTC_Ready to HOST to indicate MBOX swap is done 456 * 17 same as above but to indicate HTT reduced tx completion capability 457 * 31..18 reserved for FW 458 */ 459 #define HI_ACS_FLAGS_HOST_SWAP_MBOX (1 << 0) /* HOST require to swap MBOX */ 460 #define HI_ACS_FLAGS_HOST_REDUCE_TX_COMPL (1 << 1) /* HOST supports HTT reduced tx completion */ 461 #define HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE (1 << 2) /* HOST supports alternate credit size for data frames */ 462 #define HI_ACS_FLAGS_FW_SWAPPED_MBOX (1 << 16) /* FW swapped MBOX */ 463 #define HI_ACS_FLAGS_FW_REDUCE_TX_COMPL (1 << 17) /* FW support HTT reduced tx completion */ 464 465 /* CONSOLE FLAGS 466 * 467 * Bit Range Meaning 468 * --------- -------------------------------- 469 * 2..0 UART ID (0 = Default) 470 * 3 Baud Select (0 = 9600, 1 = 115200) 471 * 30..4 Reserved 472 * 31 Enable Console 473 * 474 * */ 475 476 #define HI_CONSOLE_FLAGS_ENABLE (1 << 31) 477 #define HI_CONSOLE_FLAGS_UART_MASK (0x7) 478 #define HI_CONSOLE_FLAGS_UART_SHIFT 0 479 #define HI_CONSOLE_FLAGS_BAUD_SELECT (1 << 3) 480 481 /* SM power save options */ 482 #define HI_SMPS_ALLOW_MASK (0x00000001) 483 #define HI_SMPS_MODE_MASK (0x00000002) 484 #define HI_SMPS_MODE_STATIC (0x00000000) 485 #define HI_SMPS_MODE_DYNAMIC (0x00000002) 486 #define HI_SMPS_DISABLE_AUTO_MODE (0x00000004) 487 #define HI_SMPS_DATA_THRESH_MASK (0x000007f8) 488 #define HI_SMPS_DATA_THRESH_SHIFT (3) 489 #define HI_SMPS_RSSI_THRESH_MASK (0x0007f800) 490 #define HI_SMPS_RSSI_THRESH_SHIFT (11) 491 #define HI_SMPS_LOWPWR_CM_MASK (0x00380000) 492 #define HI_SMPS_LOWPWR_CM_SHIFT (15) 493 #define HI_SMPS_HIPWR_CM_MASK (0x03c00000) 494 #define HI_SMPS_HIPWR_CM_SHIFT (19) 495 496 #define HOST_INTEREST_SMPS_GET_MODE() (HOST_INTEREST->hi_smps_options & HI_SMPS_MODE_MASK) 497 #define HOST_INTEREST_SMPS_GET_DATA_THRESH() ((HOST_INTEREST->hi_smps_options & HI_SMPS_DATA_THRESH_MASK) >> HI_SMPS_DATA_THRESH_SHIFT) 498 #define HOST_INTEREST_SMPS_SET_DATA_THRESH(x) (((x) << HI_SMPS_DATA_THRESH_SHIFT) & HI_SMPS_DATA_THRESH_MASK) 499 #define HOST_INTEREST_SMPS_GET_RSSI_THRESH() ((HOST_INTEREST->hi_smps_options & HI_SMPS_RSSI_THRESH_MASK) >> HI_SMPS_RSSI_THRESH_SHIFT) 500 #define HOST_INTEREST_SMPS_SET_RSSI_THRESH(x) (((x) << HI_SMPS_RSSI_THRESH_SHIFT) & HI_SMPS_RSSI_THRESH_MASK) 501 #define HOST_INTEREST_SMPS_SET_LOWPWR_CM() ((HOST_INTEREST->hi_smps_options & HI_SMPS_LOWPWR_CM_MASK) >> HI_SMPS_LOWPWR_CM_SHIFT) 502 #define HOST_INTEREST_SMPS_SET_HIPWR_CM() ((HOST_INTEREST->hi_smps_options << HI_SMPS_HIPWR_CM_MASK) & HI_SMPS_HIPWR_CM_SHIFT) 503 #define HOST_INTEREST_SMPS_IS_AUTO_MODE_DISABLED() (HOST_INTEREST->hi_smps_options & HI_SMPS_DISABLE_AUTO_MODE) 504 505 506 /* WOW Extension configuration 507 * 508 * Bit Range Meaning 509 * --------- -------------------------------- 510 * 8..0 Size of each WOW pattern (max 511) 511 * 15..9 Number of patterns per list (max 127) 512 * 17..16 Number of lists (max 4) 513 * 30..18 Reserved 514 * 31 Enabled 515 * 516 * set values (except enable) to zeros for default settings 517 * 518 * */ 519 520 #define HI_WOW_EXT_ENABLED_MASK (1 << 31) 521 #define HI_WOW_EXT_NUM_LIST_SHIFT 16 522 #define HI_WOW_EXT_NUM_LIST_MASK (0x3 << HI_WOW_EXT_NUM_LIST_SHIFT) 523 #define HI_WOW_EXT_NUM_PATTERNS_SHIFT 9 524 #define HI_WOW_EXT_NUM_PATTERNS_MASK (0x7F << HI_WOW_EXT_NUM_PATTERNS_SHIFT) 525 #define HI_WOW_EXT_PATTERN_SIZE_SHIFT 0 526 #define HI_WOW_EXT_PATTERN_SIZE_MASK (0x1FF << HI_WOW_EXT_PATTERN_SIZE_SHIFT) 527 528 #define HI_WOW_EXT_MAKE_CONFIG(num_lists,count,size) \ 529 ((((num_lists) << HI_WOW_EXT_NUM_LIST_SHIFT) & HI_WOW_EXT_NUM_LIST_MASK) | \ 530 (((count) << HI_WOW_EXT_NUM_PATTERNS_SHIFT) & HI_WOW_EXT_NUM_PATTERNS_MASK) | \ 531 (((size) << HI_WOW_EXT_PATTERN_SIZE_SHIFT) & HI_WOW_EXT_PATTERN_SIZE_MASK)) 532 533 #define HI_WOW_EXT_GET_NUM_LISTS(config) \ 534 (((config) & HI_WOW_EXT_NUM_LIST_MASK) >> HI_WOW_EXT_NUM_LIST_SHIFT) 535 #define HI_WOW_EXT_GET_NUM_PATTERNS(config) \ 536 (((config) & HI_WOW_EXT_NUM_PATTERNS_MASK) >> HI_WOW_EXT_NUM_PATTERNS_SHIFT) 537 #define HI_WOW_EXT_GET_PATTERN_SIZE(config) \ 538 (((config) & HI_WOW_EXT_PATTERN_SIZE_MASK) >> HI_WOW_EXT_PATTERN_SIZE_SHIFT) 539 540 /* 541 * Early allocation configuration 542 * Support RAM bank configuration before BMI done and this eases the memory 543 * allocation at very early stage 544 * Bit Range Meaning 545 * --------- ---------------------------------- 546 * [0:3] number of bank assigned to be IRAM 547 * [4:15] reserved 548 * [16:31] magic number 549 * 550 * Note: 551 * 1. target firmware would check magic number and if it's a match, firmware 552 * would consider the bits[0:15] are valid and base on that to calculate 553 * the end of DRAM. Early allocation would be located at that area and 554 * may be reclaimed when necesary 555 * 2. if no magic number is found, early allocation would happen at "_end" 556 * symbol of ROM which is located before the app-data and might NOT be 557 * re-claimable. If this is adopted, link script should keep this in 558 * mind to avoid data corruption. 559 */ 560 #define HI_EARLY_ALLOC_MAGIC 0x6d8a 561 #define HI_EARLY_ALLOC_MAGIC_MASK 0xffff0000 562 #define HI_EARLY_ALLOC_MAGIC_SHIFT 16 563 #define HI_EARLY_ALLOC_IRAM_BANKS_MASK 0x0000000f 564 #define HI_EARLY_ALLOC_IRAM_BANKS_SHIFT 0 565 566 #define HI_EARLY_ALLOC_VALID() \ 567 ((((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_MAGIC_MASK) >> HI_EARLY_ALLOC_MAGIC_SHIFT) \ 568 == (HI_EARLY_ALLOC_MAGIC)) 569 #define HI_EARLY_ALLOC_GET_IRAM_BANKS() \ 570 (((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_IRAM_BANKS_MASK) >> HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) 571 572 /* 573 * Intended for use by Host software, this macro returns the Target RAM 574 * address of any item in the host_interest structure. 575 * Example: target_addr = AR6002_HOST_INTEREST_ITEM_ADDRESS(hi_board_data); 576 */ 577 #define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \ 578 (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item))) 579 580 #define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \ 581 (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item))) 582 583 #define AR6004_HOST_INTEREST_ITEM_ADDRESS(item) \ 584 (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6004_HOST_INTEREST_ADDRESS))->item))) 585 586 #define AR6006_HOST_INTEREST_ITEM_ADDRESS(item) \ 587 (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6006_HOST_INTEREST_ADDRESS))->item))) 588 589 #define AR9888_HOST_INTEREST_ITEM_ADDRESS(item) \ 590 (A_UINT32)((size_t)&((((struct host_interest_s *)(AR9888_HOST_INTEREST_ADDRESS))->item))) 591 592 #define AR6320_HOST_INTEREST_ITEM_ADDRESS(item) \ 593 (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6320_HOST_INTEREST_ADDRESS))->item))) 594 595 #define AR900B_HOST_INTEREST_ITEM_ADDRESS(item) \ 596 (A_UINT32)((size_t)&((((struct host_interest_s *)(AR900B_HOST_INTEREST_ADDRESS))->item))) 597 598 #define HOST_INTEREST_DBGLOG_IS_ENABLED() \ 599 (!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG)) 600 601 #define HOST_INTEREST_PKTLOG_IS_ENABLED() \ 602 ((HOST_INTEREST->hi_pktlog_num_buffers)) 603 604 #define HOST_INTEREST_PROFILE_IS_ENABLED() \ 605 (HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE) 606 607 #define LF_TIMER_STABILIZATION_IS_ENABLED() \ 608 (!(HOST_INTEREST->hi_option_flag & HI_OPTION_NO_LFT_STBL)) 609 610 #define IS_AMSDU_OFFLAOD_ENABLED() \ 611 ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_OFFLOAD_AMSDU)) 612 613 #define HOST_INTEREST_DFS_IS_ENABLED() \ 614 ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_DFS_SUPPORT)) 615 616 #define HOST_INTEREST_EARLY_CFG_DONE() \ 617 ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_EARLY_CFG_DONE)) 618 619 /*power save flag bit definitions*/ 620 #define HI_PWR_SAVE_LPL_ENABLED 0x1 621 /*b1-b3 reserved*/ 622 /*b4-b5 : dev0 LPL type : 0 - none 623 1- Reduce Pwr Search 624 2- Reduce Pwr Listen*/ 625 /*b6-b7 : dev1 LPL type and so on for Max 8 devices*/ 626 #define HI_PWR_SAVE_LPL_DEV0_LSB 4 627 #define HI_PWR_SAVE_LPL_DEV_MASK 0x3 628 /*power save related utility macros*/ 629 #define HI_LPL_ENABLED() \ 630 ((HOST_INTEREST->hi_pwr_save_flags & HI_PWR_SAVE_LPL_ENABLED)) 631 #define HI_DEV_LPL_TYPE_GET(_devix) \ 632 (HOST_INTEREST->hi_pwr_save_flags & \ 633 ((HI_PWR_SAVE_LPL_DEV_MASK) << \ 634 (HI_PWR_SAVE_LPL_DEV0_LSB + \ 635 (_devix)*2))) 636 637 #define HOST_INTEREST_SMPS_IS_ALLOWED() \ 638 ((HOST_INTEREST->hi_smps_options & HI_SMPS_ALLOW_MASK)) 639 640 /* Convert a Target virtual address into a Target physical address */ 641 #define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff) 642 #define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff) 643 #define AR6004_VTOP(vaddr) (vaddr) 644 #define AR6006_VTOP(vaddr) (vaddr) 645 #define AR9888_VTOP(vaddr) (vaddr) 646 #define AR6320_VTOP(vaddr) (vaddr) 647 #define AR900B_VTOP(vaddr) (vaddr) 648 #define TARG_VTOP(TargetType, vaddr) \ 649 (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : \ 650 (((TargetType) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \ 651 (((TargetType) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : \ 652 (((TargetType) == TARGET_TYPE_AR6006) ? AR6006_VTOP(vaddr) : \ 653 (((TargetType) == TARGET_TYPE_AR9888) ? AR9888_VTOP(vaddr) : \ 654 (((TargetType) == TARGET_TYPE_AR6320) ? AR6320_VTOP(vaddr) : \ 655 (((TargetType) == TARGET_TYPE_AR900B) ? AR900B_VTOP(vaddr) : \ 656 0))))))) 657 658 #define HOST_INTEREST_ITEM_ADDRESS(TargetType, item) \ 659 (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \ 660 (((TargetType) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : \ 661 (((TargetType) == TARGET_TYPE_AR6004) ? AR6004_HOST_INTEREST_ITEM_ADDRESS(item) : \ 662 (((TargetType) == TARGET_TYPE_AR6006) ? AR6006_HOST_INTEREST_ITEM_ADDRESS(item) : \ 663 (((TargetType) == TARGET_TYPE_AR9888) ? AR9888_HOST_INTEREST_ITEM_ADDRESS(item) : \ 664 (((TargetType) == TARGET_TYPE_AR6320) ? AR6320_HOST_INTEREST_ITEM_ADDRESS(item) : \ 665 (((TargetType) == TARGET_TYPE_AR900B) ? AR900B_HOST_INTEREST_ITEM_ADDRESS(item) : \ 666 0))))))) 667 668 #define AR6002_BOARD_DATA_SZ 768 669 #define AR6002_BOARD_EXT_DATA_SZ 0 670 #define AR6003_BOARD_DATA_SZ 1024 671 /* Reserve 1024 bytes for extended board data */ 672 #if defined(AR6002_REV43) 673 #define AR6003_BOARD_EXT_DATA_SZ 1024 674 #else 675 #define AR6003_BOARD_EXT_DATA_SZ 768 676 #endif 677 #define AR6004_BOARD_DATA_SZ 7168 678 #define AR6004_BOARD_EXT_DATA_SZ 0 679 #define AR9888_BOARD_DATA_SZ 7168 680 #define AR9888_BOARD_EXT_DATA_SZ 0 681 #define AR6320_BOARD_DATA_SZ 8192 682 #define AR6320_BOARD_EXT_DATA_SZ 0 683 #define QCA9377_BOARD_DATA_SZ 8192 684 #define QCA9377_BOARD_EXT_DATA_SZ 0 685 #define AR900B_BOARD_DATA_SZ (14 * 1024) 686 #define AR900B_BOARD_EXT_DATA_SZ 0 687 #define QCA9984_BOARD_DATA_SZ (14 * 1024) 688 #define QCA9984_BOARD_EXT_DATA_SZ 0 689 #define QCA9888_BOARD_DATA_SZ (14 * 1024) 690 #define QCA9888_BOARD_EXT_DATA_SZ 0 691 #define IPQ4019_BOARD_DATA_SZ (14 * 1024) 692 #define IPQ4019_BOARD_EXT_DATA_SZ 0 693 694 /* Allocate board data right at the begining of AXI SRAM, 695 * Current size for beeliner is 14K. 696 * Allocate it towards the end of DRAM, until AXI SRAM is functional. 697 */ 698 #define AR900B_BOARD_DATA_ADDR 0xc0000 699 #define QCA9984_BOARD_DATA_ADDR 0xc0000 700 #define QCA9888_BOARD_DATA_ADDR 0xc0000 701 #define IPQ4019_BOARD_DATA_ADDR 0xc0000 702 703 #define AR6003_REV3_APP_START_OVERRIDE 0x946100 704 #define AR6003_REV3_APP_LOAD_ADDRESS 0x545000 705 #define AR6003_REV3_BOARD_EXT_DATA_ADDRESS 0x542330 706 #define AR6003_REV3_DATASET_PATCH_ADDRESS 0x57FF74 707 #define AR6003_REV3_RAM_RESERVE_SIZE 4096 708 709 #define AR6004_REV1_BOARD_DATA_ADDRESS 0x423900 710 #define AR6004_REV1_RAM_RESERVE_SIZE 19456 711 #define AR6004_REV1_DATASET_PATCH_ADDRESS 0x425294 712 713 #define AR6004_REV2_BOARD_DATA_ADDRESS 0x426400 714 #define AR6004_REV2_RAM_RESERVE_SIZE 7168 715 #define AR6004_REV2_DATASET_PATCH_ADDRESS 0x435294 716 717 #define AR6004_REV5_BOARD_DATA_ADDRESS 0x436400 718 #define AR6004_REV5_RAM_RESERVE_SIZE 7168 719 #define AR6004_REV5_DATASET_PATCH_ADDRESS 0x437860 720 721 /* Reserve 4K for OTA test script */ 722 #define AR6004_REV1_RAM_RESERVE_SIZE_FOR_TEST_SCRIPT 4096 723 #define AR6004_REV1_TEST_SCRIPT_ADDRESS 0x422900 724 725 /* # of A_UINT32 entries in targregs, used by DIAG_FETCH_TARG_REGS */ 726 #define AR6003_FETCH_TARG_REGS_COUNT 64 727 #define AR6004_FETCH_TARG_REGS_COUNT 64 728 #define AR9888_FETCH_TARG_REGS_COUNT 64 729 #define AR6320_FETCH_TARG_REGS_COUNT 64 730 #define AR900B_FETCH_TARG_REGS_COUNT 64 731 732 #endif /* !__ASSEMBLER__ */ 733 734 #ifndef ATH_TARGET 735 #include "athendpack.h" 736 #endif 737 738 #endif /* __TARGADDRS_H__ */ 739