| /wlan-driver/qca-wifi-host-cmn/hif/src/ |
| H A D | qcn6122def.c | 29 #define MISSING 0 macro
31 #define SOC_RESET_CONTROL_OFFSET MISSING
32 #define GPIO_PIN0_OFFSET MISSING
33 #define GPIO_PIN1_OFFSET MISSING
34 #define GPIO_PIN0_CONFIG_MASK MISSING
35 #define GPIO_PIN1_CONFIG_MASK MISSING
37 #define GPIO_PIN10_OFFSET MISSING
38 #define GPIO_PIN11_OFFSET MISSING
39 #define GPIO_PIN12_OFFSET MISSING
40 #define GPIO_PIN13_OFFSET MISSING
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| H A D | qca6018def.c | 30 #define MISSING 0 macro
32 #define SOC_RESET_CONTROL_OFFSET MISSING
33 #define GPIO_PIN0_OFFSET MISSING
34 #define GPIO_PIN1_OFFSET MISSING
35 #define GPIO_PIN0_CONFIG_MASK MISSING
36 #define GPIO_PIN1_CONFIG_MASK MISSING
38 #define GPIO_PIN10_OFFSET MISSING
39 #define GPIO_PIN11_OFFSET MISSING
40 #define GPIO_PIN12_OFFSET MISSING
41 #define GPIO_PIN13_OFFSET MISSING
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| H A D | qca8074v2def.c | 30 #define MISSING 0 macro
32 #define SOC_RESET_CONTROL_OFFSET MISSING
33 #define GPIO_PIN0_OFFSET MISSING
34 #define GPIO_PIN1_OFFSET MISSING
35 #define GPIO_PIN0_CONFIG_MASK MISSING
36 #define GPIO_PIN1_CONFIG_MASK MISSING
38 #define GPIO_PIN10_OFFSET MISSING
39 #define GPIO_PIN11_OFFSET MISSING
40 #define GPIO_PIN12_OFFSET MISSING
41 #define GPIO_PIN13_OFFSET MISSING
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| H A D | qca8074def.c | 30 #define MISSING 0 macro
32 #define SOC_RESET_CONTROL_OFFSET MISSING
33 #define GPIO_PIN0_OFFSET MISSING
34 #define GPIO_PIN1_OFFSET MISSING
35 #define GPIO_PIN0_CONFIG_MASK MISSING
36 #define GPIO_PIN1_CONFIG_MASK MISSING
38 #define GPIO_PIN10_OFFSET MISSING
39 #define GPIO_PIN11_OFFSET MISSING
40 #define GPIO_PIN12_OFFSET MISSING
41 #define GPIO_PIN13_OFFSET MISSING
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| H A D | qcn6432def.c | 28 #define MISSING 0 macro
30 #define SOC_RESET_CONTROL_OFFSET MISSING
31 #define GPIO_PIN0_OFFSET MISSING
32 #define GPIO_PIN1_OFFSET MISSING
33 #define GPIO_PIN0_CONFIG_MASK MISSING
34 #define GPIO_PIN1_CONFIG_MASK MISSING
36 #define GPIO_PIN10_OFFSET MISSING
37 #define GPIO_PIN11_OFFSET MISSING
38 #define GPIO_PIN12_OFFSET MISSING
39 #define GPIO_PIN13_OFFSET MISSING
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| H A D | qca5332def.c | 28 #define MISSING 0 macro
30 #define SOC_RESET_CONTROL_OFFSET MISSING
31 #define GPIO_PIN0_OFFSET MISSING
32 #define GPIO_PIN1_OFFSET MISSING
33 #define GPIO_PIN0_CONFIG_MASK MISSING
34 #define GPIO_PIN1_CONFIG_MASK MISSING
36 #define GPIO_PIN10_OFFSET MISSING
37 #define GPIO_PIN11_OFFSET MISSING
38 #define GPIO_PIN12_OFFSET MISSING
39 #define GPIO_PIN13_OFFSET MISSING
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| H A D | qca6290def.c | 27 #define MISSING 0 macro
29 #define SOC_RESET_CONTROL_OFFSET MISSING
30 #define GPIO_PIN0_OFFSET MISSING
31 #define GPIO_PIN1_OFFSET MISSING
32 #define GPIO_PIN0_CONFIG_MASK MISSING
33 #define GPIO_PIN1_CONFIG_MASK MISSING
35 #define GPIO_PIN10_OFFSET MISSING
36 #define GPIO_PIN11_OFFSET MISSING
37 #define GPIO_PIN12_OFFSET MISSING
38 #define GPIO_PIN13_OFFSET MISSING
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| H A D | qca6490def.c | 27 #define MISSING 0 macro
29 #define SOC_RESET_CONTROL_OFFSET MISSING
30 #define GPIO_PIN0_OFFSET MISSING
31 #define GPIO_PIN1_OFFSET MISSING
32 #define GPIO_PIN0_CONFIG_MASK MISSING
33 #define GPIO_PIN1_CONFIG_MASK MISSING
35 #define GPIO_PIN10_OFFSET MISSING
36 #define GPIO_PIN11_OFFSET MISSING
37 #define GPIO_PIN12_OFFSET MISSING
38 #define GPIO_PIN13_OFFSET MISSING
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| H A D | qca6390def.c | 27 #define MISSING 0 macro
29 #define SOC_RESET_CONTROL_OFFSET MISSING
30 #define GPIO_PIN0_OFFSET MISSING
31 #define GPIO_PIN1_OFFSET MISSING
32 #define GPIO_PIN0_CONFIG_MASK MISSING
33 #define GPIO_PIN1_CONFIG_MASK MISSING
35 #define GPIO_PIN10_OFFSET MISSING
36 #define GPIO_PIN11_OFFSET MISSING
37 #define GPIO_PIN12_OFFSET MISSING
38 #define GPIO_PIN13_OFFSET MISSING
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| H A D | qca6750def.c | 25 #define MISSING 0 macro
27 #define SOC_RESET_CONTROL_OFFSET MISSING
28 #define GPIO_PIN0_OFFSET MISSING
29 #define GPIO_PIN1_OFFSET MISSING
30 #define GPIO_PIN0_CONFIG_MASK MISSING
31 #define GPIO_PIN1_CONFIG_MASK MISSING
33 #define GPIO_PIN10_OFFSET MISSING
34 #define GPIO_PIN11_OFFSET MISSING
35 #define GPIO_PIN12_OFFSET MISSING
36 #define GPIO_PIN13_OFFSET MISSING
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| H A D | qcn9160def.c | 26 #define MISSING 0 macro
28 #define SOC_RESET_CONTROL_OFFSET MISSING
29 #define GPIO_PIN0_OFFSET MISSING
30 #define GPIO_PIN1_OFFSET MISSING
31 #define GPIO_PIN0_CONFIG_MASK MISSING
32 #define GPIO_PIN1_CONFIG_MASK MISSING
34 #define GPIO_PIN10_OFFSET MISSING
35 #define GPIO_PIN11_OFFSET MISSING
36 #define GPIO_PIN12_OFFSET MISSING
37 #define GPIO_PIN13_OFFSET MISSING
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| H A D | kiwidef.c | 28 #define MISSING 0 macro
30 #define SOC_RESET_CONTROL_OFFSET MISSING
31 #define GPIO_PIN0_OFFSET MISSING
32 #define GPIO_PIN1_OFFSET MISSING
33 #define GPIO_PIN0_CONFIG_MASK MISSING
34 #define GPIO_PIN1_CONFIG_MASK MISSING
36 #define GPIO_PIN10_OFFSET MISSING
37 #define GPIO_PIN11_OFFSET MISSING
38 #define GPIO_PIN12_OFFSET MISSING
39 #define GPIO_PIN13_OFFSET MISSING
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| H A D | qcn9224def.c | 30 #define MISSING 0 macro
32 #define SOC_RESET_CONTROL_OFFSET MISSING
33 #define GPIO_PIN0_OFFSET MISSING
34 #define GPIO_PIN1_OFFSET MISSING
35 #define GPIO_PIN0_CONFIG_MASK MISSING
36 #define GPIO_PIN1_CONFIG_MASK MISSING
38 #define GPIO_PIN10_OFFSET MISSING
39 #define GPIO_PIN11_OFFSET MISSING
40 #define GPIO_PIN12_OFFSET MISSING
41 #define GPIO_PIN13_OFFSET MISSING
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| H A D | qca5018def.c | 30 #define MISSING 0 macro
32 #define SOC_RESET_CONTROL_OFFSET MISSING
33 #define GPIO_PIN0_OFFSET MISSING
34 #define GPIO_PIN1_OFFSET MISSING
35 #define GPIO_PIN0_CONFIG_MASK MISSING
36 #define GPIO_PIN1_CONFIG_MASK MISSING
38 #define GPIO_PIN10_OFFSET MISSING
39 #define GPIO_PIN11_OFFSET MISSING
40 #define GPIO_PIN12_OFFSET MISSING
41 #define GPIO_PIN13_OFFSET MISSING
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| H A D | qcn9000def.c | 30 #define MISSING 0 macro
32 #define SOC_RESET_CONTROL_OFFSET MISSING
33 #define GPIO_PIN0_OFFSET MISSING
34 #define GPIO_PIN1_OFFSET MISSING
35 #define GPIO_PIN0_CONFIG_MASK MISSING
36 #define GPIO_PIN1_CONFIG_MASK MISSING
38 #define GPIO_PIN10_OFFSET MISSING
39 #define GPIO_PIN11_OFFSET MISSING
40 #define GPIO_PIN12_OFFSET MISSING
41 #define GPIO_PIN13_OFFSET MISSING
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| H A D | qca9574def.c | 28 #define MISSING 0 macro
30 #define SOC_RESET_CONTROL_OFFSET MISSING
31 #define GPIO_PIN0_OFFSET MISSING
32 #define GPIO_PIN1_OFFSET MISSING
33 #define GPIO_PIN0_CONFIG_MASK MISSING
34 #define GPIO_PIN1_CONFIG_MASK MISSING
36 #define GPIO_PIN10_OFFSET MISSING
37 #define GPIO_PIN11_OFFSET MISSING
38 #define GPIO_PIN12_OFFSET MISSING
39 #define GPIO_PIN13_OFFSET MISSING
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| H A D | ar9888def.c | 56 #define MISSING 0 macro
63 #define RESET_CONTROL_MBOX_RST_MASK MISSING
84 #define MBOX_BASE_ADDRESS MISSING
85 #define INT_STATUS_ENABLE_ERROR_LSB MISSING
86 #define INT_STATUS_ENABLE_ERROR_MASK MISSING
87 #define INT_STATUS_ENABLE_CPU_LSB MISSING
88 #define INT_STATUS_ENABLE_CPU_MASK MISSING
89 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING
90 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING
91 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
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| H A D | ar900Bdef.c | 71 #define MISSING 0 macro
110 #define MBOX_BASE_ADDRESS MISSING
111 #define INT_STATUS_ENABLE_ERROR_LSB MISSING
112 #define INT_STATUS_ENABLE_ERROR_MASK MISSING
113 #define INT_STATUS_ENABLE_CPU_LSB MISSING
114 #define INT_STATUS_ENABLE_CPU_MASK MISSING
115 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING
116 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING
117 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
118 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
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| H A D | qca9888def.c | 67 #define MISSING 0 macro
106 #define MBOX_BASE_ADDRESS MISSING
107 #define INT_STATUS_ENABLE_ERROR_LSB MISSING
108 #define INT_STATUS_ENABLE_ERROR_MASK MISSING
109 #define INT_STATUS_ENABLE_CPU_LSB MISSING
110 #define INT_STATUS_ENABLE_CPU_MASK MISSING
111 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING
112 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING
113 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
114 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
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| H A D | qca9984def.c | 68 #define MISSING 0 macro
107 #define MBOX_BASE_ADDRESS MISSING
108 #define INT_STATUS_ENABLE_ERROR_LSB MISSING
109 #define INT_STATUS_ENABLE_ERROR_MASK MISSING
110 #define INT_STATUS_ENABLE_CPU_LSB MISSING
111 #define INT_STATUS_ENABLE_CPU_MASK MISSING
112 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING
113 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING
114 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
115 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
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| H A D | ar9888def.h | 226 #define AR9888_RESET_CONTROL_MBOX_RST_MASK MISSING
246 #define AR9888_MBOX_BASE_ADDRESS MISSING
247 #define AR9888_INT_STATUS_ENABLE_ERROR_LSB MISSING
248 #define AR9888_INT_STATUS_ENABLE_ERROR_MASK MISSING
249 #define AR9888_INT_STATUS_ENABLE_CPU_LSB MISSING
250 #define AR9888_INT_STATUS_ENABLE_CPU_MASK MISSING
251 #define AR9888_INT_STATUS_ENABLE_COUNTER_LSB MISSING
252 #define AR9888_INT_STATUS_ENABLE_COUNTER_MASK MISSING
253 #define AR9888_INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
254 #define AR9888_INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
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| H A D | wcn6450def.h | 171 #define WCN6450_MISC_IS_DST_ADDR_ERR_MASK MISSING
172 #define WCN6450_CE_WRAPPER_DEBUG_OFFSET MISSING
173 #define WCN6450_CE_WRAPPER_DEBUG_SEL_MSB MISSING
174 #define WCN6450_CE_WRAPPER_DEBUG_SEL_LSB MISSING
175 #define WCN6450_CE_WRAPPER_DEBUG_SEL_MASK MISSING
176 #define WCN6450_CE_DEBUG_OFFSET MISSING
177 #define WCN6450_CE_DEBUG_SEL_MSB MISSING
178 #define WCN6450_CE_DEBUG_SEL_LSB MISSING
179 #define WCN6450_CE_DEBUG_SEL_MASK MISSING
180 #define MISSING_FOR_WCN6450 MISSING
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| H A D | adrastea_reg_def.h | 1187 #define MISSING 0 macro
1188 #define MISSING_FOR_ADRASTEA MISSING
1200 #define ADRASTEA_MAC_WIFICMN_REG_BASE_ADDRESS MISSING
1245 #define ADRASTEA_A_SOC_PCIE_SOC_PCIE_REG MISSING
1246 #define ADRASTEA_DBI_BASE_ADDRESS MISSING
1247 #define ADRASTEA_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS MISSING
1248 #define ADRASTEA_WIFICMN_BASE_ADDRESS MISSING
1249 #define ADRASTEA_BOARD_DATA_SZ MISSING
1250 #define ADRASTEA_BOARD_EXT_DATA_SZ MISSING
1251 #define ADRASTEA_A_SOC_PCIE_PCIE_BAR0_START MISSING
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| /wlan-driver/qca-wifi-host-cmn/hif/src/sdio/ |
| H A D | regtable_sdio.c | 23 #define MISSING 0 macro
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| /wlan-driver/qca-wifi-host-cmn/hif/inc/ |
| H A D | regtable_pcie.h | 22 #define MISSING 0 macro
|