1 /* 2 * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved. 3 * 4 * Previously licensed under the ISC license by Qualcomm Atheros, Inc. 5 * 6 * 7 * Permission to use, copy, modify, and/or distribute this software for 8 * any purpose with or without fee is hereby granted, provided that the 9 * above copyright notice and this permission notice appear in all 10 * copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 13 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 14 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 15 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 16 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 17 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 18 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 19 * PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* 23 * This file was originally distributed by Qualcomm Atheros, Inc. 24 * under proprietary terms before Copyright ownership was assigned 25 * to the Linux Foundation. 26 */ 27 28 #ifndef _EFUSE_REG_REG_H_ 29 #define _EFUSE_REG_REG_H_ 30 31 #define EFUSE_WR_ENABLE_REG_ADDRESS 0x00000000 32 #define EFUSE_WR_ENABLE_REG_OFFSET 0x00000000 33 #define EFUSE_WR_ENABLE_REG_V_MSB 0 34 #define EFUSE_WR_ENABLE_REG_V_LSB 0 35 #define EFUSE_WR_ENABLE_REG_V_MASK 0x00000001 36 #define EFUSE_WR_ENABLE_REG_V_GET(x) (((x) & EFUSE_WR_ENABLE_REG_V_MASK) >> EFUSE_WR_ENABLE_REG_V_LSB) 37 #define EFUSE_WR_ENABLE_REG_V_SET(x) (((x) << EFUSE_WR_ENABLE_REG_V_LSB) & EFUSE_WR_ENABLE_REG_V_MASK) 38 39 #define EFUSE_INT_ENABLE_REG_ADDRESS 0x00000004 40 #define EFUSE_INT_ENABLE_REG_OFFSET 0x00000004 41 #define EFUSE_INT_ENABLE_REG_V_MSB 0 42 #define EFUSE_INT_ENABLE_REG_V_LSB 0 43 #define EFUSE_INT_ENABLE_REG_V_MASK 0x00000001 44 #define EFUSE_INT_ENABLE_REG_V_GET(x) (((x) & EFUSE_INT_ENABLE_REG_V_MASK) >> EFUSE_INT_ENABLE_REG_V_LSB) 45 #define EFUSE_INT_ENABLE_REG_V_SET(x) (((x) << EFUSE_INT_ENABLE_REG_V_LSB) & EFUSE_INT_ENABLE_REG_V_MASK) 46 47 #define EFUSE_INT_STATUS_REG_ADDRESS 0x00000008 48 #define EFUSE_INT_STATUS_REG_OFFSET 0x00000008 49 #define EFUSE_INT_STATUS_REG_V_MSB 0 50 #define EFUSE_INT_STATUS_REG_V_LSB 0 51 #define EFUSE_INT_STATUS_REG_V_MASK 0x00000001 52 #define EFUSE_INT_STATUS_REG_V_GET(x) (((x) & EFUSE_INT_STATUS_REG_V_MASK) >> EFUSE_INT_STATUS_REG_V_LSB) 53 #define EFUSE_INT_STATUS_REG_V_SET(x) (((x) << EFUSE_INT_STATUS_REG_V_LSB) & EFUSE_INT_STATUS_REG_V_MASK) 54 55 #define BITMASK_WR_REG_ADDRESS 0x0000000c 56 #define BITMASK_WR_REG_OFFSET 0x0000000c 57 #define BITMASK_WR_REG_V_MSB 31 58 #define BITMASK_WR_REG_V_LSB 0 59 #define BITMASK_WR_REG_V_MASK 0xffffffff 60 #define BITMASK_WR_REG_V_GET(x) (((x) & BITMASK_WR_REG_V_MASK) >> BITMASK_WR_REG_V_LSB) 61 #define BITMASK_WR_REG_V_SET(x) (((x) << BITMASK_WR_REG_V_LSB) & BITMASK_WR_REG_V_MASK) 62 63 #define VDDQ_SETTLE_TIME_REG_ADDRESS 0x00000010 64 #define VDDQ_SETTLE_TIME_REG_OFFSET 0x00000010 65 #define VDDQ_SETTLE_TIME_REG_V_MSB 31 66 #define VDDQ_SETTLE_TIME_REG_V_LSB 0 67 #define VDDQ_SETTLE_TIME_REG_V_MASK 0xffffffff 68 #define VDDQ_SETTLE_TIME_REG_V_GET(x) (((x) & VDDQ_SETTLE_TIME_REG_V_MASK) >> VDDQ_SETTLE_TIME_REG_V_LSB) 69 #define VDDQ_SETTLE_TIME_REG_V_SET(x) (((x) << VDDQ_SETTLE_TIME_REG_V_LSB) & VDDQ_SETTLE_TIME_REG_V_MASK) 70 71 #define VDDQ_HOLD_TIME_REG_ADDRESS 0x00000014 72 #define VDDQ_HOLD_TIME_REG_OFFSET 0x00000014 73 #define VDDQ_HOLD_TIME_REG_V_MSB 31 74 #define VDDQ_HOLD_TIME_REG_V_LSB 0 75 #define VDDQ_HOLD_TIME_REG_V_MASK 0xffffffff 76 #define VDDQ_HOLD_TIME_REG_V_GET(x) (((x) & VDDQ_HOLD_TIME_REG_V_MASK) >> VDDQ_HOLD_TIME_REG_V_LSB) 77 #define VDDQ_HOLD_TIME_REG_V_SET(x) (((x) << VDDQ_HOLD_TIME_REG_V_LSB) & VDDQ_HOLD_TIME_REG_V_MASK) 78 79 #define RD_STROBE_PW_REG_ADDRESS 0x00000018 80 #define RD_STROBE_PW_REG_OFFSET 0x00000018 81 #define RD_STROBE_PW_REG_V_MSB 31 82 #define RD_STROBE_PW_REG_V_LSB 0 83 #define RD_STROBE_PW_REG_V_MASK 0xffffffff 84 #define RD_STROBE_PW_REG_V_GET(x) (((x) & RD_STROBE_PW_REG_V_MASK) >> RD_STROBE_PW_REG_V_LSB) 85 #define RD_STROBE_PW_REG_V_SET(x) (((x) << RD_STROBE_PW_REG_V_LSB) & RD_STROBE_PW_REG_V_MASK) 86 87 #define PG_STROBE_PW_REG_ADDRESS 0x0000001c 88 #define PG_STROBE_PW_REG_OFFSET 0x0000001c 89 #define PG_STROBE_PW_REG_V_MSB 31 90 #define PG_STROBE_PW_REG_V_LSB 0 91 #define PG_STROBE_PW_REG_V_MASK 0xffffffff 92 #define PG_STROBE_PW_REG_V_GET(x) (((x) & PG_STROBE_PW_REG_V_MASK) >> PG_STROBE_PW_REG_V_LSB) 93 #define PG_STROBE_PW_REG_V_SET(x) (((x) << PG_STROBE_PW_REG_V_LSB) & PG_STROBE_PW_REG_V_MASK) 94 95 #define PGENB_SETUP_HOLD_TIME_REG_ADDRESS 0x00000020 96 #define PGENB_SETUP_HOLD_TIME_REG_OFFSET 0x00000020 97 #define PGENB_SETUP_HOLD_TIME_REG_V_MSB 31 98 #define PGENB_SETUP_HOLD_TIME_REG_V_LSB 0 99 #define PGENB_SETUP_HOLD_TIME_REG_V_MASK 0xffffffff 100 #define PGENB_SETUP_HOLD_TIME_REG_V_GET(x) (((x) & PGENB_SETUP_HOLD_TIME_REG_V_MASK) >> PGENB_SETUP_HOLD_TIME_REG_V_LSB) 101 #define PGENB_SETUP_HOLD_TIME_REG_V_SET(x) (((x) << PGENB_SETUP_HOLD_TIME_REG_V_LSB) & PGENB_SETUP_HOLD_TIME_REG_V_MASK) 102 103 #define STROBE_PULSE_INTERVAL_REG_ADDRESS 0x00000024 104 #define STROBE_PULSE_INTERVAL_REG_OFFSET 0x00000024 105 #define STROBE_PULSE_INTERVAL_REG_V_MSB 31 106 #define STROBE_PULSE_INTERVAL_REG_V_LSB 0 107 #define STROBE_PULSE_INTERVAL_REG_V_MASK 0xffffffff 108 #define STROBE_PULSE_INTERVAL_REG_V_GET(x) (((x) & STROBE_PULSE_INTERVAL_REG_V_MASK) >> STROBE_PULSE_INTERVAL_REG_V_LSB) 109 #define STROBE_PULSE_INTERVAL_REG_V_SET(x) (((x) << STROBE_PULSE_INTERVAL_REG_V_LSB) & STROBE_PULSE_INTERVAL_REG_V_MASK) 110 111 #define CSB_ADDR_LOAD_SETUP_HOLD_REG_ADDRESS 0x00000028 112 #define CSB_ADDR_LOAD_SETUP_HOLD_REG_OFFSET 0x00000028 113 #define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MSB 31 114 #define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_LSB 0 115 #define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MASK 0xffffffff 116 #define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_GET(x) (((x) & CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MASK) >> CSB_ADDR_LOAD_SETUP_HOLD_REG_V_LSB) 117 #define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_SET(x) (((x) << CSB_ADDR_LOAD_SETUP_HOLD_REG_V_LSB) & CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MASK) 118 119 #define EFUSE_INTF0_ADDRESS 0x00000800 120 #define EFUSE_INTF0_OFFSET 0x00000800 121 #define EFUSE_INTF0_R_MSB 31 122 #define EFUSE_INTF0_R_LSB 0 123 #define EFUSE_INTF0_R_MASK 0xffffffff 124 #define EFUSE_INTF0_R_GET(x) (((x) & EFUSE_INTF0_R_MASK) >> EFUSE_INTF0_R_LSB) 125 #define EFUSE_INTF0_R_SET(x) (((x) << EFUSE_INTF0_R_LSB) & EFUSE_INTF0_R_MASK) 126 127 #define EFUSE_INTF1_ADDRESS 0x00001000 128 #define EFUSE_INTF1_OFFSET 0x00001000 129 #define EFUSE_INTF1_R_MSB 31 130 #define EFUSE_INTF1_R_LSB 0 131 #define EFUSE_INTF1_R_MASK 0xffffffff 132 #define EFUSE_INTF1_R_GET(x) (((x) & EFUSE_INTF1_R_MASK) >> EFUSE_INTF1_R_LSB) 133 #define EFUSE_INTF1_R_SET(x) (((x) << EFUSE_INTF1_R_LSB) & EFUSE_INTF1_R_MASK) 134 135 #ifndef __ASSEMBLER__ 136 typedef struct efuse_reg_reg_s { 137 volatile unsigned int efuse_wr_enable_reg; 138 volatile unsigned int efuse_int_enable_reg; 139 volatile unsigned int efuse_int_status_reg; 140 volatile unsigned int bitmask_wr_reg; 141 volatile unsigned int vddq_settle_time_reg; 142 volatile unsigned int vddq_hold_time_reg; 143 volatile unsigned int rd_strobe_pw_reg; 144 volatile unsigned int pg_strobe_pw_reg; 145 volatile unsigned int pgenb_setup_hold_time_reg; 146 volatile unsigned int strobe_pulse_interval_reg; 147 volatile unsigned int csb_addr_load_setup_hold_reg; 148 unsigned char pad0[2004]; /* pad to 0x800 */ 149 volatile unsigned int efuse_intf0[512]; 150 volatile unsigned int efuse_intf1[512]; 151 } efuse_reg_reg_t; 152 #endif /* __ASSEMBLER__ */ 153 154 #endif /* _EFUSE_REG_H_ */ 155