1 /* 2 * Copyright (c) 2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _RX_MPDU_INFO_H_ 25 #define _RX_MPDU_INFO_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "rxpt_classify_info.h" 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0 struct rxpt_classify_info rxpt_classify_info_details; 35 // 1 rx_reo_queue_desc_addr_31_0[31:0] 36 // 2 rx_reo_queue_desc_addr_39_32[7:0], receive_queue_number[23:8], pre_delim_err_warning[24], first_delim_err[25], reserved_11[31:26] 37 // 3 pn_31_0[31:0] 38 // 4 pn_63_32[31:0] 39 // 5 pn_95_64[31:0] 40 // 6 pn_127_96[31:0] 41 // 7 epd_en[0], all_frames_shall_be_encrypted[1], encrypt_type[5:2], wep_key_width_for_variable_key[7:6], mesh_sta[9:8], bssid_hit[10], bssid_number[14:11], tid[18:15], reserved_3a[31:19] 42 // 8 peer_meta_data[31:0] 43 // 9 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], ndp_frame[9], phy_err[10], phy_err_during_mpdu_header[11], protocol_version_err[12], ast_based_lookup_valid[13], reserved_0a[15:14], phy_ppdu_id[31:16] 44 // 10 ast_index[15:0], sw_peer_id[31:16] 45 // 11 mpdu_frame_control_valid[0], mpdu_duration_valid[1], mac_addr_ad1_valid[2], mac_addr_ad2_valid[3], mac_addr_ad3_valid[4], mac_addr_ad4_valid[5], mpdu_sequence_control_valid[6], mpdu_qos_control_valid[7], mpdu_ht_control_valid[8], frame_encryption_info_valid[9], mpdu_fragment_number[13:10], more_fragment_flag[14], reserved_2a[15], fr_ds[16], to_ds[17], encrypted[18], mpdu_retry[19], mpdu_sequence_number[31:20] 46 // 12 key_id_octet[7:0], new_peer_entry[8], decrypt_needed[9], decap_type[11:10], rx_insert_vlan_c_tag_padding[12], rx_insert_vlan_s_tag_padding[13], strip_vlan_c_tag_decap[14], strip_vlan_s_tag_decap[15], pre_delim_count[27:16], ampdu_flag[28], bar_frame[29], raw_mpdu[30], reserved_12[31] 47 // 13 mpdu_length[13:0], first_mpdu[14], mcast_bcast[15], ast_index_not_found[16], ast_index_timeout[17], power_mgmt[18], non_qos[19], null_data[20], mgmt_type[21], ctrl_type[22], more_data[23], eosp[24], fragment_flag[25], order[26], u_apsd_trigger[27], encrypt_required[28], directed[29], amsdu_present[30], reserved_13[31] 48 // 14 mpdu_frame_control_field[15:0], mpdu_duration_field[31:16] 49 // 15 mac_addr_ad1_31_0[31:0] 50 // 16 mac_addr_ad1_47_32[15:0], mac_addr_ad2_15_0[31:16] 51 // 17 mac_addr_ad2_47_16[31:0] 52 // 18 mac_addr_ad3_31_0[31:0] 53 // 19 mac_addr_ad3_47_32[15:0], mpdu_sequence_control_field[31:16] 54 // 20 mac_addr_ad4_31_0[31:0] 55 // 21 mac_addr_ad4_47_32[15:0], mpdu_qos_control_field[31:16] 56 // 22 mpdu_ht_control_field[31:0] 57 // 58 // ################ END SUMMARY ################# 59 60 #define NUM_OF_DWORDS_RX_MPDU_INFO 23 61 62 struct rx_mpdu_info { 63 struct rxpt_classify_info rxpt_classify_info_details; 64 uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] 65 uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] 66 receive_queue_number : 16, //[23:8] 67 pre_delim_err_warning : 1, //[24] 68 first_delim_err : 1, //[25] 69 reserved_11 : 6; //[31:26] 70 uint32_t pn_31_0 : 32; //[31:0] 71 uint32_t pn_63_32 : 32; //[31:0] 72 uint32_t pn_95_64 : 32; //[31:0] 73 uint32_t pn_127_96 : 32; //[31:0] 74 uint32_t epd_en : 1, //[0] 75 all_frames_shall_be_encrypted : 1, //[1] 76 encrypt_type : 4, //[5:2] 77 wep_key_width_for_variable_key : 2, //[7:6] 78 mesh_sta : 2, //[9:8] 79 bssid_hit : 1, //[10] 80 bssid_number : 4, //[14:11] 81 tid : 4, //[18:15] 82 reserved_3a : 13; //[31:19] 83 uint32_t peer_meta_data : 32; //[31:0] 84 uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] 85 sw_frame_group_id : 7, //[8:2] 86 ndp_frame : 1, //[9] 87 phy_err : 1, //[10] 88 phy_err_during_mpdu_header : 1, //[11] 89 protocol_version_err : 1, //[12] 90 ast_based_lookup_valid : 1, //[13] 91 reserved_0a : 2, //[15:14] 92 phy_ppdu_id : 16; //[31:16] 93 uint32_t ast_index : 16, //[15:0] 94 sw_peer_id : 16; //[31:16] 95 uint32_t mpdu_frame_control_valid : 1, //[0] 96 mpdu_duration_valid : 1, //[1] 97 mac_addr_ad1_valid : 1, //[2] 98 mac_addr_ad2_valid : 1, //[3] 99 mac_addr_ad3_valid : 1, //[4] 100 mac_addr_ad4_valid : 1, //[5] 101 mpdu_sequence_control_valid : 1, //[6] 102 mpdu_qos_control_valid : 1, //[7] 103 mpdu_ht_control_valid : 1, //[8] 104 frame_encryption_info_valid : 1, //[9] 105 mpdu_fragment_number : 4, //[13:10] 106 more_fragment_flag : 1, //[14] 107 reserved_2a : 1, //[15] 108 fr_ds : 1, //[16] 109 to_ds : 1, //[17] 110 encrypted : 1, //[18] 111 mpdu_retry : 1, //[19] 112 mpdu_sequence_number : 12; //[31:20] 113 uint32_t key_id_octet : 8, //[7:0] 114 new_peer_entry : 1, //[8] 115 decrypt_needed : 1, //[9] 116 decap_type : 2, //[11:10] 117 rx_insert_vlan_c_tag_padding : 1, //[12] 118 rx_insert_vlan_s_tag_padding : 1, //[13] 119 strip_vlan_c_tag_decap : 1, //[14] 120 strip_vlan_s_tag_decap : 1, //[15] 121 pre_delim_count : 12, //[27:16] 122 ampdu_flag : 1, //[28] 123 bar_frame : 1, //[29] 124 raw_mpdu : 1, //[30] 125 reserved_12 : 1; //[31] 126 uint32_t mpdu_length : 14, //[13:0] 127 first_mpdu : 1, //[14] 128 mcast_bcast : 1, //[15] 129 ast_index_not_found : 1, //[16] 130 ast_index_timeout : 1, //[17] 131 power_mgmt : 1, //[18] 132 non_qos : 1, //[19] 133 null_data : 1, //[20] 134 mgmt_type : 1, //[21] 135 ctrl_type : 1, //[22] 136 more_data : 1, //[23] 137 eosp : 1, //[24] 138 fragment_flag : 1, //[25] 139 order : 1, //[26] 140 u_apsd_trigger : 1, //[27] 141 encrypt_required : 1, //[28] 142 directed : 1, //[29] 143 amsdu_present : 1, //[30] 144 reserved_13 : 1; //[31] 145 uint32_t mpdu_frame_control_field : 16, //[15:0] 146 mpdu_duration_field : 16; //[31:16] 147 uint32_t mac_addr_ad1_31_0 : 32; //[31:0] 148 uint32_t mac_addr_ad1_47_32 : 16, //[15:0] 149 mac_addr_ad2_15_0 : 16; //[31:16] 150 uint32_t mac_addr_ad2_47_16 : 32; //[31:0] 151 uint32_t mac_addr_ad3_31_0 : 32; //[31:0] 152 uint32_t mac_addr_ad3_47_32 : 16, //[15:0] 153 mpdu_sequence_control_field : 16; //[31:16] 154 uint32_t mac_addr_ad4_31_0 : 32; //[31:0] 155 uint32_t mac_addr_ad4_47_32 : 16, //[15:0] 156 mpdu_qos_control_field : 16; //[31:16] 157 uint32_t mpdu_ht_control_field : 32; //[31:0] 158 }; 159 160 /* 161 162 struct rxpt_classify_info rxpt_classify_info_details 163 164 In case of ndp or phy_err or AST_based_lookup_valid == 165 0, this field will be set to 0 166 167 168 169 RXOLE related classification info 170 171 <legal all 172 173 rx_reo_queue_desc_addr_31_0 174 175 In case of ndp or phy_err or AST_based_lookup_valid == 176 0, this field will be set to 0 177 178 179 180 Address (lower 32 bits) of the REO queue descriptor. 181 182 183 184 If no Peer entry lookup happened for this frame, the 185 value wil be set to 0, and the frame shall never be pushed 186 to REO entrance ring. 187 188 <legal all> 189 190 rx_reo_queue_desc_addr_39_32 191 192 In case of ndp or phy_err or AST_based_lookup_valid == 193 0, this field will be set to 0 194 195 196 197 Address (upper 8 bits) of the REO queue descriptor. 198 199 200 201 If no Peer entry lookup happened for this frame, the 202 value wil be set to 0, and the frame shall never be pushed 203 to REO entrance ring. 204 205 <legal all> 206 207 receive_queue_number 208 209 In case of ndp or phy_err or AST_based_lookup_valid == 210 0, this field will be set to 0 211 212 213 214 Indicates the MPDU queue ID to which this MPDU link 215 descriptor belongs 216 217 Used for tracking and debugging 218 219 <legal all> 220 221 pre_delim_err_warning 222 223 Indicates that a delimiter FCS error was found in 224 between the Previous MPDU and this MPDU. 225 226 227 228 Note that this is just a warning, and does not mean that 229 this MPDU is corrupted in any way. If it is, there will be 230 other errors indicated such as FCS or decrypt errors 231 232 233 234 In case of ndp or phy_err, this field will indicate at 235 least one of delimiters located after the last MPDU in the 236 previous PPDU has been corrupted. 237 238 first_delim_err 239 240 Indicates that the first delimiter had a FCS failure. 241 Only valid when first_mpdu and first_msdu are set. 242 243 244 245 246 reserved_11 247 248 <legal 0> 249 250 pn_31_0 251 252 253 254 255 256 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 257 is valid. 258 259 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 260 WEPSeed[1], pn1}. Only pn[47:0] is valid. 261 262 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, 263 pn1, pn0}. Only pn[47:0] is valid. 264 265 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, 266 pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, 267 pn0}. pn[127:0] are valid. 268 269 270 271 272 pn_63_32 273 274 275 276 277 Bits [63:32] of the PN number. See description for 278 pn_31_0. 279 280 281 282 283 pn_95_64 284 285 286 287 288 Bits [95:64] of the PN number. See description for 289 pn_31_0. 290 291 292 293 294 pn_127_96 295 296 297 298 299 Bits [127:96] of the PN number. See description for 300 pn_31_0. 301 302 303 304 305 epd_en 306 307 Field only valid when AST_based_lookup_valid == 1. 308 309 310 311 312 313 In case of ndp or phy_err or AST_based_lookup_valid == 314 0, this field will be set to 0 315 316 317 318 If set to one use EPD instead of LPD 319 320 321 322 323 <legal all> 324 325 all_frames_shall_be_encrypted 326 327 In case of ndp or phy_err or AST_based_lookup_valid == 328 0, this field will be set to 0 329 330 331 332 When set, all frames (data only ?) shall be encrypted. 333 If not, RX CRYPTO shall set an error flag. 334 335 <legal all> 336 337 encrypt_type 338 339 In case of ndp or phy_err or AST_based_lookup_valid == 340 0, this field will be set to 0 341 342 343 344 Indicates type of decrypt cipher used (as defined in the 345 peer entry) 346 347 348 349 <enum 0 wep_40> WEP 40-bit 350 351 <enum 1 wep_104> WEP 104-bit 352 353 <enum 2 tkip_no_mic> TKIP without MIC 354 355 <enum 3 wep_128> WEP 128-bit 356 357 <enum 4 tkip_with_mic> TKIP with MIC 358 359 <enum 5 wapi> WAPI 360 361 <enum 6 aes_ccmp_128> AES CCMP 128 362 363 <enum 7 no_cipher> No crypto 364 365 <enum 8 aes_ccmp_256> AES CCMP 256 366 367 <enum 9 aes_gcmp_128> AES CCMP 128 368 369 <enum 10 aes_gcmp_256> AES CCMP 256 370 371 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 372 373 374 375 <enum 12 wep_varied_width> WEP encryption. As for WEP 376 per keyid the key bit width can vary, the key bit width for 377 this MPDU will be indicated in field 378 wep_key_width_for_variable key 379 380 <legal 0-12> 381 382 wep_key_width_for_variable_key 383 384 Field only valid when key_type is set to 385 wep_varied_width. 386 387 388 389 This field indicates the size of the wep key for this 390 MPDU. 391 392 393 394 <enum 0 wep_varied_width_40> WEP 40-bit 395 396 <enum 1 wep_varied_width_104> WEP 104-bit 397 398 <enum 2 wep_varied_width_128> WEP 128-bit 399 400 401 402 <legal 0-2> 403 404 mesh_sta 405 406 In case of ndp or phy_err or AST_based_lookup_valid == 407 0, this field will be set to 0 408 409 410 411 When set, this is a Mesh (11s) STA. 412 413 414 415 The interpretation of the A-MSDU 'Length' field in the 416 MPDU (if any) is decided by the e-numerations below. 417 418 419 420 <enum 0 MESH_DISABLE> 421 422 <enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and 423 includes the length of Mesh Control. 424 425 <enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and 426 excludes the length of Mesh Control. 427 428 <enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian 429 and excludes the length of Mesh Control. This is 430 802.11s-compliant. 431 432 <legal all> 433 434 bssid_hit 435 436 In case of ndp or phy_err or AST_based_lookup_valid == 437 0, this field will be set to 0 438 439 440 441 When set, the BSSID of the incoming frame matched one of 442 the 8 BSSID register values 443 444 445 446 <legal all> 447 448 bssid_number 449 450 Field only valid when bssid_hit is set. 451 452 453 454 This number indicates which one out of the 8 BSSID 455 register values matched the incoming frame 456 457 <legal all> 458 459 tid 460 461 Field only valid when mpdu_qos_control_valid is set 462 463 464 465 The TID field in the QoS control field 466 467 <legal all> 468 469 reserved_3a 470 471 <legal 0> 472 473 peer_meta_data 474 475 In case of ndp or phy_err or AST_based_lookup_valid == 476 0, this field will be set to 0 477 478 479 480 Meta data that SW has programmed in the Peer table entry 481 of the transmitting STA. 482 483 <legal all> 484 485 rxpcu_mpdu_filter_in_category 486 487 Field indicates what the reason was that this MPDU frame 488 was allowed to come into the receive path by RXPCU 489 490 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 491 frame filter programming of rxpcu 492 493 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 494 regular frame filter and would have been dropped, were it 495 not for the frame fitting into the 'monitor_client' 496 category. 497 498 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 499 regular frame filter and also did not pass the 500 rxpcu_monitor_client filter. It would have been dropped 501 accept that it did pass the 'monitor_other' category. 502 503 504 505 Note: for ndp frame, if it was expected because the 506 preceding NDPA was filter_pass, the setting 507 rxpcu_filter_pass will be used. This setting will also be 508 used for every ndp frame in case Promiscuous mode is 509 enabled. 510 511 512 513 In case promiscuous is not enabled, and an NDP is not 514 preceded by a NPDA filter pass frame, the only other setting 515 that could appear here for the NDP is rxpcu_monitor_other. 516 517 (rxpcu has a configuration bit specifically for this 518 scenario) 519 520 521 522 Note: for 523 524 <legal 0-2> 525 526 sw_frame_group_id 527 528 SW processes frames based on certain classifications. 529 This field indicates to what sw classification this MPDU is 530 mapped. 531 532 The classification is given in priority order 533 534 535 536 <enum 0 sw_frame_group_NDP_frame> Note: The 537 corresponding Rxpcu_Mpdu_filter_in_category can be 538 rxpcu_filter_pass or rxpcu_monitor_other 539 540 541 542 <enum 1 sw_frame_group_Multicast_data> 543 544 <enum 2 sw_frame_group_Unicast_data> 545 546 <enum 3 sw_frame_group_Null_data > This includes mpdus 547 of type Data Null as well as QoS Data Null 548 549 550 551 <enum 4 sw_frame_group_mgmt_0000 > 552 553 <enum 5 sw_frame_group_mgmt_0001 > 554 555 <enum 6 sw_frame_group_mgmt_0010 > 556 557 <enum 7 sw_frame_group_mgmt_0011 > 558 559 <enum 8 sw_frame_group_mgmt_0100 > 560 561 <enum 9 sw_frame_group_mgmt_0101 > 562 563 <enum 10 sw_frame_group_mgmt_0110 > 564 565 <enum 11 sw_frame_group_mgmt_0111 > 566 567 <enum 12 sw_frame_group_mgmt_1000 > 568 569 <enum 13 sw_frame_group_mgmt_1001 > 570 571 <enum 14 sw_frame_group_mgmt_1010 > 572 573 <enum 15 sw_frame_group_mgmt_1011 > 574 575 <enum 16 sw_frame_group_mgmt_1100 > 576 577 <enum 17 sw_frame_group_mgmt_1101 > 578 579 <enum 18 sw_frame_group_mgmt_1110 > 580 581 <enum 19 sw_frame_group_mgmt_1111 > 582 583 584 585 <enum 20 sw_frame_group_ctrl_0000 > 586 587 <enum 21 sw_frame_group_ctrl_0001 > 588 589 <enum 22 sw_frame_group_ctrl_0010 > 590 591 <enum 23 sw_frame_group_ctrl_0011 > 592 593 <enum 24 sw_frame_group_ctrl_0100 > 594 595 <enum 25 sw_frame_group_ctrl_0101 > 596 597 <enum 26 sw_frame_group_ctrl_0110 > 598 599 <enum 27 sw_frame_group_ctrl_0111 > 600 601 <enum 28 sw_frame_group_ctrl_1000 > 602 603 <enum 29 sw_frame_group_ctrl_1001 > 604 605 <enum 30 sw_frame_group_ctrl_1010 > 606 607 <enum 31 sw_frame_group_ctrl_1011 > 608 609 <enum 32 sw_frame_group_ctrl_1100 > 610 611 <enum 33 sw_frame_group_ctrl_1101 > 612 613 <enum 34 sw_frame_group_ctrl_1110 > 614 615 <enum 35 sw_frame_group_ctrl_1111 > 616 617 618 619 <enum 36 sw_frame_group_unsupported> This covers type 3 620 and protocol version != 0 621 622 Note: The corresponding Rxpcu_Mpdu_filter_in_category 623 can only be rxpcu_monitor_other 624 625 626 627 628 Note: The corresponding Rxpcu_Mpdu_filter_in_category 629 can be rxpcu_filter_pass 630 631 632 633 <legal 0-37> 634 635 ndp_frame 636 637 When set, the received frame was an NDP frame, and thus 638 there will be no MPDU data. 639 640 <legal all> 641 642 phy_err 643 644 When set, a PHY error was received before MAC received 645 any data, and thus there will be no MPDU data. 646 647 <legal all> 648 649 phy_err_during_mpdu_header 650 651 When set, a PHY error was received before MAC received 652 the complete MPDU header which was needed for proper 653 decoding 654 655 <legal all> 656 657 protocol_version_err 658 659 Set when RXPCU detected a version error in the Frame 660 control field 661 662 <legal all> 663 664 ast_based_lookup_valid 665 666 When set, AST based lookup for this frame has found a 667 valid result. 668 669 670 671 Note that for NDP frame this will never be set 672 673 <legal all> 674 675 reserved_0a 676 677 <legal 0> 678 679 phy_ppdu_id 680 681 A ppdu counter value that PHY increments for every PPDU 682 received. The counter value wraps around 683 684 <legal all> 685 686 ast_index 687 688 This field indicates the index of the AST entry 689 corresponding to this MPDU. It is provided by the GSE module 690 instantiated in RXPCU. 691 692 A value of 0xFFFF indicates an invalid AST index, 693 meaning that No AST entry was found or NO AST search was 694 performed 695 696 697 698 In case of ndp or phy_err, this field will be set to 699 0xFFFF 700 701 <legal all> 702 703 sw_peer_id 704 705 In case of ndp or phy_err or AST_based_lookup_valid == 706 0, this field will be set to 0 707 708 709 710 This field indicates a unique peer identifier. It is set 711 equal to field 'sw_peer_id' from the AST entry 712 713 714 715 <legal all> 716 717 mpdu_frame_control_valid 718 719 When set, the field Mpdu_Frame_control_field has valid 720 information 721 722 723 724 725 <legal all> 726 727 mpdu_duration_valid 728 729 When set, the field Mpdu_duration_field has valid 730 information 731 732 733 734 735 <legal all> 736 737 mac_addr_ad1_valid 738 739 When set, the fields mac_addr_ad1_..... have valid 740 information 741 742 743 744 745 <legal all> 746 747 mac_addr_ad2_valid 748 749 When set, the fields mac_addr_ad2_..... have valid 750 information 751 752 753 754 755 756 757 758 <legal all> 759 760 mac_addr_ad3_valid 761 762 When set, the fields mac_addr_ad3_..... have valid 763 information 764 765 766 767 768 769 770 771 <legal all> 772 773 mac_addr_ad4_valid 774 775 When set, the fields mac_addr_ad4_..... have valid 776 information 777 778 779 780 781 782 783 784 <legal all> 785 786 mpdu_sequence_control_valid 787 788 When set, the fields mpdu_sequence_control_field and 789 mpdu_sequence_number have valid information as well as field 790 791 792 793 For MPDUs without a sequence control field, this field 794 will not be set. 795 796 797 798 799 <legal all> 800 801 mpdu_qos_control_valid 802 803 When set, the field mpdu_qos_control_field has valid 804 information 805 806 807 808 For MPDUs without a QoS control field, this field will 809 not be set. 810 811 812 813 814 <legal all> 815 816 mpdu_ht_control_valid 817 818 When set, the field mpdu_HT_control_field has valid 819 information 820 821 822 823 For MPDUs without a HT control field, this field will 824 not be set. 825 826 827 828 829 <legal all> 830 831 frame_encryption_info_valid 832 833 When set, the encryption related info fields, like IV 834 and PN are valid 835 836 837 838 For MPDUs that are not encrypted, this will not be set. 839 840 841 842 843 <legal all> 844 845 mpdu_fragment_number 846 847 Field only valid when Mpdu_sequence_control_valid is set 848 AND Fragment_flag is set 849 850 851 852 The fragment number from the 802.11 header 853 854 855 856 <legal all> 857 858 more_fragment_flag 859 860 The More Fragment bit setting from the MPDU header of 861 the received frame 862 863 864 865 <legal all> 866 867 reserved_2a 868 869 <legal 0> 870 871 fr_ds 872 873 Field only valid when Mpdu_frame_control_valid is set 874 875 876 877 Set if the from DS bit is set in the frame control. 878 879 <legal all> 880 881 to_ds 882 883 Field only valid when Mpdu_frame_control_valid is set 884 885 886 887 Set if the to DS bit is set in the frame control. 888 889 <legal all> 890 891 encrypted 892 893 Field only valid when Mpdu_frame_control_valid is set. 894 895 896 897 Protected bit from the frame control. 898 899 <legal all> 900 901 mpdu_retry 902 903 Field only valid when Mpdu_frame_control_valid is set. 904 905 906 907 Retry bit from the frame control. Only valid when 908 first_msdu is set. 909 910 <legal all> 911 912 mpdu_sequence_number 913 914 Field only valid when Mpdu_sequence_control_valid is 915 set. 916 917 918 919 The sequence number from the 802.11 header. 920 921 <legal all> 922 923 key_id_octet 924 925 926 927 928 The key ID octet from the IV. 929 930 931 932 In case of ndp or phy_err or AST_based_lookup_valid == 933 0, this field will be set to 0 934 935 <legal all> 936 937 new_peer_entry 938 939 In case of ndp or phy_err or AST_based_lookup_valid == 940 0, this field will be set to 0 941 942 943 944 Set if new RX_PEER_ENTRY TLV follows. If clear, 945 RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either 946 uses old peer entry or not decrypt. 947 948 <legal all> 949 950 decrypt_needed 951 952 In case of ndp or phy_err or AST_based_lookup_valid == 953 0, this field will be set to 0 954 955 956 957 Set if decryption is needed. 958 959 960 961 Note: 962 963 When RXPCU sets bit 'ast_index_not_found' and/or 964 ast_index_timeout', RXPCU will also ensure that this bit is 965 NOT set 966 967 CRYPTO for that reason only needs to evaluate this bit 968 and non of the other ones. 969 970 <legal all> 971 972 decap_type 973 974 In case of ndp or phy_err or AST_based_lookup_valid == 975 0, this field will be set to 0 976 977 978 979 Used by the OLE during decapsulation. 980 981 982 983 Indicates the decapsulation that HW will perform: 984 985 986 987 <enum 0 RAW> No encapsulation 988 989 <enum 1 Native_WiFi> 990 991 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses 992 SNAP/LLC) 993 994 <enum 3 802_3> Indicate Ethernet 995 996 997 998 <legal all> 999 1000 rx_insert_vlan_c_tag_padding 1001 1002 In case of ndp or phy_err or AST_based_lookup_valid == 1003 0, this field will be set to 0 1004 1005 1006 1007 Insert 4 byte of all zeros as VLAN tag if the rx payload 1008 does not have VLAN. Used during decapsulation. 1009 1010 <legal all> 1011 1012 rx_insert_vlan_s_tag_padding 1013 1014 In case of ndp or phy_err or AST_based_lookup_valid == 1015 0, this field will be set to 0 1016 1017 1018 1019 Insert 4 byte of all zeros as double VLAN tag if the rx 1020 payload does not have VLAN. Used during 1021 1022 <legal all> 1023 1024 strip_vlan_c_tag_decap 1025 1026 In case of ndp or phy_err or AST_based_lookup_valid == 1027 0, this field will be set to 0 1028 1029 1030 1031 Strip the VLAN during decapsulation. Used by the OLE. 1032 1033 <legal all> 1034 1035 strip_vlan_s_tag_decap 1036 1037 In case of ndp or phy_err or AST_based_lookup_valid == 1038 0, this field will be set to 0 1039 1040 1041 1042 Strip the double VLAN during decapsulation. Used by 1043 the OLE. 1044 1045 <legal all> 1046 1047 pre_delim_count 1048 1049 The number of delimiters before this MPDU. 1050 1051 1052 1053 Note that this number is cleared at PPDU start. 1054 1055 1056 1057 If this MPDU is the first received MPDU in the PPDU and 1058 this MPDU gets filtered-in, this field will indicate the 1059 number of delimiters located after the last MPDU in the 1060 previous PPDU. 1061 1062 1063 1064 If this MPDU is located after the first received MPDU in 1065 an PPDU, this field will indicate the number of delimiters 1066 located between the previous MPDU and this MPDU. 1067 1068 1069 1070 In case of ndp or phy_err, this field will indicate the 1071 number of delimiters located after the last MPDU in the 1072 previous PPDU. 1073 1074 <legal all> 1075 1076 ampdu_flag 1077 1078 When set, received frame was part of an A-MPDU. 1079 1080 1081 1082 1083 <legal all> 1084 1085 bar_frame 1086 1087 In case of ndp or phy_err or AST_based_lookup_valid == 1088 0, this field will be set to 0 1089 1090 1091 1092 When set, received frame is a BAR frame 1093 1094 <legal all> 1095 1096 raw_mpdu 1097 1098 Consumer: SW 1099 1100 Producer: RXOLE 1101 1102 1103 1104 RXPCU sets this field to 0 and RXOLE overwrites it. 1105 1106 1107 1108 Set to 1 by RXOLE when it has not performed any 802.11 1109 to Ethernet/Natvie WiFi header conversion on this MPDU. 1110 1111 <legal all> 1112 1113 reserved_12 1114 1115 <legal 0> 1116 1117 mpdu_length 1118 1119 In case of ndp or phy_err this field will be set to 0 1120 1121 1122 1123 MPDU length before decapsulation. 1124 1125 <legal all> 1126 1127 first_mpdu 1128 1129 See definition in RX attention descriptor 1130 1131 1132 1133 In case of ndp or phy_err, this field will be set. Note 1134 however that there will not actually be any data contents in 1135 the MPDU. 1136 1137 <legal all> 1138 1139 mcast_bcast 1140 1141 In case of ndp or phy_err or Phy_err_during_mpdu_header 1142 this field will be set to 0 1143 1144 1145 1146 See definition in RX attention descriptor 1147 1148 <legal all> 1149 1150 ast_index_not_found 1151 1152 In case of ndp or phy_err or Phy_err_during_mpdu_header 1153 this field will be set to 0 1154 1155 1156 1157 See definition in RX attention descriptor 1158 1159 <legal all> 1160 1161 ast_index_timeout 1162 1163 In case of ndp or phy_err or Phy_err_during_mpdu_header 1164 this field will be set to 0 1165 1166 1167 1168 See definition in RX attention descriptor 1169 1170 <legal all> 1171 1172 power_mgmt 1173 1174 In case of ndp or phy_err or Phy_err_during_mpdu_header 1175 this field will be set to 0 1176 1177 1178 1179 See definition in RX attention descriptor 1180 1181 <legal all> 1182 1183 non_qos 1184 1185 In case of ndp or phy_err or Phy_err_during_mpdu_header 1186 this field will be set to 1 1187 1188 1189 1190 See definition in RX attention descriptor 1191 1192 <legal all> 1193 1194 null_data 1195 1196 In case of ndp or phy_err or Phy_err_during_mpdu_header 1197 this field will be set to 0 1198 1199 1200 1201 See definition in RX attention descriptor 1202 1203 <legal all> 1204 1205 mgmt_type 1206 1207 In case of ndp or phy_err or Phy_err_during_mpdu_header 1208 this field will be set to 0 1209 1210 1211 1212 See definition in RX attention descriptor 1213 1214 <legal all> 1215 1216 ctrl_type 1217 1218 In case of ndp or phy_err or Phy_err_during_mpdu_header 1219 this field will be set to 0 1220 1221 1222 1223 See definition in RX attention descriptor 1224 1225 <legal all> 1226 1227 more_data 1228 1229 In case of ndp or phy_err or Phy_err_during_mpdu_header 1230 this field will be set to 0 1231 1232 1233 1234 See definition in RX attention descriptor 1235 1236 <legal all> 1237 1238 eosp 1239 1240 In case of ndp or phy_err or Phy_err_during_mpdu_header 1241 this field will be set to 0 1242 1243 1244 1245 See definition in RX attention descriptor 1246 1247 <legal all> 1248 1249 fragment_flag 1250 1251 In case of ndp or phy_err or Phy_err_during_mpdu_header 1252 this field will be set to 0 1253 1254 1255 1256 See definition in RX attention descriptor 1257 1258 <legal all> 1259 1260 order 1261 1262 In case of ndp or phy_err or Phy_err_during_mpdu_header 1263 this field will be set to 0 1264 1265 1266 1267 See definition in RX attention descriptor 1268 1269 1270 1271 <legal all> 1272 1273 u_apsd_trigger 1274 1275 In case of ndp or phy_err or Phy_err_during_mpdu_header 1276 this field will be set to 0 1277 1278 1279 1280 See definition in RX attention descriptor 1281 1282 <legal all> 1283 1284 encrypt_required 1285 1286 In case of ndp or phy_err or Phy_err_during_mpdu_header 1287 this field will be set to 0 1288 1289 1290 1291 See definition in RX attention descriptor 1292 1293 <legal all> 1294 1295 directed 1296 1297 In case of ndp or phy_err or Phy_err_during_mpdu_header 1298 this field will be set to 0 1299 1300 1301 1302 See definition in RX attention descriptor 1303 1304 <legal all> 1305 1306 amsdu_present 1307 1308 Field only valid when Mpdu_qos_control_valid is set 1309 1310 1311 1312 The 'amsdu_present' bit within the QoS control field of 1313 the MPDU 1314 1315 <legal all> 1316 1317 reserved_13 1318 1319 <legal 0> 1320 1321 mpdu_frame_control_field 1322 1323 Field only valid when Mpdu_frame_control_valid is set 1324 1325 1326 1327 The frame control field of this received MPDU. 1328 1329 1330 1331 Field only valid when Ndp_frame and phy_err are NOT set 1332 1333 1334 1335 Bytes 0 + 1 of the received MPDU 1336 1337 <legal all> 1338 1339 mpdu_duration_field 1340 1341 Field only valid when Mpdu_duration_valid is set 1342 1343 1344 1345 The duration field of this received MPDU. 1346 1347 <legal all> 1348 1349 mac_addr_ad1_31_0 1350 1351 Field only valid when mac_addr_ad1_valid is set 1352 1353 1354 1355 The Least Significant 4 bytes of the Received Frames MAC 1356 Address AD1 1357 1358 <legal all> 1359 1360 mac_addr_ad1_47_32 1361 1362 Field only valid when mac_addr_ad1_valid is set 1363 1364 1365 1366 The 2 most significant bytes of the Received Frames MAC 1367 Address AD1 1368 1369 <legal all> 1370 1371 mac_addr_ad2_15_0 1372 1373 Field only valid when mac_addr_ad2_valid is set 1374 1375 1376 1377 The Least Significant 2 bytes of the Received Frames MAC 1378 Address AD2 1379 1380 <legal all> 1381 1382 mac_addr_ad2_47_16 1383 1384 Field only valid when mac_addr_ad2_valid is set 1385 1386 1387 1388 The 4 most significant bytes of the Received Frames MAC 1389 Address AD2 1390 1391 <legal all> 1392 1393 mac_addr_ad3_31_0 1394 1395 Field only valid when mac_addr_ad3_valid is set 1396 1397 1398 1399 The Least Significant 4 bytes of the Received Frames MAC 1400 Address AD3 1401 1402 <legal all> 1403 1404 mac_addr_ad3_47_32 1405 1406 Field only valid when mac_addr_ad3_valid is set 1407 1408 1409 1410 The 2 most significant bytes of the Received Frames MAC 1411 Address AD3 1412 1413 <legal all> 1414 1415 mpdu_sequence_control_field 1416 1417 1418 1419 1420 The sequence control field of the MPDU 1421 1422 <legal all> 1423 1424 mac_addr_ad4_31_0 1425 1426 Field only valid when mac_addr_ad4_valid is set 1427 1428 1429 1430 The Least Significant 4 bytes of the Received Frames MAC 1431 Address AD4 1432 1433 <legal all> 1434 1435 mac_addr_ad4_47_32 1436 1437 Field only valid when mac_addr_ad4_valid is set 1438 1439 1440 1441 The 2 most significant bytes of the Received Frames MAC 1442 Address AD4 1443 1444 <legal all> 1445 1446 mpdu_qos_control_field 1447 1448 Field only valid when mpdu_qos_control_valid is set 1449 1450 1451 1452 The sequence control field of the MPDU 1453 1454 <legal all> 1455 1456 mpdu_ht_control_field 1457 1458 Field only valid when mpdu_qos_control_valid is set 1459 1460 1461 1462 The HT control field of the MPDU 1463 1464 <legal all> 1465 */ 1466 1467 1468 /* EXTERNAL REFERENCE : struct rxpt_classify_info rxpt_classify_info_details */ 1469 1470 1471 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION 1472 1473 The ID of the REO exit ring where the MSDU frame shall 1474 push after (MPDU level) reordering has finished. 1475 1476 1477 1478 <enum 0 reo_destination_tcl> Reo will push the frame 1479 into the REO2TCL ring 1480 1481 <enum 1 reo_destination_sw1> Reo will push the frame 1482 into the REO2SW1 ring 1483 1484 <enum 2 reo_destination_sw2> Reo will push the frame 1485 into the REO2SW2 ring 1486 1487 <enum 3 reo_destination_sw3> Reo will push the frame 1488 into the REO2SW3 ring 1489 1490 <enum 4 reo_destination_sw4> Reo will push the frame 1491 into the REO2SW4 ring 1492 1493 <enum 5 reo_destination_release> Reo will push the frame 1494 into the REO_release ring 1495 1496 <enum 6 reo_destination_fw> Reo will push the frame into 1497 the REO2FW ring 1498 1499 <enum 7 reo_destination_sw5> Reo will push the frame 1500 into the REO2SW5 ring 1501 1502 <enum 8 reo_destination_sw6> Reo will push the frame 1503 into the REO2SW6 ring 1504 1505 <enum 9 reo_destination_9> REO remaps this <enum 10 1506 reo_destination_10> REO remaps this 1507 1508 <enum 11 reo_destination_11> REO remaps this 1509 1510 <enum 12 reo_destination_12> REO remaps this <enum 13 1511 reo_destination_13> REO remaps this 1512 1513 <enum 14 reo_destination_14> REO remaps this 1514 1515 <enum 15 reo_destination_15> REO remaps this 1516 1517 <enum 16 reo_destination_16> REO remaps this 1518 1519 <enum 17 reo_destination_17> REO remaps this 1520 1521 <enum 18 reo_destination_18> REO remaps this 1522 1523 <enum 19 reo_destination_19> REO remaps this 1524 1525 <enum 20 reo_destination_20> REO remaps this 1526 1527 <enum 21 reo_destination_21> REO remaps this 1528 1529 <enum 22 reo_destination_22> REO remaps this 1530 1531 <enum 23 reo_destination_23> REO remaps this 1532 1533 <enum 24 reo_destination_24> REO remaps this 1534 1535 <enum 25 reo_destination_25> REO remaps this 1536 1537 <enum 26 reo_destination_26> REO remaps this 1538 1539 <enum 27 reo_destination_27> REO remaps this 1540 1541 <enum 28 reo_destination_28> REO remaps this 1542 1543 <enum 29 reo_destination_29> REO remaps this 1544 1545 <enum 30 reo_destination_30> REO remaps this 1546 1547 <enum 31 reo_destination_31> REO remaps this 1548 1549 1550 1551 <legal all> 1552 */ 1553 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 1554 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 1555 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 1556 1557 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB 1558 1559 If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb 1560 is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1, 1561 hash[3:0]} using the chosen Toeplitz hash from Common Parser 1562 if flow search fails. 1563 1564 If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb 1565 's not 2'b00, Rx OLE uses a REO desination indication of 1566 {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz hash 1567 from Common Parser if flow search fails. 1568 1569 This LMAC/peer-based routing is not supported in 1570 Hastings80 and HastingsPrime. 1571 1572 <legal 0> 1573 */ 1574 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 1575 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 1576 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 1577 1578 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY 1579 1580 Indication to Rx OLE to enable REO destination routing 1581 based on the chosen Toeplitz hash from Common Parser, in 1582 case flow search fails 1583 1584 <legal all> 1585 */ 1586 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 1587 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 1588 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 1589 1590 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA 1591 1592 Filter pass Unicast data frame (matching 1593 rxpcu_filter_pass and sw_frame_group_Unicast_data) routing 1594 selection 1595 1596 1597 1598 1'b0: source and destination rings are selected from the 1599 RxOLE register settings for the packet type 1600 1601 1602 1603 1'b1: source ring and destination ring is selected from 1604 the rxdma0_source_ring_selection and 1605 rxdma0_destination_ring_selection fields in this STRUCT 1606 1607 <legal all> 1608 */ 1609 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 1610 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 1611 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 1612 1613 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA 1614 1615 Filter pass Multicast data frame (matching 1616 rxpcu_filter_pass and sw_frame_group_Multicast_data) routing 1617 selection 1618 1619 1620 1621 1'b0: source and destination rings are selected from the 1622 RxOLE register settings for the packet type 1623 1624 1625 1626 1'b1: source ring and destination ring is selected from 1627 the rxdma0_source_ring_selection and 1628 rxdma0_destination_ring_selection fields in this STRUCT 1629 1630 <legal all> 1631 */ 1632 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 1633 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 1634 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 1635 1636 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000 1637 1638 Filter pass BAR frame (matching rxpcu_filter_pass and 1639 sw_frame_group_ctrl_1000) routing selection 1640 1641 1642 1643 1'b0: source and destination rings are selected from the 1644 RxOLE register settings for the packet type 1645 1646 1647 1648 1'b1: source ring and destination ring is selected from 1649 the rxdma0_source_ring_selection and 1650 rxdma0_destination_ring_selection fields in this STRUCT 1651 1652 <legal all> 1653 */ 1654 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 1655 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 1656 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 1657 1658 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION 1659 1660 Field only valid when for the received frame type the 1661 corresponding pkt_selection_fp_... bit is set 1662 1663 1664 1665 <enum 0 wbm2rxdma_buf_source_ring> The data buffer for 1666 1667 <enum 1 fw2rxdma_buf_source_ring> The data buffer for 1668 this frame shall be sourced by fw2rxdma buffer source ring. 1669 1670 <enum 2 sw2rxdma_buf_source_ring> The data buffer for 1671 this frame shall be sourced by sw2rxdma buffer source ring. 1672 1673 <enum 3 no_buffer_ring> The frame shall not be written 1674 to any data buffer. 1675 1676 1677 1678 <legal all> 1679 */ 1680 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 1681 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 1682 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800 1683 1684 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION 1685 1686 Field only valid when for the received frame type the 1687 corresponding pkt_selection_fp_... bit is set 1688 1689 1690 1691 <enum 0 rxdma_release_ring> RXDMA0 shall push the frame 1692 to the Release ring. Effectively this means the frame needs 1693 to be dropped. 1694 1695 <enum 1 rxdma2fw_ring> RXDMA0 shall push the frame to 1696 the FW ring. 1697 1698 <enum 2 rxdma2sw_ring> RXDMA0 shall push the frame to 1699 the SW ring. 1700 1701 <enum 3 rxdma2reo_ring> RXDMA0 shall push the frame to 1702 the REO entrance ring. 1703 1704 1705 1706 <legal all> 1707 */ 1708 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 1709 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13 1710 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000 1711 1712 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B 1713 1714 <legal 0> 1715 */ 1716 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 1717 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15 1718 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000 1719 1720 /* Description RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0 1721 1722 In case of ndp or phy_err or AST_based_lookup_valid == 1723 0, this field will be set to 0 1724 1725 1726 1727 Address (lower 32 bits) of the REO queue descriptor. 1728 1729 1730 1731 If no Peer entry lookup happened for this frame, the 1732 value wil be set to 0, and the frame shall never be pushed 1733 to REO entrance ring. 1734 1735 <legal all> 1736 */ 1737 #define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 1738 #define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 1739 #define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 1740 1741 /* Description RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32 1742 1743 In case of ndp or phy_err or AST_based_lookup_valid == 1744 0, this field will be set to 0 1745 1746 1747 1748 Address (upper 8 bits) of the REO queue descriptor. 1749 1750 1751 1752 If no Peer entry lookup happened for this frame, the 1753 value wil be set to 0, and the frame shall never be pushed 1754 to REO entrance ring. 1755 1756 <legal all> 1757 */ 1758 #define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 1759 #define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 1760 #define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 1761 1762 /* Description RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER 1763 1764 In case of ndp or phy_err or AST_based_lookup_valid == 1765 0, this field will be set to 0 1766 1767 1768 1769 Indicates the MPDU queue ID to which this MPDU link 1770 descriptor belongs 1771 1772 Used for tracking and debugging 1773 1774 <legal all> 1775 */ 1776 #define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 1777 #define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_LSB 8 1778 #define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 1779 1780 /* Description RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING 1781 1782 Indicates that a delimiter FCS error was found in 1783 between the Previous MPDU and this MPDU. 1784 1785 1786 1787 Note that this is just a warning, and does not mean that 1788 this MPDU is corrupted in any way. If it is, there will be 1789 other errors indicated such as FCS or decrypt errors 1790 1791 1792 1793 In case of ndp or phy_err, this field will indicate at 1794 least one of delimiters located after the last MPDU in the 1795 previous PPDU has been corrupted. 1796 */ 1797 #define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 1798 #define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_LSB 24 1799 #define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_MASK 0x01000000 1800 1801 /* Description RX_MPDU_INFO_2_FIRST_DELIM_ERR 1802 1803 Indicates that the first delimiter had a FCS failure. 1804 Only valid when first_mpdu and first_msdu are set. 1805 1806 1807 1808 */ 1809 #define RX_MPDU_INFO_2_FIRST_DELIM_ERR_OFFSET 0x00000008 1810 #define RX_MPDU_INFO_2_FIRST_DELIM_ERR_LSB 25 1811 #define RX_MPDU_INFO_2_FIRST_DELIM_ERR_MASK 0x02000000 1812 1813 /* Description RX_MPDU_INFO_2_RESERVED_11 1814 1815 <legal 0> 1816 */ 1817 #define RX_MPDU_INFO_2_RESERVED_11_OFFSET 0x00000008 1818 #define RX_MPDU_INFO_2_RESERVED_11_LSB 26 1819 #define RX_MPDU_INFO_2_RESERVED_11_MASK 0xfc000000 1820 1821 /* Description RX_MPDU_INFO_3_PN_31_0 1822 1823 1824 1825 1826 1827 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 1828 is valid. 1829 1830 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 1831 WEPSeed[1], pn1}. Only pn[47:0] is valid. 1832 1833 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, 1834 pn1, pn0}. Only pn[47:0] is valid. 1835 1836 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, 1837 pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, 1838 pn0}. pn[127:0] are valid. 1839 1840 1841 1842 */ 1843 #define RX_MPDU_INFO_3_PN_31_0_OFFSET 0x0000000c 1844 #define RX_MPDU_INFO_3_PN_31_0_LSB 0 1845 #define RX_MPDU_INFO_3_PN_31_0_MASK 0xffffffff 1846 1847 /* Description RX_MPDU_INFO_4_PN_63_32 1848 1849 1850 1851 1852 Bits [63:32] of the PN number. See description for 1853 pn_31_0. 1854 1855 1856 1857 */ 1858 #define RX_MPDU_INFO_4_PN_63_32_OFFSET 0x00000010 1859 #define RX_MPDU_INFO_4_PN_63_32_LSB 0 1860 #define RX_MPDU_INFO_4_PN_63_32_MASK 0xffffffff 1861 1862 /* Description RX_MPDU_INFO_5_PN_95_64 1863 1864 1865 1866 1867 Bits [95:64] of the PN number. See description for 1868 pn_31_0. 1869 1870 1871 1872 */ 1873 #define RX_MPDU_INFO_5_PN_95_64_OFFSET 0x00000014 1874 #define RX_MPDU_INFO_5_PN_95_64_LSB 0 1875 #define RX_MPDU_INFO_5_PN_95_64_MASK 0xffffffff 1876 1877 /* Description RX_MPDU_INFO_6_PN_127_96 1878 1879 1880 1881 1882 Bits [127:96] of the PN number. See description for 1883 pn_31_0. 1884 1885 1886 1887 */ 1888 #define RX_MPDU_INFO_6_PN_127_96_OFFSET 0x00000018 1889 #define RX_MPDU_INFO_6_PN_127_96_LSB 0 1890 #define RX_MPDU_INFO_6_PN_127_96_MASK 0xffffffff 1891 1892 /* Description RX_MPDU_INFO_7_EPD_EN 1893 1894 Field only valid when AST_based_lookup_valid == 1. 1895 1896 1897 1898 1899 1900 In case of ndp or phy_err or AST_based_lookup_valid == 1901 0, this field will be set to 0 1902 1903 1904 1905 If set to one use EPD instead of LPD 1906 1907 1908 1909 1910 <legal all> 1911 */ 1912 #define RX_MPDU_INFO_7_EPD_EN_OFFSET 0x0000001c 1913 #define RX_MPDU_INFO_7_EPD_EN_LSB 0 1914 #define RX_MPDU_INFO_7_EPD_EN_MASK 0x00000001 1915 1916 /* Description RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED 1917 1918 In case of ndp or phy_err or AST_based_lookup_valid == 1919 0, this field will be set to 0 1920 1921 1922 1923 When set, all frames (data only ?) shall be encrypted. 1924 If not, RX CRYPTO shall set an error flag. 1925 1926 <legal all> 1927 */ 1928 #define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c 1929 #define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 1930 #define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 1931 1932 /* Description RX_MPDU_INFO_7_ENCRYPT_TYPE 1933 1934 In case of ndp or phy_err or AST_based_lookup_valid == 1935 0, this field will be set to 0 1936 1937 1938 1939 Indicates type of decrypt cipher used (as defined in the 1940 peer entry) 1941 1942 1943 1944 <enum 0 wep_40> WEP 40-bit 1945 1946 <enum 1 wep_104> WEP 104-bit 1947 1948 <enum 2 tkip_no_mic> TKIP without MIC 1949 1950 <enum 3 wep_128> WEP 128-bit 1951 1952 <enum 4 tkip_with_mic> TKIP with MIC 1953 1954 <enum 5 wapi> WAPI 1955 1956 <enum 6 aes_ccmp_128> AES CCMP 128 1957 1958 <enum 7 no_cipher> No crypto 1959 1960 <enum 8 aes_ccmp_256> AES CCMP 256 1961 1962 <enum 9 aes_gcmp_128> AES CCMP 128 1963 1964 <enum 10 aes_gcmp_256> AES CCMP 256 1965 1966 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 1967 1968 1969 1970 <enum 12 wep_varied_width> WEP encryption. As for WEP 1971 per keyid the key bit width can vary, the key bit width for 1972 this MPDU will be indicated in field 1973 wep_key_width_for_variable key 1974 1975 <legal 0-12> 1976 */ 1977 #define RX_MPDU_INFO_7_ENCRYPT_TYPE_OFFSET 0x0000001c 1978 #define RX_MPDU_INFO_7_ENCRYPT_TYPE_LSB 2 1979 #define RX_MPDU_INFO_7_ENCRYPT_TYPE_MASK 0x0000003c 1980 1981 /* Description RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY 1982 1983 Field only valid when key_type is set to 1984 wep_varied_width. 1985 1986 1987 1988 This field indicates the size of the wep key for this 1989 MPDU. 1990 1991 1992 1993 <enum 0 wep_varied_width_40> WEP 40-bit 1994 1995 <enum 1 wep_varied_width_104> WEP 104-bit 1996 1997 <enum 2 wep_varied_width_128> WEP 128-bit 1998 1999 2000 2001 <legal 0-2> 2002 */ 2003 #define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c 2004 #define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 2005 #define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 2006 2007 /* Description RX_MPDU_INFO_7_MESH_STA 2008 2009 In case of ndp or phy_err or AST_based_lookup_valid == 2010 0, this field will be set to 0 2011 2012 2013 2014 When set, this is a Mesh (11s) STA. 2015 2016 2017 2018 The interpretation of the A-MSDU 'Length' field in the 2019 MPDU (if any) is decided by the e-numerations below. 2020 2021 2022 2023 <enum 0 MESH_DISABLE> 2024 2025 <enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and 2026 includes the length of Mesh Control. 2027 2028 <enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and 2029 excludes the length of Mesh Control. 2030 2031 <enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian 2032 and excludes the length of Mesh Control. This is 2033 802.11s-compliant. 2034 2035 <legal all> 2036 */ 2037 #define RX_MPDU_INFO_7_MESH_STA_OFFSET 0x0000001c 2038 #define RX_MPDU_INFO_7_MESH_STA_LSB 8 2039 #define RX_MPDU_INFO_7_MESH_STA_MASK 0x00000300 2040 2041 /* Description RX_MPDU_INFO_7_BSSID_HIT 2042 2043 In case of ndp or phy_err or AST_based_lookup_valid == 2044 0, this field will be set to 0 2045 2046 2047 2048 When set, the BSSID of the incoming frame matched one of 2049 the 8 BSSID register values 2050 2051 2052 2053 <legal all> 2054 */ 2055 #define RX_MPDU_INFO_7_BSSID_HIT_OFFSET 0x0000001c 2056 #define RX_MPDU_INFO_7_BSSID_HIT_LSB 10 2057 #define RX_MPDU_INFO_7_BSSID_HIT_MASK 0x00000400 2058 2059 /* Description RX_MPDU_INFO_7_BSSID_NUMBER 2060 2061 Field only valid when bssid_hit is set. 2062 2063 2064 2065 This number indicates which one out of the 8 BSSID 2066 register values matched the incoming frame 2067 2068 <legal all> 2069 */ 2070 #define RX_MPDU_INFO_7_BSSID_NUMBER_OFFSET 0x0000001c 2071 #define RX_MPDU_INFO_7_BSSID_NUMBER_LSB 11 2072 #define RX_MPDU_INFO_7_BSSID_NUMBER_MASK 0x00007800 2073 2074 /* Description RX_MPDU_INFO_7_TID 2075 2076 Field only valid when mpdu_qos_control_valid is set 2077 2078 2079 2080 The TID field in the QoS control field 2081 2082 <legal all> 2083 */ 2084 #define RX_MPDU_INFO_7_TID_OFFSET 0x0000001c 2085 #define RX_MPDU_INFO_7_TID_LSB 15 2086 #define RX_MPDU_INFO_7_TID_MASK 0x00078000 2087 2088 /* Description RX_MPDU_INFO_7_RESERVED_3A 2089 2090 <legal 0> 2091 */ 2092 #define RX_MPDU_INFO_7_RESERVED_3A_OFFSET 0x0000001c 2093 #define RX_MPDU_INFO_7_RESERVED_3A_LSB 19 2094 #define RX_MPDU_INFO_7_RESERVED_3A_MASK 0xfff80000 2095 2096 /* Description RX_MPDU_INFO_8_PEER_META_DATA 2097 2098 In case of ndp or phy_err or AST_based_lookup_valid == 2099 0, this field will be set to 0 2100 2101 2102 2103 Meta data that SW has programmed in the Peer table entry 2104 of the transmitting STA. 2105 2106 <legal all> 2107 */ 2108 #define RX_MPDU_INFO_8_PEER_META_DATA_OFFSET 0x00000020 2109 #define RX_MPDU_INFO_8_PEER_META_DATA_LSB 0 2110 #define RX_MPDU_INFO_8_PEER_META_DATA_MASK 0xffffffff 2111 2112 /* Description RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY 2113 2114 Field indicates what the reason was that this MPDU frame 2115 was allowed to come into the receive path by RXPCU 2116 2117 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 2118 frame filter programming of rxpcu 2119 2120 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 2121 regular frame filter and would have been dropped, were it 2122 not for the frame fitting into the 'monitor_client' 2123 category. 2124 2125 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 2126 regular frame filter and also did not pass the 2127 rxpcu_monitor_client filter. It would have been dropped 2128 accept that it did pass the 'monitor_other' category. 2129 2130 2131 2132 Note: for ndp frame, if it was expected because the 2133 preceding NDPA was filter_pass, the setting 2134 rxpcu_filter_pass will be used. This setting will also be 2135 used for every ndp frame in case Promiscuous mode is 2136 enabled. 2137 2138 2139 2140 In case promiscuous is not enabled, and an NDP is not 2141 preceded by a NPDA filter pass frame, the only other setting 2142 that could appear here for the NDP is rxpcu_monitor_other. 2143 2144 (rxpcu has a configuration bit specifically for this 2145 scenario) 2146 2147 2148 2149 Note: for 2150 2151 <legal 0-2> 2152 */ 2153 #define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 2154 #define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 2155 #define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 2156 2157 /* Description RX_MPDU_INFO_9_SW_FRAME_GROUP_ID 2158 2159 SW processes frames based on certain classifications. 2160 This field indicates to what sw classification this MPDU is 2161 mapped. 2162 2163 The classification is given in priority order 2164 2165 2166 2167 <enum 0 sw_frame_group_NDP_frame> Note: The 2168 corresponding Rxpcu_Mpdu_filter_in_category can be 2169 rxpcu_filter_pass or rxpcu_monitor_other 2170 2171 2172 2173 <enum 1 sw_frame_group_Multicast_data> 2174 2175 <enum 2 sw_frame_group_Unicast_data> 2176 2177 <enum 3 sw_frame_group_Null_data > This includes mpdus 2178 of type Data Null as well as QoS Data Null 2179 2180 2181 2182 <enum 4 sw_frame_group_mgmt_0000 > 2183 2184 <enum 5 sw_frame_group_mgmt_0001 > 2185 2186 <enum 6 sw_frame_group_mgmt_0010 > 2187 2188 <enum 7 sw_frame_group_mgmt_0011 > 2189 2190 <enum 8 sw_frame_group_mgmt_0100 > 2191 2192 <enum 9 sw_frame_group_mgmt_0101 > 2193 2194 <enum 10 sw_frame_group_mgmt_0110 > 2195 2196 <enum 11 sw_frame_group_mgmt_0111 > 2197 2198 <enum 12 sw_frame_group_mgmt_1000 > 2199 2200 <enum 13 sw_frame_group_mgmt_1001 > 2201 2202 <enum 14 sw_frame_group_mgmt_1010 > 2203 2204 <enum 15 sw_frame_group_mgmt_1011 > 2205 2206 <enum 16 sw_frame_group_mgmt_1100 > 2207 2208 <enum 17 sw_frame_group_mgmt_1101 > 2209 2210 <enum 18 sw_frame_group_mgmt_1110 > 2211 2212 <enum 19 sw_frame_group_mgmt_1111 > 2213 2214 2215 2216 <enum 20 sw_frame_group_ctrl_0000 > 2217 2218 <enum 21 sw_frame_group_ctrl_0001 > 2219 2220 <enum 22 sw_frame_group_ctrl_0010 > 2221 2222 <enum 23 sw_frame_group_ctrl_0011 > 2223 2224 <enum 24 sw_frame_group_ctrl_0100 > 2225 2226 <enum 25 sw_frame_group_ctrl_0101 > 2227 2228 <enum 26 sw_frame_group_ctrl_0110 > 2229 2230 <enum 27 sw_frame_group_ctrl_0111 > 2231 2232 <enum 28 sw_frame_group_ctrl_1000 > 2233 2234 <enum 29 sw_frame_group_ctrl_1001 > 2235 2236 <enum 30 sw_frame_group_ctrl_1010 > 2237 2238 <enum 31 sw_frame_group_ctrl_1011 > 2239 2240 <enum 32 sw_frame_group_ctrl_1100 > 2241 2242 <enum 33 sw_frame_group_ctrl_1101 > 2243 2244 <enum 34 sw_frame_group_ctrl_1110 > 2245 2246 <enum 35 sw_frame_group_ctrl_1111 > 2247 2248 2249 2250 <enum 36 sw_frame_group_unsupported> This covers type 3 2251 and protocol version != 0 2252 2253 Note: The corresponding Rxpcu_Mpdu_filter_in_category 2254 can only be rxpcu_monitor_other 2255 2256 2257 2258 2259 Note: The corresponding Rxpcu_Mpdu_filter_in_category 2260 can be rxpcu_filter_pass 2261 2262 2263 2264 <legal 0-37> 2265 */ 2266 #define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET 0x00000024 2267 #define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB 2 2268 #define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK 0x000001fc 2269 2270 /* Description RX_MPDU_INFO_9_NDP_FRAME 2271 2272 When set, the received frame was an NDP frame, and thus 2273 there will be no MPDU data. 2274 2275 <legal all> 2276 */ 2277 #define RX_MPDU_INFO_9_NDP_FRAME_OFFSET 0x00000024 2278 #define RX_MPDU_INFO_9_NDP_FRAME_LSB 9 2279 #define RX_MPDU_INFO_9_NDP_FRAME_MASK 0x00000200 2280 2281 /* Description RX_MPDU_INFO_9_PHY_ERR 2282 2283 When set, a PHY error was received before MAC received 2284 any data, and thus there will be no MPDU data. 2285 2286 <legal all> 2287 */ 2288 #define RX_MPDU_INFO_9_PHY_ERR_OFFSET 0x00000024 2289 #define RX_MPDU_INFO_9_PHY_ERR_LSB 10 2290 #define RX_MPDU_INFO_9_PHY_ERR_MASK 0x00000400 2291 2292 /* Description RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER 2293 2294 When set, a PHY error was received before MAC received 2295 the complete MPDU header which was needed for proper 2296 decoding 2297 2298 <legal all> 2299 */ 2300 #define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 2301 #define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_LSB 11 2302 #define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 2303 2304 /* Description RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR 2305 2306 Set when RXPCU detected a version error in the Frame 2307 control field 2308 2309 <legal all> 2310 */ 2311 #define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 2312 #define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_LSB 12 2313 #define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_MASK 0x00001000 2314 2315 /* Description RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID 2316 2317 When set, AST based lookup for this frame has found a 2318 valid result. 2319 2320 2321 2322 Note that for NDP frame this will never be set 2323 2324 <legal all> 2325 */ 2326 #define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 2327 #define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_LSB 13 2328 #define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_MASK 0x00002000 2329 2330 /* Description RX_MPDU_INFO_9_RESERVED_0A 2331 2332 <legal 0> 2333 */ 2334 #define RX_MPDU_INFO_9_RESERVED_0A_OFFSET 0x00000024 2335 #define RX_MPDU_INFO_9_RESERVED_0A_LSB 14 2336 #define RX_MPDU_INFO_9_RESERVED_0A_MASK 0x0000c000 2337 2338 /* Description RX_MPDU_INFO_9_PHY_PPDU_ID 2339 2340 A ppdu counter value that PHY increments for every PPDU 2341 received. The counter value wraps around 2342 2343 <legal all> 2344 */ 2345 #define RX_MPDU_INFO_9_PHY_PPDU_ID_OFFSET 0x00000024 2346 #define RX_MPDU_INFO_9_PHY_PPDU_ID_LSB 16 2347 #define RX_MPDU_INFO_9_PHY_PPDU_ID_MASK 0xffff0000 2348 2349 /* Description RX_MPDU_INFO_10_AST_INDEX 2350 2351 This field indicates the index of the AST entry 2352 corresponding to this MPDU. It is provided by the GSE module 2353 instantiated in RXPCU. 2354 2355 A value of 0xFFFF indicates an invalid AST index, 2356 meaning that No AST entry was found or NO AST search was 2357 performed 2358 2359 2360 2361 In case of ndp or phy_err, this field will be set to 2362 0xFFFF 2363 2364 <legal all> 2365 */ 2366 #define RX_MPDU_INFO_10_AST_INDEX_OFFSET 0x00000028 2367 #define RX_MPDU_INFO_10_AST_INDEX_LSB 0 2368 #define RX_MPDU_INFO_10_AST_INDEX_MASK 0x0000ffff 2369 2370 /* Description RX_MPDU_INFO_10_SW_PEER_ID 2371 2372 In case of ndp or phy_err or AST_based_lookup_valid == 2373 0, this field will be set to 0 2374 2375 2376 2377 This field indicates a unique peer identifier. It is set 2378 equal to field 'sw_peer_id' from the AST entry 2379 2380 2381 2382 <legal all> 2383 */ 2384 #define RX_MPDU_INFO_10_SW_PEER_ID_OFFSET 0x00000028 2385 #define RX_MPDU_INFO_10_SW_PEER_ID_LSB 16 2386 #define RX_MPDU_INFO_10_SW_PEER_ID_MASK 0xffff0000 2387 2388 /* Description RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID 2389 2390 When set, the field Mpdu_Frame_control_field has valid 2391 information 2392 2393 2394 2395 2396 <legal all> 2397 */ 2398 #define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c 2399 #define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB 0 2400 #define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 2401 2402 /* Description RX_MPDU_INFO_11_MPDU_DURATION_VALID 2403 2404 When set, the field Mpdu_duration_field has valid 2405 information 2406 2407 2408 2409 2410 <legal all> 2411 */ 2412 #define RX_MPDU_INFO_11_MPDU_DURATION_VALID_OFFSET 0x0000002c 2413 #define RX_MPDU_INFO_11_MPDU_DURATION_VALID_LSB 1 2414 #define RX_MPDU_INFO_11_MPDU_DURATION_VALID_MASK 0x00000002 2415 2416 /* Description RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID 2417 2418 When set, the fields mac_addr_ad1_..... have valid 2419 information 2420 2421 2422 2423 2424 <legal all> 2425 */ 2426 #define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c 2427 #define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB 2 2428 #define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK 0x00000004 2429 2430 /* Description RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID 2431 2432 When set, the fields mac_addr_ad2_..... have valid 2433 information 2434 2435 2436 2437 2438 2439 2440 2441 <legal all> 2442 */ 2443 #define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c 2444 #define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB 3 2445 #define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK 0x00000008 2446 2447 /* Description RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID 2448 2449 When set, the fields mac_addr_ad3_..... have valid 2450 information 2451 2452 2453 2454 2455 2456 2457 2458 <legal all> 2459 */ 2460 #define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c 2461 #define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB 4 2462 #define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK 0x00000010 2463 2464 /* Description RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID 2465 2466 When set, the fields mac_addr_ad4_..... have valid 2467 information 2468 2469 2470 2471 2472 2473 2474 2475 <legal all> 2476 */ 2477 #define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c 2478 #define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB 5 2479 #define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK 0x00000020 2480 2481 /* Description RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID 2482 2483 When set, the fields mpdu_sequence_control_field and 2484 mpdu_sequence_number have valid information as well as field 2485 2486 2487 2488 For MPDUs without a sequence control field, this field 2489 will not be set. 2490 2491 2492 2493 2494 <legal all> 2495 */ 2496 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c 2497 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 2498 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 2499 2500 /* Description RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID 2501 2502 When set, the field mpdu_qos_control_field has valid 2503 information 2504 2505 2506 2507 For MPDUs without a QoS control field, this field will 2508 not be set. 2509 2510 2511 2512 2513 <legal all> 2514 */ 2515 #define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c 2516 #define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB 7 2517 #define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 2518 2519 /* Description RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID 2520 2521 When set, the field mpdu_HT_control_field has valid 2522 information 2523 2524 2525 2526 For MPDUs without a HT control field, this field will 2527 not be set. 2528 2529 2530 2531 2532 <legal all> 2533 */ 2534 #define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c 2535 #define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_LSB 8 2536 #define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_MASK 0x00000100 2537 2538 /* Description RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID 2539 2540 When set, the encryption related info fields, like IV 2541 and PN are valid 2542 2543 2544 2545 For MPDUs that are not encrypted, this will not be set. 2546 2547 2548 2549 2550 <legal all> 2551 */ 2552 #define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c 2553 #define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB 9 2554 #define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 2555 2556 /* Description RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER 2557 2558 Field only valid when Mpdu_sequence_control_valid is set 2559 AND Fragment_flag is set 2560 2561 2562 2563 The fragment number from the 802.11 header 2564 2565 2566 2567 <legal all> 2568 */ 2569 #define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c 2570 #define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_LSB 10 2571 #define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 2572 2573 /* Description RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG 2574 2575 The More Fragment bit setting from the MPDU header of 2576 the received frame 2577 2578 2579 2580 <legal all> 2581 */ 2582 #define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c 2583 #define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_LSB 14 2584 #define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_MASK 0x00004000 2585 2586 /* Description RX_MPDU_INFO_11_RESERVED_2A 2587 2588 <legal 0> 2589 */ 2590 #define RX_MPDU_INFO_11_RESERVED_2A_OFFSET 0x0000002c 2591 #define RX_MPDU_INFO_11_RESERVED_2A_LSB 15 2592 #define RX_MPDU_INFO_11_RESERVED_2A_MASK 0x00008000 2593 2594 /* Description RX_MPDU_INFO_11_FR_DS 2595 2596 Field only valid when Mpdu_frame_control_valid is set 2597 2598 2599 2600 Set if the from DS bit is set in the frame control. 2601 2602 <legal all> 2603 */ 2604 #define RX_MPDU_INFO_11_FR_DS_OFFSET 0x0000002c 2605 #define RX_MPDU_INFO_11_FR_DS_LSB 16 2606 #define RX_MPDU_INFO_11_FR_DS_MASK 0x00010000 2607 2608 /* Description RX_MPDU_INFO_11_TO_DS 2609 2610 Field only valid when Mpdu_frame_control_valid is set 2611 2612 2613 2614 Set if the to DS bit is set in the frame control. 2615 2616 <legal all> 2617 */ 2618 #define RX_MPDU_INFO_11_TO_DS_OFFSET 0x0000002c 2619 #define RX_MPDU_INFO_11_TO_DS_LSB 17 2620 #define RX_MPDU_INFO_11_TO_DS_MASK 0x00020000 2621 2622 /* Description RX_MPDU_INFO_11_ENCRYPTED 2623 2624 Field only valid when Mpdu_frame_control_valid is set. 2625 2626 2627 2628 Protected bit from the frame control. 2629 2630 <legal all> 2631 */ 2632 #define RX_MPDU_INFO_11_ENCRYPTED_OFFSET 0x0000002c 2633 #define RX_MPDU_INFO_11_ENCRYPTED_LSB 18 2634 #define RX_MPDU_INFO_11_ENCRYPTED_MASK 0x00040000 2635 2636 /* Description RX_MPDU_INFO_11_MPDU_RETRY 2637 2638 Field only valid when Mpdu_frame_control_valid is set. 2639 2640 2641 2642 Retry bit from the frame control. Only valid when 2643 first_msdu is set. 2644 2645 <legal all> 2646 */ 2647 #define RX_MPDU_INFO_11_MPDU_RETRY_OFFSET 0x0000002c 2648 #define RX_MPDU_INFO_11_MPDU_RETRY_LSB 19 2649 #define RX_MPDU_INFO_11_MPDU_RETRY_MASK 0x00080000 2650 2651 /* Description RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER 2652 2653 Field only valid when Mpdu_sequence_control_valid is 2654 set. 2655 2656 2657 2658 The sequence number from the 802.11 header. 2659 2660 <legal all> 2661 */ 2662 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c 2663 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB 20 2664 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 2665 2666 /* Description RX_MPDU_INFO_12_KEY_ID_OCTET 2667 2668 2669 2670 2671 The key ID octet from the IV. 2672 2673 2674 2675 In case of ndp or phy_err or AST_based_lookup_valid == 2676 0, this field will be set to 0 2677 2678 <legal all> 2679 */ 2680 #define RX_MPDU_INFO_12_KEY_ID_OCTET_OFFSET 0x00000030 2681 #define RX_MPDU_INFO_12_KEY_ID_OCTET_LSB 0 2682 #define RX_MPDU_INFO_12_KEY_ID_OCTET_MASK 0x000000ff 2683 2684 /* Description RX_MPDU_INFO_12_NEW_PEER_ENTRY 2685 2686 In case of ndp or phy_err or AST_based_lookup_valid == 2687 0, this field will be set to 0 2688 2689 2690 2691 Set if new RX_PEER_ENTRY TLV follows. If clear, 2692 RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either 2693 uses old peer entry or not decrypt. 2694 2695 <legal all> 2696 */ 2697 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_OFFSET 0x00000030 2698 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_LSB 8 2699 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_MASK 0x00000100 2700 2701 /* Description RX_MPDU_INFO_12_DECRYPT_NEEDED 2702 2703 In case of ndp or phy_err or AST_based_lookup_valid == 2704 0, this field will be set to 0 2705 2706 2707 2708 Set if decryption is needed. 2709 2710 2711 2712 Note: 2713 2714 When RXPCU sets bit 'ast_index_not_found' and/or 2715 ast_index_timeout', RXPCU will also ensure that this bit is 2716 NOT set 2717 2718 CRYPTO for that reason only needs to evaluate this bit 2719 and non of the other ones. 2720 2721 <legal all> 2722 */ 2723 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_OFFSET 0x00000030 2724 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_LSB 9 2725 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_MASK 0x00000200 2726 2727 /* Description RX_MPDU_INFO_12_DECAP_TYPE 2728 2729 In case of ndp or phy_err or AST_based_lookup_valid == 2730 0, this field will be set to 0 2731 2732 2733 2734 Used by the OLE during decapsulation. 2735 2736 2737 2738 Indicates the decapsulation that HW will perform: 2739 2740 2741 2742 <enum 0 RAW> No encapsulation 2743 2744 <enum 1 Native_WiFi> 2745 2746 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses 2747 SNAP/LLC) 2748 2749 <enum 3 802_3> Indicate Ethernet 2750 2751 2752 2753 <legal all> 2754 */ 2755 #define RX_MPDU_INFO_12_DECAP_TYPE_OFFSET 0x00000030 2756 #define RX_MPDU_INFO_12_DECAP_TYPE_LSB 10 2757 #define RX_MPDU_INFO_12_DECAP_TYPE_MASK 0x00000c00 2758 2759 /* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING 2760 2761 In case of ndp or phy_err or AST_based_lookup_valid == 2762 0, this field will be set to 0 2763 2764 2765 2766 Insert 4 byte of all zeros as VLAN tag if the rx payload 2767 does not have VLAN. Used during decapsulation. 2768 2769 <legal all> 2770 */ 2771 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 2772 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 2773 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 2774 2775 /* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING 2776 2777 In case of ndp or phy_err or AST_based_lookup_valid == 2778 0, this field will be set to 0 2779 2780 2781 2782 Insert 4 byte of all zeros as double VLAN tag if the rx 2783 payload does not have VLAN. Used during 2784 2785 <legal all> 2786 */ 2787 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 2788 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 2789 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 2790 2791 /* Description RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP 2792 2793 In case of ndp or phy_err or AST_based_lookup_valid == 2794 0, this field will be set to 0 2795 2796 2797 2798 Strip the VLAN during decapsulation. Used by the OLE. 2799 2800 <legal all> 2801 */ 2802 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 2803 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_LSB 14 2804 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 2805 2806 /* Description RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP 2807 2808 In case of ndp or phy_err or AST_based_lookup_valid == 2809 0, this field will be set to 0 2810 2811 2812 2813 Strip the double VLAN during decapsulation. Used by 2814 the OLE. 2815 2816 <legal all> 2817 */ 2818 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 2819 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_LSB 15 2820 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 2821 2822 /* Description RX_MPDU_INFO_12_PRE_DELIM_COUNT 2823 2824 The number of delimiters before this MPDU. 2825 2826 2827 2828 Note that this number is cleared at PPDU start. 2829 2830 2831 2832 If this MPDU is the first received MPDU in the PPDU and 2833 this MPDU gets filtered-in, this field will indicate the 2834 number of delimiters located after the last MPDU in the 2835 previous PPDU. 2836 2837 2838 2839 If this MPDU is located after the first received MPDU in 2840 an PPDU, this field will indicate the number of delimiters 2841 located between the previous MPDU and this MPDU. 2842 2843 2844 2845 In case of ndp or phy_err, this field will indicate the 2846 number of delimiters located after the last MPDU in the 2847 previous PPDU. 2848 2849 <legal all> 2850 */ 2851 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_OFFSET 0x00000030 2852 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_LSB 16 2853 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_MASK 0x0fff0000 2854 2855 /* Description RX_MPDU_INFO_12_AMPDU_FLAG 2856 2857 When set, received frame was part of an A-MPDU. 2858 2859 2860 2861 2862 <legal all> 2863 */ 2864 #define RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET 0x00000030 2865 #define RX_MPDU_INFO_12_AMPDU_FLAG_LSB 28 2866 #define RX_MPDU_INFO_12_AMPDU_FLAG_MASK 0x10000000 2867 2868 /* Description RX_MPDU_INFO_12_BAR_FRAME 2869 2870 In case of ndp or phy_err or AST_based_lookup_valid == 2871 0, this field will be set to 0 2872 2873 2874 2875 When set, received frame is a BAR frame 2876 2877 <legal all> 2878 */ 2879 #define RX_MPDU_INFO_12_BAR_FRAME_OFFSET 0x00000030 2880 #define RX_MPDU_INFO_12_BAR_FRAME_LSB 29 2881 #define RX_MPDU_INFO_12_BAR_FRAME_MASK 0x20000000 2882 2883 /* Description RX_MPDU_INFO_12_RAW_MPDU 2884 2885 Consumer: SW 2886 2887 Producer: RXOLE 2888 2889 2890 2891 RXPCU sets this field to 0 and RXOLE overwrites it. 2892 2893 2894 2895 Set to 1 by RXOLE when it has not performed any 802.11 2896 to Ethernet/Natvie WiFi header conversion on this MPDU. 2897 2898 <legal all> 2899 */ 2900 #define RX_MPDU_INFO_12_RAW_MPDU_OFFSET 0x00000030 2901 #define RX_MPDU_INFO_12_RAW_MPDU_LSB 30 2902 #define RX_MPDU_INFO_12_RAW_MPDU_MASK 0x40000000 2903 2904 /* Description RX_MPDU_INFO_12_RESERVED_12 2905 2906 <legal 0> 2907 */ 2908 #define RX_MPDU_INFO_12_RESERVED_12_OFFSET 0x00000030 2909 #define RX_MPDU_INFO_12_RESERVED_12_LSB 31 2910 #define RX_MPDU_INFO_12_RESERVED_12_MASK 0x80000000 2911 2912 /* Description RX_MPDU_INFO_13_MPDU_LENGTH 2913 2914 In case of ndp or phy_err this field will be set to 0 2915 2916 2917 2918 MPDU length before decapsulation. 2919 2920 <legal all> 2921 */ 2922 #define RX_MPDU_INFO_13_MPDU_LENGTH_OFFSET 0x00000034 2923 #define RX_MPDU_INFO_13_MPDU_LENGTH_LSB 0 2924 #define RX_MPDU_INFO_13_MPDU_LENGTH_MASK 0x00003fff 2925 2926 /* Description RX_MPDU_INFO_13_FIRST_MPDU 2927 2928 See definition in RX attention descriptor 2929 2930 2931 2932 In case of ndp or phy_err, this field will be set. Note 2933 however that there will not actually be any data contents in 2934 the MPDU. 2935 2936 <legal all> 2937 */ 2938 #define RX_MPDU_INFO_13_FIRST_MPDU_OFFSET 0x00000034 2939 #define RX_MPDU_INFO_13_FIRST_MPDU_LSB 14 2940 #define RX_MPDU_INFO_13_FIRST_MPDU_MASK 0x00004000 2941 2942 /* Description RX_MPDU_INFO_13_MCAST_BCAST 2943 2944 In case of ndp or phy_err or Phy_err_during_mpdu_header 2945 this field will be set to 0 2946 2947 2948 2949 See definition in RX attention descriptor 2950 2951 <legal all> 2952 */ 2953 #define RX_MPDU_INFO_13_MCAST_BCAST_OFFSET 0x00000034 2954 #define RX_MPDU_INFO_13_MCAST_BCAST_LSB 15 2955 #define RX_MPDU_INFO_13_MCAST_BCAST_MASK 0x00008000 2956 2957 /* Description RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND 2958 2959 In case of ndp or phy_err or Phy_err_during_mpdu_header 2960 this field will be set to 0 2961 2962 2963 2964 See definition in RX attention descriptor 2965 2966 <legal all> 2967 */ 2968 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 2969 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_LSB 16 2970 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_MASK 0x00010000 2971 2972 /* Description RX_MPDU_INFO_13_AST_INDEX_TIMEOUT 2973 2974 In case of ndp or phy_err or Phy_err_during_mpdu_header 2975 this field will be set to 0 2976 2977 2978 2979 See definition in RX attention descriptor 2980 2981 <legal all> 2982 */ 2983 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_OFFSET 0x00000034 2984 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_LSB 17 2985 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_MASK 0x00020000 2986 2987 /* Description RX_MPDU_INFO_13_POWER_MGMT 2988 2989 In case of ndp or phy_err or Phy_err_during_mpdu_header 2990 this field will be set to 0 2991 2992 2993 2994 See definition in RX attention descriptor 2995 2996 <legal all> 2997 */ 2998 #define RX_MPDU_INFO_13_POWER_MGMT_OFFSET 0x00000034 2999 #define RX_MPDU_INFO_13_POWER_MGMT_LSB 18 3000 #define RX_MPDU_INFO_13_POWER_MGMT_MASK 0x00040000 3001 3002 /* Description RX_MPDU_INFO_13_NON_QOS 3003 3004 In case of ndp or phy_err or Phy_err_during_mpdu_header 3005 this field will be set to 1 3006 3007 3008 3009 See definition in RX attention descriptor 3010 3011 <legal all> 3012 */ 3013 #define RX_MPDU_INFO_13_NON_QOS_OFFSET 0x00000034 3014 #define RX_MPDU_INFO_13_NON_QOS_LSB 19 3015 #define RX_MPDU_INFO_13_NON_QOS_MASK 0x00080000 3016 3017 /* Description RX_MPDU_INFO_13_NULL_DATA 3018 3019 In case of ndp or phy_err or Phy_err_during_mpdu_header 3020 this field will be set to 0 3021 3022 3023 3024 See definition in RX attention descriptor 3025 3026 <legal all> 3027 */ 3028 #define RX_MPDU_INFO_13_NULL_DATA_OFFSET 0x00000034 3029 #define RX_MPDU_INFO_13_NULL_DATA_LSB 20 3030 #define RX_MPDU_INFO_13_NULL_DATA_MASK 0x00100000 3031 3032 /* Description RX_MPDU_INFO_13_MGMT_TYPE 3033 3034 In case of ndp or phy_err or Phy_err_during_mpdu_header 3035 this field will be set to 0 3036 3037 3038 3039 See definition in RX attention descriptor 3040 3041 <legal all> 3042 */ 3043 #define RX_MPDU_INFO_13_MGMT_TYPE_OFFSET 0x00000034 3044 #define RX_MPDU_INFO_13_MGMT_TYPE_LSB 21 3045 #define RX_MPDU_INFO_13_MGMT_TYPE_MASK 0x00200000 3046 3047 /* Description RX_MPDU_INFO_13_CTRL_TYPE 3048 3049 In case of ndp or phy_err or Phy_err_during_mpdu_header 3050 this field will be set to 0 3051 3052 3053 3054 See definition in RX attention descriptor 3055 3056 <legal all> 3057 */ 3058 #define RX_MPDU_INFO_13_CTRL_TYPE_OFFSET 0x00000034 3059 #define RX_MPDU_INFO_13_CTRL_TYPE_LSB 22 3060 #define RX_MPDU_INFO_13_CTRL_TYPE_MASK 0x00400000 3061 3062 /* Description RX_MPDU_INFO_13_MORE_DATA 3063 3064 In case of ndp or phy_err or Phy_err_during_mpdu_header 3065 this field will be set to 0 3066 3067 3068 3069 See definition in RX attention descriptor 3070 3071 <legal all> 3072 */ 3073 #define RX_MPDU_INFO_13_MORE_DATA_OFFSET 0x00000034 3074 #define RX_MPDU_INFO_13_MORE_DATA_LSB 23 3075 #define RX_MPDU_INFO_13_MORE_DATA_MASK 0x00800000 3076 3077 /* Description RX_MPDU_INFO_13_EOSP 3078 3079 In case of ndp or phy_err or Phy_err_during_mpdu_header 3080 this field will be set to 0 3081 3082 3083 3084 See definition in RX attention descriptor 3085 3086 <legal all> 3087 */ 3088 #define RX_MPDU_INFO_13_EOSP_OFFSET 0x00000034 3089 #define RX_MPDU_INFO_13_EOSP_LSB 24 3090 #define RX_MPDU_INFO_13_EOSP_MASK 0x01000000 3091 3092 /* Description RX_MPDU_INFO_13_FRAGMENT_FLAG 3093 3094 In case of ndp or phy_err or Phy_err_during_mpdu_header 3095 this field will be set to 0 3096 3097 3098 3099 See definition in RX attention descriptor 3100 3101 <legal all> 3102 */ 3103 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_OFFSET 0x00000034 3104 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_LSB 25 3105 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_MASK 0x02000000 3106 3107 /* Description RX_MPDU_INFO_13_ORDER 3108 3109 In case of ndp or phy_err or Phy_err_during_mpdu_header 3110 this field will be set to 0 3111 3112 3113 3114 See definition in RX attention descriptor 3115 3116 3117 3118 <legal all> 3119 */ 3120 #define RX_MPDU_INFO_13_ORDER_OFFSET 0x00000034 3121 #define RX_MPDU_INFO_13_ORDER_LSB 26 3122 #define RX_MPDU_INFO_13_ORDER_MASK 0x04000000 3123 3124 /* Description RX_MPDU_INFO_13_U_APSD_TRIGGER 3125 3126 In case of ndp or phy_err or Phy_err_during_mpdu_header 3127 this field will be set to 0 3128 3129 3130 3131 See definition in RX attention descriptor 3132 3133 <legal all> 3134 */ 3135 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_OFFSET 0x00000034 3136 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_LSB 27 3137 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_MASK 0x08000000 3138 3139 /* Description RX_MPDU_INFO_13_ENCRYPT_REQUIRED 3140 3141 In case of ndp or phy_err or Phy_err_during_mpdu_header 3142 this field will be set to 0 3143 3144 3145 3146 See definition in RX attention descriptor 3147 3148 <legal all> 3149 */ 3150 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_OFFSET 0x00000034 3151 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_LSB 28 3152 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_MASK 0x10000000 3153 3154 /* Description RX_MPDU_INFO_13_DIRECTED 3155 3156 In case of ndp or phy_err or Phy_err_during_mpdu_header 3157 this field will be set to 0 3158 3159 3160 3161 See definition in RX attention descriptor 3162 3163 <legal all> 3164 */ 3165 #define RX_MPDU_INFO_13_DIRECTED_OFFSET 0x00000034 3166 #define RX_MPDU_INFO_13_DIRECTED_LSB 29 3167 #define RX_MPDU_INFO_13_DIRECTED_MASK 0x20000000 3168 3169 /* Description RX_MPDU_INFO_13_AMSDU_PRESENT 3170 3171 Field only valid when Mpdu_qos_control_valid is set 3172 3173 3174 3175 The 'amsdu_present' bit within the QoS control field of 3176 the MPDU 3177 3178 <legal all> 3179 */ 3180 #define RX_MPDU_INFO_13_AMSDU_PRESENT_OFFSET 0x00000034 3181 #define RX_MPDU_INFO_13_AMSDU_PRESENT_LSB 30 3182 #define RX_MPDU_INFO_13_AMSDU_PRESENT_MASK 0x40000000 3183 3184 /* Description RX_MPDU_INFO_13_RESERVED_13 3185 3186 <legal 0> 3187 */ 3188 #define RX_MPDU_INFO_13_RESERVED_13_OFFSET 0x00000034 3189 #define RX_MPDU_INFO_13_RESERVED_13_LSB 31 3190 #define RX_MPDU_INFO_13_RESERVED_13_MASK 0x80000000 3191 3192 /* Description RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD 3193 3194 Field only valid when Mpdu_frame_control_valid is set 3195 3196 3197 3198 The frame control field of this received MPDU. 3199 3200 3201 3202 Field only valid when Ndp_frame and phy_err are NOT set 3203 3204 3205 3206 Bytes 0 + 1 of the received MPDU 3207 3208 <legal all> 3209 */ 3210 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 3211 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB 0 3212 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff 3213 3214 /* Description RX_MPDU_INFO_14_MPDU_DURATION_FIELD 3215 3216 Field only valid when Mpdu_duration_valid is set 3217 3218 3219 3220 The duration field of this received MPDU. 3221 3222 <legal all> 3223 */ 3224 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_OFFSET 0x00000038 3225 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_LSB 16 3226 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_MASK 0xffff0000 3227 3228 /* Description RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0 3229 3230 Field only valid when mac_addr_ad1_valid is set 3231 3232 3233 3234 The Least Significant 4 bytes of the Received Frames MAC 3235 Address AD1 3236 3237 <legal all> 3238 */ 3239 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c 3240 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB 0 3241 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK 0xffffffff 3242 3243 /* Description RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32 3244 3245 Field only valid when mac_addr_ad1_valid is set 3246 3247 3248 3249 The 2 most significant bytes of the Received Frames MAC 3250 Address AD1 3251 3252 <legal all> 3253 */ 3254 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 3255 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB 0 3256 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK 0x0000ffff 3257 3258 /* Description RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0 3259 3260 Field only valid when mac_addr_ad2_valid is set 3261 3262 3263 3264 The Least Significant 2 bytes of the Received Frames MAC 3265 Address AD2 3266 3267 <legal all> 3268 */ 3269 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 3270 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB 16 3271 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK 0xffff0000 3272 3273 /* Description RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16 3274 3275 Field only valid when mac_addr_ad2_valid is set 3276 3277 3278 3279 The 4 most significant bytes of the Received Frames MAC 3280 Address AD2 3281 3282 <legal all> 3283 */ 3284 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 3285 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB 0 3286 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK 0xffffffff 3287 3288 /* Description RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0 3289 3290 Field only valid when mac_addr_ad3_valid is set 3291 3292 3293 3294 The Least Significant 4 bytes of the Received Frames MAC 3295 Address AD3 3296 3297 <legal all> 3298 */ 3299 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 3300 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB 0 3301 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK 0xffffffff 3302 3303 /* Description RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32 3304 3305 Field only valid when mac_addr_ad3_valid is set 3306 3307 3308 3309 The 2 most significant bytes of the Received Frames MAC 3310 Address AD3 3311 3312 <legal all> 3313 */ 3314 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c 3315 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB 0 3316 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK 0x0000ffff 3317 3318 /* Description RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD 3319 3320 3321 3322 3323 The sequence control field of the MPDU 3324 3325 <legal all> 3326 */ 3327 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c 3328 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 3329 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 3330 3331 /* Description RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0 3332 3333 Field only valid when mac_addr_ad4_valid is set 3334 3335 3336 3337 The Least Significant 4 bytes of the Received Frames MAC 3338 Address AD4 3339 3340 <legal all> 3341 */ 3342 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 3343 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB 0 3344 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK 0xffffffff 3345 3346 /* Description RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32 3347 3348 Field only valid when mac_addr_ad4_valid is set 3349 3350 3351 3352 The 2 most significant bytes of the Received Frames MAC 3353 Address AD4 3354 3355 <legal all> 3356 */ 3357 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 3358 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB 0 3359 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK 0x0000ffff 3360 3361 /* Description RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD 3362 3363 Field only valid when mpdu_qos_control_valid is set 3364 3365 3366 3367 The sequence control field of the MPDU 3368 3369 <legal all> 3370 */ 3371 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 3372 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_LSB 16 3373 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 3374 3375 /* Description RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD 3376 3377 Field only valid when mpdu_qos_control_valid is set 3378 3379 3380 3381 The HT control field of the MPDU 3382 3383 <legal all> 3384 */ 3385 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 3386 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_LSB 0 3387 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff 3388 3389 3390 #endif // _RX_MPDU_INFO_H_ 3391