1 /* 2 * Copyright (c) 2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _RX_MSDU_END_H_ 25 #define _RX_MSDU_END_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 30 // ################ START SUMMARY ################# 31 // 32 // Dword Fields 33 // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] 34 // 1 ip_hdr_chksum[15:0], reported_mpdu_length[29:16], reserved_1a[31:30] 35 // 2 key_id_octet[7:0], cce_super_rule[13:8], cce_classify_not_done_truncate[14], cce_classify_not_done_cce_dis[15], ext_wapi_pn_63_48[31:16] 36 // 3 ext_wapi_pn_95_64[31:0] 37 // 4 ext_wapi_pn_127_96[31:0] 38 // 5 da_offset[5:0], sa_offset[11:6], da_offset_valid[12], sa_offset_valid[13], reserved_10a[15:14], l3_type[31:16] 39 // 6 ipv6_options_crc[31:0] 40 // 7 tcp_seq_number[31:0] 41 // 8 tcp_ack_number[31:0] 42 // 9 tcp_flag[8:0], lro_eligible[9], reserved_9a[15:10], window_size[31:16] 43 // 10 tcp_udp_chksum[15:0], sa_idx_timeout[16], da_idx_timeout[17], msdu_limit_error[18], flow_idx_timeout[19], flow_idx_invalid[20], wifi_parser_error[21], amsdu_parser_error[22], sa_is_valid[23], da_is_valid[24], da_is_mcbc[25], l3_header_padding[27:26], first_msdu[28], last_msdu[29], reserved_5a[31:30] 44 // 11 sa_idx[15:0], da_idx_or_sw_peer_id[31:16] 45 // 12 msdu_drop[0], reo_destination_indication[5:1], flow_idx[25:6], reserved_14[31:26] 46 // 13 fse_metadata[31:0] 47 // 14 cce_metadata[15:0], sa_sw_peer_id[31:16] 48 // 15 rule_indication_31_0[31:0] 49 // 16 rule_indication_63_32[31:0] 50 // 17 aggregation_count[7:0], flow_aggregation_continuation[8], fisa_timeout[9], reserve_17a[31:10] 51 // 18 cumulative_l4_checksum[15:0], cumulative_ip_length[31:16] 52 // 53 // ################ END SUMMARY ################# 54 55 #define NUM_OF_DWORDS_RX_MSDU_END 19 56 57 struct rx_msdu_end { 58 uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] 59 sw_frame_group_id : 7, //[8:2] 60 reserved_0 : 7, //[15:9] 61 phy_ppdu_id : 16; //[31:16] 62 uint32_t ip_hdr_chksum : 16, //[15:0] 63 reported_mpdu_length : 14, //[29:16] 64 reserved_1a : 2; //[31:30] 65 uint32_t key_id_octet : 8, //[7:0] 66 cce_super_rule : 6, //[13:8] 67 cce_classify_not_done_truncate : 1, //[14] 68 cce_classify_not_done_cce_dis : 1, //[15] 69 ext_wapi_pn_63_48 : 16; //[31:16] 70 uint32_t ext_wapi_pn_95_64 : 32; //[31:0] 71 uint32_t ext_wapi_pn_127_96 : 32; //[31:0] 72 uint32_t da_offset : 6, //[5:0] 73 sa_offset : 6, //[11:6] 74 da_offset_valid : 1, //[12] 75 sa_offset_valid : 1, //[13] 76 reserved_10a : 2, //[15:14] 77 l3_type : 16; //[31:16] 78 uint32_t ipv6_options_crc : 32; //[31:0] 79 uint32_t tcp_seq_number : 32; //[31:0] 80 uint32_t tcp_ack_number : 32; //[31:0] 81 uint32_t tcp_flag : 9, //[8:0] 82 lro_eligible : 1, //[9] 83 reserved_9a : 6, //[15:10] 84 window_size : 16; //[31:16] 85 uint32_t tcp_udp_chksum : 16, //[15:0] 86 sa_idx_timeout : 1, //[16] 87 da_idx_timeout : 1, //[17] 88 msdu_limit_error : 1, //[18] 89 flow_idx_timeout : 1, //[19] 90 flow_idx_invalid : 1, //[20] 91 wifi_parser_error : 1, //[21] 92 amsdu_parser_error : 1, //[22] 93 sa_is_valid : 1, //[23] 94 da_is_valid : 1, //[24] 95 da_is_mcbc : 1, //[25] 96 l3_header_padding : 2, //[27:26] 97 first_msdu : 1, //[28] 98 last_msdu : 1, //[29] 99 reserved_5a : 2; //[31:30] 100 uint32_t sa_idx : 16, //[15:0] 101 da_idx_or_sw_peer_id : 16; //[31:16] 102 uint32_t msdu_drop : 1, //[0] 103 reo_destination_indication : 5, //[5:1] 104 flow_idx : 20, //[25:6] 105 reserved_14 : 6; //[31:26] 106 uint32_t fse_metadata : 32; //[31:0] 107 uint32_t cce_metadata : 16, //[15:0] 108 sa_sw_peer_id : 16; //[31:16] 109 uint32_t rule_indication_31_0 : 32; //[31:0] 110 uint32_t rule_indication_63_32 : 32; //[31:0] 111 uint32_t aggregation_count : 8, //[7:0] 112 flow_aggregation_continuation : 1, //[8] 113 fisa_timeout : 1, //[9] 114 reserve_17a : 22; //[31:10] 115 uint32_t cumulative_l4_checksum : 16, //[15:0] 116 cumulative_ip_length : 16; //[31:16] 117 }; 118 119 /* 120 121 rxpcu_mpdu_filter_in_category 122 123 Field indicates what the reason was that this MPDU frame 124 was allowed to come into the receive path by RXPCU 125 126 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 127 frame filter programming of rxpcu 128 129 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 130 regular frame filter and would have been dropped, were it 131 not for the frame fitting into the 'monitor_client' 132 category. 133 134 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 135 regular frame filter and also did not pass the 136 rxpcu_monitor_client filter. It would have been dropped 137 accept that it did pass the 'monitor_other' category. 138 139 <legal 0-2> 140 141 sw_frame_group_id 142 143 SW processes frames based on certain classifications. 144 This field indicates to what sw classification this MPDU is 145 mapped. 146 147 The classification is given in priority order 148 149 150 151 <enum 0 sw_frame_group_NDP_frame> 152 153 154 155 <enum 1 sw_frame_group_Multicast_data> 156 157 <enum 2 sw_frame_group_Unicast_data> 158 159 <enum 3 sw_frame_group_Null_data > This includes mpdus 160 of type Data Null as well as QoS Data Null 161 162 163 164 <enum 4 sw_frame_group_mgmt_0000 > 165 166 <enum 5 sw_frame_group_mgmt_0001 > 167 168 <enum 6 sw_frame_group_mgmt_0010 > 169 170 <enum 7 sw_frame_group_mgmt_0011 > 171 172 <enum 8 sw_frame_group_mgmt_0100 > 173 174 <enum 9 sw_frame_group_mgmt_0101 > 175 176 <enum 10 sw_frame_group_mgmt_0110 > 177 178 <enum 11 sw_frame_group_mgmt_0111 > 179 180 <enum 12 sw_frame_group_mgmt_1000 > 181 182 <enum 13 sw_frame_group_mgmt_1001 > 183 184 <enum 14 sw_frame_group_mgmt_1010 > 185 186 <enum 15 sw_frame_group_mgmt_1011 > 187 188 <enum 16 sw_frame_group_mgmt_1100 > 189 190 <enum 17 sw_frame_group_mgmt_1101 > 191 192 <enum 18 sw_frame_group_mgmt_1110 > 193 194 <enum 19 sw_frame_group_mgmt_1111 > 195 196 197 198 <enum 20 sw_frame_group_ctrl_0000 > 199 200 <enum 21 sw_frame_group_ctrl_0001 > 201 202 <enum 22 sw_frame_group_ctrl_0010 > 203 204 <enum 23 sw_frame_group_ctrl_0011 > 205 206 <enum 24 sw_frame_group_ctrl_0100 > 207 208 <enum 25 sw_frame_group_ctrl_0101 > 209 210 <enum 26 sw_frame_group_ctrl_0110 > 211 212 <enum 27 sw_frame_group_ctrl_0111 > 213 214 <enum 28 sw_frame_group_ctrl_1000 > 215 216 <enum 29 sw_frame_group_ctrl_1001 > 217 218 <enum 30 sw_frame_group_ctrl_1010 > 219 220 <enum 31 sw_frame_group_ctrl_1011 > 221 222 <enum 32 sw_frame_group_ctrl_1100 > 223 224 <enum 33 sw_frame_group_ctrl_1101 > 225 226 <enum 34 sw_frame_group_ctrl_1110 > 227 228 <enum 35 sw_frame_group_ctrl_1111 > 229 230 231 232 <enum 36 sw_frame_group_unsupported> This covers type 3 233 and protocol version != 0 234 235 236 237 238 239 240 <legal 0-37> 241 242 reserved_0 243 244 <legal 0> 245 246 phy_ppdu_id 247 248 A ppdu counter value that PHY increments for every PPDU 249 received. The counter value wraps around 250 251 <legal all> 252 253 ip_hdr_chksum 254 255 This can include the IP header checksum or the pseudo 256 header checksum used by TCP/UDP checksum. 257 258 (with the first byte in the MSB and the second byte in 259 the LSB, i.e. requiring a byte-swap for little-endian FW/SW 260 w.r.t. the byte order in a packet) 261 262 reported_mpdu_length 263 264 MPDU length before decapsulation. Only valid when 265 first_msdu is set. This field is taken directly from the 266 length field of the A-MPDU delimiter or the preamble length 267 field for non-A-MPDU frames. 268 269 reserved_1a 270 271 <legal 0> 272 273 key_id_octet 274 275 The key ID octet from the IV. Only valid when 276 first_msdu is set. 277 278 cce_super_rule 279 280 Indicates the super filter rule 281 282 cce_classify_not_done_truncate 283 284 Classification failed due to truncated frame 285 286 cce_classify_not_done_cce_dis 287 288 Classification failed due to CCE global disable 289 290 ext_wapi_pn_63_48 291 292 Extension PN (packet number) which is only used by WAPI. 293 This corresponds to WAPI PN bits [63:48] (pn6 and pn7). 294 The WAPI PN bits [63:0] are in the pn field of the 295 rx_mpdu_start descriptor. 296 297 ext_wapi_pn_95_64 298 299 Extension PN (packet number) which is only used by WAPI. 300 This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 301 and pn11). 302 303 ext_wapi_pn_127_96 304 305 Extension PN (packet number) which is only used by WAPI. 306 This corresponds to WAPI PN bits [127:96] (pn12, pn13, 307 pn14, pn15). 308 309 da_offset 310 311 Offset into MSDU buffer for DA 312 313 sa_offset 314 315 Offset into MSDU buffer for SA 316 317 da_offset_valid 318 319 da_offset field is valid. This will be set to 0 in case 320 of a dynamic A-MSDU when DA is compressed 321 322 sa_offset_valid 323 324 sa_offset field is valid. This will be set to 0 in case 325 of a dynamic A-MSDU when SA is compressed 326 327 reserved_10a 328 329 <legal 0> 330 331 l3_type 332 333 The 16-bit type value indicating the type of L3 later 334 extracted from LLC/SNAP, set to zero if SNAP is not 335 available 336 337 ipv6_options_crc 338 339 32 bit CRC computed out of IP v6 extension headers 340 341 tcp_seq_number 342 343 TCP sequence number (as a number assembled from a TCP 344 packet in big-endian order, i.e. requiring a byte-swap for 345 little-endian FW/SW w.r.t. the byte order in a packet) 346 347 tcp_ack_number 348 349 TCP acknowledge number (as a number assembled from a TCP 350 packet in big-endian order, i.e. requiring a byte-swap for 351 little-endian FW/SW w.r.t. the byte order in a packet) 352 353 tcp_flag 354 355 TCP flags 356 357 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit 358 in bit 8 and the FIN bit in bit 0, i.e. in big-endian order, 359 i.e. requiring a byte-swap for little-endian FW/SW w.r.t. 360 the byte order in a packet) 361 362 lro_eligible 363 364 Computed out of TCP and IP fields to indicate that this 365 MSDU is eligible for LRO 366 367 reserved_9a 368 369 NOTE: DO not assign a field... Internally used in 370 RXOLE.. 371 372 <legal 0> 373 374 window_size 375 376 TCP receive window size (as a number assembled from a 377 TCP packet in big-endian order, i.e. requiring a byte-swap 378 for little-endian FW/SW w.r.t. the byte order in a packet) 379 380 tcp_udp_chksum 381 382 The value of the computed TCP/UDP checksum. A mode bit 383 selects whether this checksum is the full checksum or the 384 partial checksum which does not include the pseudo header. 385 (with the first byte in the MSB and the second byte in the 386 LSB, i.e. requiring a byte-swap for little-endian FW/SW 387 w.r.t. the byte order in a packet) 388 389 sa_idx_timeout 390 391 Indicates an unsuccessful MAC source address search due 392 to the expiring of the search timer. 393 394 da_idx_timeout 395 396 Indicates an unsuccessful MAC destination address search 397 due to the expiring of the search timer. 398 399 msdu_limit_error 400 401 Indicates that the MSDU threshold was exceeded and thus 402 all the rest of the MSDUs will not be scattered and will not 403 be decapsulated but will be DMA'ed in RAW format as a single 404 MSDU buffer 405 406 flow_idx_timeout 407 408 Indicates an unsuccessful flow search due to the 409 expiring of the search timer. 410 411 <legal all> 412 413 flow_idx_invalid 414 415 flow id is not valid 416 417 <legal all> 418 419 wifi_parser_error 420 421 Indicates that the WiFi frame has one of the following 422 errors 423 424 o has less than minimum allowed bytes as per standard 425 426 o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) 427 428 <legal all> 429 430 amsdu_parser_error 431 432 A-MSDU could not be properly de-agregated. 433 434 <legal all> 435 436 sa_is_valid 437 438 Indicates that OLE found a valid SA entry 439 440 da_is_valid 441 442 Indicates that OLE found a valid DA entry 443 444 da_is_mcbc 445 446 Field Only valid if da_is_valid is set 447 448 449 450 Indicates the DA address was a Multicast of Broadcast 451 address. 452 453 l3_header_padding 454 455 Number of bytes padded to make sure that the L3 header 456 will always start of a Dword boundary 457 458 first_msdu 459 460 Indicates the first MSDU of A-MSDU. If both first_msdu 461 and last_msdu are set in the MSDU then this is a 462 non-aggregated MSDU frame: normal MPDU. Interior MSDU in an 463 A-MSDU shall have both first_mpdu and last_mpdu bits set to 464 0. 465 466 last_msdu 467 468 Indicates the last MSDU of the A-MSDU. MPDU end status 469 is only valid when last_msdu is set. 470 471 reserved_5a 472 473 <legal 0> 474 475 sa_idx 476 477 The offset in the address table which matches the MAC 478 source address. 479 480 da_idx_or_sw_peer_id 481 482 Based on a register configuration in RXOLE, this field 483 will contain: 484 485 The offset in the address table which matches the MAC 486 destination address 487 488 OR: 489 490 sw_peer_id from the address search entry corresponding 491 to the destination address of the MSDU 492 493 msdu_drop 494 495 When set, REO shall drop this MSDU and not forward it to 496 any other ring... 497 498 <legal all> 499 500 reo_destination_indication 501 502 The ID of the REO exit ring where the MSDU frame shall 503 push after (MPDU level) reordering has finished. 504 505 506 507 <enum 0 reo_destination_tcl> Reo will push the frame 508 into the REO2TCL ring 509 510 <enum 1 reo_destination_sw1> Reo will push the frame 511 into the REO2SW1 ring 512 513 <enum 2 reo_destination_sw2> Reo will push the frame 514 into the REO2SW2 ring 515 516 <enum 3 reo_destination_sw3> Reo will push the frame 517 into the REO2SW3 ring 518 519 <enum 4 reo_destination_sw4> Reo will push the frame 520 into the REO2SW4 ring 521 522 <enum 5 reo_destination_release> Reo will push the frame 523 into the REO_release ring 524 525 <enum 6 reo_destination_fw> Reo will push the frame into 526 the REO2FW ring 527 528 <enum 7 reo_destination_sw5> Reo will push the frame 529 into the REO2SW5 ring 530 531 <enum 8 reo_destination_sw6> Reo will push the frame 532 into the REO2SW6 ring 533 534 <enum 9 reo_destination_9> REO remaps this <enum 10 535 reo_destination_10> REO remaps this 536 537 <enum 11 reo_destination_11> REO remaps this 538 539 <enum 12 reo_destination_12> REO remaps this <enum 13 540 reo_destination_13> REO remaps this 541 542 <enum 14 reo_destination_14> REO remaps this 543 544 <enum 15 reo_destination_15> REO remaps this 545 546 <enum 16 reo_destination_16> REO remaps this 547 548 <enum 17 reo_destination_17> REO remaps this 549 550 <enum 18 reo_destination_18> REO remaps this 551 552 <enum 19 reo_destination_19> REO remaps this 553 554 <enum 20 reo_destination_20> REO remaps this 555 556 <enum 21 reo_destination_21> REO remaps this 557 558 <enum 22 reo_destination_22> REO remaps this 559 560 <enum 23 reo_destination_23> REO remaps this 561 562 <enum 24 reo_destination_24> REO remaps this 563 564 <enum 25 reo_destination_25> REO remaps this 565 566 <enum 26 reo_destination_26> REO remaps this 567 568 <enum 27 reo_destination_27> REO remaps this 569 570 <enum 28 reo_destination_28> REO remaps this 571 572 <enum 29 reo_destination_29> REO remaps this 573 574 <enum 30 reo_destination_30> REO remaps this 575 576 <enum 31 reo_destination_31> REO remaps this 577 578 579 580 <legal all> 581 582 flow_idx 583 584 Flow table index 585 586 <legal all> 587 588 reserved_14 589 590 <legal 0> 591 592 fse_metadata 593 594 FSE related meta data: 595 596 <legal all> 597 598 cce_metadata 599 600 CCE related meta data: 601 602 <legal all> 603 604 sa_sw_peer_id 605 606 sw_peer_id from the address search entry corresponding 607 to the source address of the MSDU 608 609 <legal all> 610 611 rule_indication_31_0 612 613 Bitmap indicating which of rules 31-0 have matched 614 615 rule_indication_63_32 616 617 Bitmap indicating which of rules 63-32 have matched 618 619 aggregation_count 620 621 FISA: Number of MSDU's aggregated so far 622 623 624 625 Set to zero in chips not supporting FISA, e.g. Pine 626 627 <legal all> 628 629 flow_aggregation_continuation 630 631 FISA: To indicate that this MSDU can be aggregated with 632 the previous packet with the same flow id 633 634 635 636 Set to zero in chips not supporting FISA, e.g. Pine 637 638 <legal all> 639 640 fisa_timeout 641 642 FISA: To indicate that the aggregation has restarted for 643 this flow due to timeout 644 645 646 647 Set to zero in chips not supporting FISA, e.g. Pine 648 649 <legal all> 650 651 reserve_17a 652 653 <legal 0> 654 655 cumulative_l4_checksum 656 657 FISA: checksum for MSDU's that is part of this flow 658 aggregated so far 659 660 661 662 Set to zero in chips not supporting FISA, e.g. Pine 663 664 <legal all> 665 666 cumulative_ip_length 667 668 FISA: Total MSDU length that is part of this flow 669 aggregated so far 670 671 672 673 Set to zero in chips not supporting FISA, e.g. Pine 674 675 <legal all> 676 */ 677 678 679 /* Description RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY 680 681 Field indicates what the reason was that this MPDU frame 682 was allowed to come into the receive path by RXPCU 683 684 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 685 frame filter programming of rxpcu 686 687 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 688 regular frame filter and would have been dropped, were it 689 not for the frame fitting into the 'monitor_client' 690 category. 691 692 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 693 regular frame filter and also did not pass the 694 rxpcu_monitor_client filter. It would have been dropped 695 accept that it did pass the 'monitor_other' category. 696 697 <legal 0-2> 698 */ 699 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 700 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 701 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 702 703 /* Description RX_MSDU_END_0_SW_FRAME_GROUP_ID 704 705 SW processes frames based on certain classifications. 706 This field indicates to what sw classification this MPDU is 707 mapped. 708 709 The classification is given in priority order 710 711 712 713 <enum 0 sw_frame_group_NDP_frame> 714 715 716 717 <enum 1 sw_frame_group_Multicast_data> 718 719 <enum 2 sw_frame_group_Unicast_data> 720 721 <enum 3 sw_frame_group_Null_data > This includes mpdus 722 of type Data Null as well as QoS Data Null 723 724 725 726 <enum 4 sw_frame_group_mgmt_0000 > 727 728 <enum 5 sw_frame_group_mgmt_0001 > 729 730 <enum 6 sw_frame_group_mgmt_0010 > 731 732 <enum 7 sw_frame_group_mgmt_0011 > 733 734 <enum 8 sw_frame_group_mgmt_0100 > 735 736 <enum 9 sw_frame_group_mgmt_0101 > 737 738 <enum 10 sw_frame_group_mgmt_0110 > 739 740 <enum 11 sw_frame_group_mgmt_0111 > 741 742 <enum 12 sw_frame_group_mgmt_1000 > 743 744 <enum 13 sw_frame_group_mgmt_1001 > 745 746 <enum 14 sw_frame_group_mgmt_1010 > 747 748 <enum 15 sw_frame_group_mgmt_1011 > 749 750 <enum 16 sw_frame_group_mgmt_1100 > 751 752 <enum 17 sw_frame_group_mgmt_1101 > 753 754 <enum 18 sw_frame_group_mgmt_1110 > 755 756 <enum 19 sw_frame_group_mgmt_1111 > 757 758 759 760 <enum 20 sw_frame_group_ctrl_0000 > 761 762 <enum 21 sw_frame_group_ctrl_0001 > 763 764 <enum 22 sw_frame_group_ctrl_0010 > 765 766 <enum 23 sw_frame_group_ctrl_0011 > 767 768 <enum 24 sw_frame_group_ctrl_0100 > 769 770 <enum 25 sw_frame_group_ctrl_0101 > 771 772 <enum 26 sw_frame_group_ctrl_0110 > 773 774 <enum 27 sw_frame_group_ctrl_0111 > 775 776 <enum 28 sw_frame_group_ctrl_1000 > 777 778 <enum 29 sw_frame_group_ctrl_1001 > 779 780 <enum 30 sw_frame_group_ctrl_1010 > 781 782 <enum 31 sw_frame_group_ctrl_1011 > 783 784 <enum 32 sw_frame_group_ctrl_1100 > 785 786 <enum 33 sw_frame_group_ctrl_1101 > 787 788 <enum 34 sw_frame_group_ctrl_1110 > 789 790 <enum 35 sw_frame_group_ctrl_1111 > 791 792 793 794 <enum 36 sw_frame_group_unsupported> This covers type 3 795 and protocol version != 0 796 797 798 799 800 801 802 <legal 0-37> 803 */ 804 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 805 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_LSB 2 806 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc 807 808 /* Description RX_MSDU_END_0_RESERVED_0 809 810 <legal 0> 811 */ 812 #define RX_MSDU_END_0_RESERVED_0_OFFSET 0x00000000 813 #define RX_MSDU_END_0_RESERVED_0_LSB 9 814 #define RX_MSDU_END_0_RESERVED_0_MASK 0x0000fe00 815 816 /* Description RX_MSDU_END_0_PHY_PPDU_ID 817 818 A ppdu counter value that PHY increments for every PPDU 819 received. The counter value wraps around 820 821 <legal all> 822 */ 823 #define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 824 #define RX_MSDU_END_0_PHY_PPDU_ID_LSB 16 825 #define RX_MSDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 826 827 /* Description RX_MSDU_END_1_IP_HDR_CHKSUM 828 829 This can include the IP header checksum or the pseudo 830 header checksum used by TCP/UDP checksum. 831 832 (with the first byte in the MSB and the second byte in 833 the LSB, i.e. requiring a byte-swap for little-endian FW/SW 834 w.r.t. the byte order in a packet) 835 */ 836 #define RX_MSDU_END_1_IP_HDR_CHKSUM_OFFSET 0x00000004 837 #define RX_MSDU_END_1_IP_HDR_CHKSUM_LSB 0 838 #define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK 0x0000ffff 839 840 /* Description RX_MSDU_END_1_REPORTED_MPDU_LENGTH 841 842 MPDU length before decapsulation. Only valid when 843 first_msdu is set. This field is taken directly from the 844 length field of the A-MPDU delimiter or the preamble length 845 field for non-A-MPDU frames. 846 */ 847 #define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_OFFSET 0x00000004 848 #define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_LSB 16 849 #define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_MASK 0x3fff0000 850 851 /* Description RX_MSDU_END_1_RESERVED_1A 852 853 <legal 0> 854 */ 855 #define RX_MSDU_END_1_RESERVED_1A_OFFSET 0x00000004 856 #define RX_MSDU_END_1_RESERVED_1A_LSB 30 857 #define RX_MSDU_END_1_RESERVED_1A_MASK 0xc0000000 858 859 /* Description RX_MSDU_END_2_KEY_ID_OCTET 860 861 The key ID octet from the IV. Only valid when 862 first_msdu is set. 863 */ 864 #define RX_MSDU_END_2_KEY_ID_OCTET_OFFSET 0x00000008 865 #define RX_MSDU_END_2_KEY_ID_OCTET_LSB 0 866 #define RX_MSDU_END_2_KEY_ID_OCTET_MASK 0x000000ff 867 868 /* Description RX_MSDU_END_2_CCE_SUPER_RULE 869 870 Indicates the super filter rule 871 */ 872 #define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET 0x00000008 873 #define RX_MSDU_END_2_CCE_SUPER_RULE_LSB 8 874 #define RX_MSDU_END_2_CCE_SUPER_RULE_MASK 0x00003f00 875 876 /* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE 877 878 Classification failed due to truncated frame 879 */ 880 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008 881 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 882 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000 883 884 /* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS 885 886 Classification failed due to CCE global disable 887 */ 888 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008 889 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 890 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000 891 892 /* Description RX_MSDU_END_2_EXT_WAPI_PN_63_48 893 894 Extension PN (packet number) which is only used by WAPI. 895 This corresponds to WAPI PN bits [63:48] (pn6 and pn7). 896 The WAPI PN bits [63:0] are in the pn field of the 897 rx_mpdu_start descriptor. 898 */ 899 #define RX_MSDU_END_2_EXT_WAPI_PN_63_48_OFFSET 0x00000008 900 #define RX_MSDU_END_2_EXT_WAPI_PN_63_48_LSB 16 901 #define RX_MSDU_END_2_EXT_WAPI_PN_63_48_MASK 0xffff0000 902 903 /* Description RX_MSDU_END_3_EXT_WAPI_PN_95_64 904 905 Extension PN (packet number) which is only used by WAPI. 906 This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 907 and pn11). 908 */ 909 #define RX_MSDU_END_3_EXT_WAPI_PN_95_64_OFFSET 0x0000000c 910 #define RX_MSDU_END_3_EXT_WAPI_PN_95_64_LSB 0 911 #define RX_MSDU_END_3_EXT_WAPI_PN_95_64_MASK 0xffffffff 912 913 /* Description RX_MSDU_END_4_EXT_WAPI_PN_127_96 914 915 Extension PN (packet number) which is only used by WAPI. 916 This corresponds to WAPI PN bits [127:96] (pn12, pn13, 917 pn14, pn15). 918 */ 919 #define RX_MSDU_END_4_EXT_WAPI_PN_127_96_OFFSET 0x00000010 920 #define RX_MSDU_END_4_EXT_WAPI_PN_127_96_LSB 0 921 #define RX_MSDU_END_4_EXT_WAPI_PN_127_96_MASK 0xffffffff 922 923 /* Description RX_MSDU_END_5_DA_OFFSET 924 925 Offset into MSDU buffer for DA 926 */ 927 #define RX_MSDU_END_5_DA_OFFSET_OFFSET 0x00000014 928 #define RX_MSDU_END_5_DA_OFFSET_LSB 0 929 #define RX_MSDU_END_5_DA_OFFSET_MASK 0x0000003f 930 931 /* Description RX_MSDU_END_5_SA_OFFSET 932 933 Offset into MSDU buffer for SA 934 */ 935 #define RX_MSDU_END_5_SA_OFFSET_OFFSET 0x00000014 936 #define RX_MSDU_END_5_SA_OFFSET_LSB 6 937 #define RX_MSDU_END_5_SA_OFFSET_MASK 0x00000fc0 938 939 /* Description RX_MSDU_END_5_DA_OFFSET_VALID 940 941 da_offset field is valid. This will be set to 0 in case 942 of a dynamic A-MSDU when DA is compressed 943 */ 944 #define RX_MSDU_END_5_DA_OFFSET_VALID_OFFSET 0x00000014 945 #define RX_MSDU_END_5_DA_OFFSET_VALID_LSB 12 946 #define RX_MSDU_END_5_DA_OFFSET_VALID_MASK 0x00001000 947 948 /* Description RX_MSDU_END_5_SA_OFFSET_VALID 949 950 sa_offset field is valid. This will be set to 0 in case 951 of a dynamic A-MSDU when SA is compressed 952 */ 953 #define RX_MSDU_END_5_SA_OFFSET_VALID_OFFSET 0x00000014 954 #define RX_MSDU_END_5_SA_OFFSET_VALID_LSB 13 955 #define RX_MSDU_END_5_SA_OFFSET_VALID_MASK 0x00002000 956 957 /* Description RX_MSDU_END_5_RESERVED_10A 958 959 <legal 0> 960 */ 961 #define RX_MSDU_END_5_RESERVED_10A_OFFSET 0x00000014 962 #define RX_MSDU_END_5_RESERVED_10A_LSB 14 963 #define RX_MSDU_END_5_RESERVED_10A_MASK 0x0000c000 964 965 /* Description RX_MSDU_END_5_L3_TYPE 966 967 The 16-bit type value indicating the type of L3 later 968 extracted from LLC/SNAP, set to zero if SNAP is not 969 available 970 */ 971 #define RX_MSDU_END_5_L3_TYPE_OFFSET 0x00000014 972 #define RX_MSDU_END_5_L3_TYPE_LSB 16 973 #define RX_MSDU_END_5_L3_TYPE_MASK 0xffff0000 974 975 /* Description RX_MSDU_END_6_IPV6_OPTIONS_CRC 976 977 32 bit CRC computed out of IP v6 extension headers 978 */ 979 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET 0x00000018 980 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_LSB 0 981 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK 0xffffffff 982 983 /* Description RX_MSDU_END_7_TCP_SEQ_NUMBER 984 985 TCP sequence number (as a number assembled from a TCP 986 packet in big-endian order, i.e. requiring a byte-swap for 987 little-endian FW/SW w.r.t. the byte order in a packet) 988 */ 989 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET 0x0000001c 990 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB 0 991 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK 0xffffffff 992 993 /* Description RX_MSDU_END_8_TCP_ACK_NUMBER 994 995 TCP acknowledge number (as a number assembled from a TCP 996 packet in big-endian order, i.e. requiring a byte-swap for 997 little-endian FW/SW w.r.t. the byte order in a packet) 998 */ 999 #define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET 0x00000020 1000 #define RX_MSDU_END_8_TCP_ACK_NUMBER_LSB 0 1001 #define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK 0xffffffff 1002 1003 /* Description RX_MSDU_END_9_TCP_FLAG 1004 1005 TCP flags 1006 1007 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit 1008 in bit 8 and the FIN bit in bit 0, i.e. in big-endian order, 1009 i.e. requiring a byte-swap for little-endian FW/SW w.r.t. 1010 the byte order in a packet) 1011 */ 1012 #define RX_MSDU_END_9_TCP_FLAG_OFFSET 0x00000024 1013 #define RX_MSDU_END_9_TCP_FLAG_LSB 0 1014 #define RX_MSDU_END_9_TCP_FLAG_MASK 0x000001ff 1015 1016 /* Description RX_MSDU_END_9_LRO_ELIGIBLE 1017 1018 Computed out of TCP and IP fields to indicate that this 1019 MSDU is eligible for LRO 1020 */ 1021 #define RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET 0x00000024 1022 #define RX_MSDU_END_9_LRO_ELIGIBLE_LSB 9 1023 #define RX_MSDU_END_9_LRO_ELIGIBLE_MASK 0x00000200 1024 1025 /* Description RX_MSDU_END_9_RESERVED_9A 1026 1027 NOTE: DO not assign a field... Internally used in 1028 RXOLE.. 1029 1030 <legal 0> 1031 */ 1032 #define RX_MSDU_END_9_RESERVED_9A_OFFSET 0x00000024 1033 #define RX_MSDU_END_9_RESERVED_9A_LSB 10 1034 #define RX_MSDU_END_9_RESERVED_9A_MASK 0x0000fc00 1035 1036 /* Description RX_MSDU_END_9_WINDOW_SIZE 1037 1038 TCP receive window size (as a number assembled from a 1039 TCP packet in big-endian order, i.e. requiring a byte-swap 1040 for little-endian FW/SW w.r.t. the byte order in a packet) 1041 */ 1042 #define RX_MSDU_END_9_WINDOW_SIZE_OFFSET 0x00000024 1043 #define RX_MSDU_END_9_WINDOW_SIZE_LSB 16 1044 #define RX_MSDU_END_9_WINDOW_SIZE_MASK 0xffff0000 1045 1046 /* Description RX_MSDU_END_10_TCP_UDP_CHKSUM 1047 1048 The value of the computed TCP/UDP checksum. A mode bit 1049 selects whether this checksum is the full checksum or the 1050 partial checksum which does not include the pseudo header. 1051 (with the first byte in the MSB and the second byte in the 1052 LSB, i.e. requiring a byte-swap for little-endian FW/SW 1053 w.r.t. the byte order in a packet) 1054 */ 1055 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET 0x00000028 1056 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB 0 1057 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK 0x0000ffff 1058 1059 /* Description RX_MSDU_END_10_SA_IDX_TIMEOUT 1060 1061 Indicates an unsuccessful MAC source address search due 1062 to the expiring of the search timer. 1063 */ 1064 #define RX_MSDU_END_10_SA_IDX_TIMEOUT_OFFSET 0x00000028 1065 #define RX_MSDU_END_10_SA_IDX_TIMEOUT_LSB 16 1066 #define RX_MSDU_END_10_SA_IDX_TIMEOUT_MASK 0x00010000 1067 1068 /* Description RX_MSDU_END_10_DA_IDX_TIMEOUT 1069 1070 Indicates an unsuccessful MAC destination address search 1071 due to the expiring of the search timer. 1072 */ 1073 #define RX_MSDU_END_10_DA_IDX_TIMEOUT_OFFSET 0x00000028 1074 #define RX_MSDU_END_10_DA_IDX_TIMEOUT_LSB 17 1075 #define RX_MSDU_END_10_DA_IDX_TIMEOUT_MASK 0x00020000 1076 1077 /* Description RX_MSDU_END_10_MSDU_LIMIT_ERROR 1078 1079 Indicates that the MSDU threshold was exceeded and thus 1080 all the rest of the MSDUs will not be scattered and will not 1081 be decapsulated but will be DMA'ed in RAW format as a single 1082 MSDU buffer 1083 */ 1084 #define RX_MSDU_END_10_MSDU_LIMIT_ERROR_OFFSET 0x00000028 1085 #define RX_MSDU_END_10_MSDU_LIMIT_ERROR_LSB 18 1086 #define RX_MSDU_END_10_MSDU_LIMIT_ERROR_MASK 0x00040000 1087 1088 /* Description RX_MSDU_END_10_FLOW_IDX_TIMEOUT 1089 1090 Indicates an unsuccessful flow search due to the 1091 expiring of the search timer. 1092 1093 <legal all> 1094 */ 1095 #define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET 0x00000028 1096 #define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB 19 1097 #define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK 0x00080000 1098 1099 /* Description RX_MSDU_END_10_FLOW_IDX_INVALID 1100 1101 flow id is not valid 1102 1103 <legal all> 1104 */ 1105 #define RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET 0x00000028 1106 #define RX_MSDU_END_10_FLOW_IDX_INVALID_LSB 20 1107 #define RX_MSDU_END_10_FLOW_IDX_INVALID_MASK 0x00100000 1108 1109 /* Description RX_MSDU_END_10_WIFI_PARSER_ERROR 1110 1111 Indicates that the WiFi frame has one of the following 1112 errors 1113 1114 o has less than minimum allowed bytes as per standard 1115 1116 o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) 1117 1118 <legal all> 1119 */ 1120 #define RX_MSDU_END_10_WIFI_PARSER_ERROR_OFFSET 0x00000028 1121 #define RX_MSDU_END_10_WIFI_PARSER_ERROR_LSB 21 1122 #define RX_MSDU_END_10_WIFI_PARSER_ERROR_MASK 0x00200000 1123 1124 /* Description RX_MSDU_END_10_AMSDU_PARSER_ERROR 1125 1126 A-MSDU could not be properly de-agregated. 1127 1128 <legal all> 1129 */ 1130 #define RX_MSDU_END_10_AMSDU_PARSER_ERROR_OFFSET 0x00000028 1131 #define RX_MSDU_END_10_AMSDU_PARSER_ERROR_LSB 22 1132 #define RX_MSDU_END_10_AMSDU_PARSER_ERROR_MASK 0x00400000 1133 1134 /* Description RX_MSDU_END_10_SA_IS_VALID 1135 1136 Indicates that OLE found a valid SA entry 1137 */ 1138 #define RX_MSDU_END_10_SA_IS_VALID_OFFSET 0x00000028 1139 #define RX_MSDU_END_10_SA_IS_VALID_LSB 23 1140 #define RX_MSDU_END_10_SA_IS_VALID_MASK 0x00800000 1141 1142 /* Description RX_MSDU_END_10_DA_IS_VALID 1143 1144 Indicates that OLE found a valid DA entry 1145 */ 1146 #define RX_MSDU_END_10_DA_IS_VALID_OFFSET 0x00000028 1147 #define RX_MSDU_END_10_DA_IS_VALID_LSB 24 1148 #define RX_MSDU_END_10_DA_IS_VALID_MASK 0x01000000 1149 1150 /* Description RX_MSDU_END_10_DA_IS_MCBC 1151 1152 Field Only valid if da_is_valid is set 1153 1154 1155 1156 Indicates the DA address was a Multicast of Broadcast 1157 address. 1158 */ 1159 #define RX_MSDU_END_10_DA_IS_MCBC_OFFSET 0x00000028 1160 #define RX_MSDU_END_10_DA_IS_MCBC_LSB 25 1161 #define RX_MSDU_END_10_DA_IS_MCBC_MASK 0x02000000 1162 1163 /* Description RX_MSDU_END_10_L3_HEADER_PADDING 1164 1165 Number of bytes padded to make sure that the L3 header 1166 will always start of a Dword boundary 1167 */ 1168 #define RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET 0x00000028 1169 #define RX_MSDU_END_10_L3_HEADER_PADDING_LSB 26 1170 #define RX_MSDU_END_10_L3_HEADER_PADDING_MASK 0x0c000000 1171 1172 /* Description RX_MSDU_END_10_FIRST_MSDU 1173 1174 Indicates the first MSDU of A-MSDU. If both first_msdu 1175 and last_msdu are set in the MSDU then this is a 1176 non-aggregated MSDU frame: normal MPDU. Interior MSDU in an 1177 A-MSDU shall have both first_mpdu and last_mpdu bits set to 1178 0. 1179 */ 1180 #define RX_MSDU_END_10_FIRST_MSDU_OFFSET 0x00000028 1181 #define RX_MSDU_END_10_FIRST_MSDU_LSB 28 1182 #define RX_MSDU_END_10_FIRST_MSDU_MASK 0x10000000 1183 1184 /* Description RX_MSDU_END_10_LAST_MSDU 1185 1186 Indicates the last MSDU of the A-MSDU. MPDU end status 1187 is only valid when last_msdu is set. 1188 */ 1189 #define RX_MSDU_END_10_LAST_MSDU_OFFSET 0x00000028 1190 #define RX_MSDU_END_10_LAST_MSDU_LSB 29 1191 #define RX_MSDU_END_10_LAST_MSDU_MASK 0x20000000 1192 1193 /* Description RX_MSDU_END_10_RESERVED_5A 1194 1195 <legal 0> 1196 */ 1197 #define RX_MSDU_END_10_RESERVED_5A_OFFSET 0x00000028 1198 #define RX_MSDU_END_10_RESERVED_5A_LSB 30 1199 #define RX_MSDU_END_10_RESERVED_5A_MASK 0xc0000000 1200 1201 /* Description RX_MSDU_END_11_SA_IDX 1202 1203 The offset in the address table which matches the MAC 1204 source address. 1205 */ 1206 #define RX_MSDU_END_11_SA_IDX_OFFSET 0x0000002c 1207 #define RX_MSDU_END_11_SA_IDX_LSB 0 1208 #define RX_MSDU_END_11_SA_IDX_MASK 0x0000ffff 1209 1210 /* Description RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID 1211 1212 Based on a register configuration in RXOLE, this field 1213 will contain: 1214 1215 The offset in the address table which matches the MAC 1216 destination address 1217 1218 OR: 1219 1220 sw_peer_id from the address search entry corresponding 1221 to the destination address of the MSDU 1222 */ 1223 #define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000002c 1224 #define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB 16 1225 #define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK 0xffff0000 1226 1227 /* Description RX_MSDU_END_12_MSDU_DROP 1228 1229 When set, REO shall drop this MSDU and not forward it to 1230 any other ring... 1231 1232 <legal all> 1233 */ 1234 #define RX_MSDU_END_12_MSDU_DROP_OFFSET 0x00000030 1235 #define RX_MSDU_END_12_MSDU_DROP_LSB 0 1236 #define RX_MSDU_END_12_MSDU_DROP_MASK 0x00000001 1237 1238 /* Description RX_MSDU_END_12_REO_DESTINATION_INDICATION 1239 1240 The ID of the REO exit ring where the MSDU frame shall 1241 push after (MPDU level) reordering has finished. 1242 1243 1244 1245 <enum 0 reo_destination_tcl> Reo will push the frame 1246 into the REO2TCL ring 1247 1248 <enum 1 reo_destination_sw1> Reo will push the frame 1249 into the REO2SW1 ring 1250 1251 <enum 2 reo_destination_sw2> Reo will push the frame 1252 into the REO2SW2 ring 1253 1254 <enum 3 reo_destination_sw3> Reo will push the frame 1255 into the REO2SW3 ring 1256 1257 <enum 4 reo_destination_sw4> Reo will push the frame 1258 into the REO2SW4 ring 1259 1260 <enum 5 reo_destination_release> Reo will push the frame 1261 into the REO_release ring 1262 1263 <enum 6 reo_destination_fw> Reo will push the frame into 1264 the REO2FW ring 1265 1266 <enum 7 reo_destination_sw5> Reo will push the frame 1267 into the REO2SW5 ring 1268 1269 <enum 8 reo_destination_sw6> Reo will push the frame 1270 into the REO2SW6 ring 1271 1272 <enum 9 reo_destination_9> REO remaps this <enum 10 1273 reo_destination_10> REO remaps this 1274 1275 <enum 11 reo_destination_11> REO remaps this 1276 1277 <enum 12 reo_destination_12> REO remaps this <enum 13 1278 reo_destination_13> REO remaps this 1279 1280 <enum 14 reo_destination_14> REO remaps this 1281 1282 <enum 15 reo_destination_15> REO remaps this 1283 1284 <enum 16 reo_destination_16> REO remaps this 1285 1286 <enum 17 reo_destination_17> REO remaps this 1287 1288 <enum 18 reo_destination_18> REO remaps this 1289 1290 <enum 19 reo_destination_19> REO remaps this 1291 1292 <enum 20 reo_destination_20> REO remaps this 1293 1294 <enum 21 reo_destination_21> REO remaps this 1295 1296 <enum 22 reo_destination_22> REO remaps this 1297 1298 <enum 23 reo_destination_23> REO remaps this 1299 1300 <enum 24 reo_destination_24> REO remaps this 1301 1302 <enum 25 reo_destination_25> REO remaps this 1303 1304 <enum 26 reo_destination_26> REO remaps this 1305 1306 <enum 27 reo_destination_27> REO remaps this 1307 1308 <enum 28 reo_destination_28> REO remaps this 1309 1310 <enum 29 reo_destination_29> REO remaps this 1311 1312 <enum 30 reo_destination_30> REO remaps this 1313 1314 <enum 31 reo_destination_31> REO remaps this 1315 1316 1317 1318 <legal all> 1319 */ 1320 #define RX_MSDU_END_12_REO_DESTINATION_INDICATION_OFFSET 0x00000030 1321 #define RX_MSDU_END_12_REO_DESTINATION_INDICATION_LSB 1 1322 #define RX_MSDU_END_12_REO_DESTINATION_INDICATION_MASK 0x0000003e 1323 1324 /* Description RX_MSDU_END_12_FLOW_IDX 1325 1326 Flow table index 1327 1328 <legal all> 1329 */ 1330 #define RX_MSDU_END_12_FLOW_IDX_OFFSET 0x00000030 1331 #define RX_MSDU_END_12_FLOW_IDX_LSB 6 1332 #define RX_MSDU_END_12_FLOW_IDX_MASK 0x03ffffc0 1333 1334 /* Description RX_MSDU_END_12_RESERVED_14 1335 1336 <legal 0> 1337 */ 1338 #define RX_MSDU_END_12_RESERVED_14_OFFSET 0x00000030 1339 #define RX_MSDU_END_12_RESERVED_14_LSB 26 1340 #define RX_MSDU_END_12_RESERVED_14_MASK 0xfc000000 1341 1342 /* Description RX_MSDU_END_13_FSE_METADATA 1343 1344 FSE related meta data: 1345 1346 <legal all> 1347 */ 1348 #define RX_MSDU_END_13_FSE_METADATA_OFFSET 0x00000034 1349 #define RX_MSDU_END_13_FSE_METADATA_LSB 0 1350 #define RX_MSDU_END_13_FSE_METADATA_MASK 0xffffffff 1351 1352 /* Description RX_MSDU_END_14_CCE_METADATA 1353 1354 CCE related meta data: 1355 1356 <legal all> 1357 */ 1358 #define RX_MSDU_END_14_CCE_METADATA_OFFSET 0x00000038 1359 #define RX_MSDU_END_14_CCE_METADATA_LSB 0 1360 #define RX_MSDU_END_14_CCE_METADATA_MASK 0x0000ffff 1361 1362 /* Description RX_MSDU_END_14_SA_SW_PEER_ID 1363 1364 sw_peer_id from the address search entry corresponding 1365 to the source address of the MSDU 1366 1367 <legal all> 1368 */ 1369 #define RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET 0x00000038 1370 #define RX_MSDU_END_14_SA_SW_PEER_ID_LSB 16 1371 #define RX_MSDU_END_14_SA_SW_PEER_ID_MASK 0xffff0000 1372 1373 /* Description RX_MSDU_END_15_RULE_INDICATION_31_0 1374 1375 Bitmap indicating which of rules 31-0 have matched 1376 */ 1377 #define RX_MSDU_END_15_RULE_INDICATION_31_0_OFFSET 0x0000003c 1378 #define RX_MSDU_END_15_RULE_INDICATION_31_0_LSB 0 1379 #define RX_MSDU_END_15_RULE_INDICATION_31_0_MASK 0xffffffff 1380 1381 /* Description RX_MSDU_END_16_RULE_INDICATION_63_32 1382 1383 Bitmap indicating which of rules 63-32 have matched 1384 */ 1385 #define RX_MSDU_END_16_RULE_INDICATION_63_32_OFFSET 0x00000040 1386 #define RX_MSDU_END_16_RULE_INDICATION_63_32_LSB 0 1387 #define RX_MSDU_END_16_RULE_INDICATION_63_32_MASK 0xffffffff 1388 1389 /* Description RX_MSDU_END_17_AGGREGATION_COUNT 1390 1391 FISA: Number of MSDU's aggregated so far 1392 1393 1394 1395 Set to zero in chips not supporting FISA, e.g. Pine 1396 1397 <legal all> 1398 */ 1399 #define RX_MSDU_END_17_AGGREGATION_COUNT_OFFSET 0x00000044 1400 #define RX_MSDU_END_17_AGGREGATION_COUNT_LSB 0 1401 #define RX_MSDU_END_17_AGGREGATION_COUNT_MASK 0x000000ff 1402 1403 /* Description RX_MSDU_END_17_FLOW_AGGREGATION_CONTINUATION 1404 1405 FISA: To indicate that this MSDU can be aggregated with 1406 the previous packet with the same flow id 1407 1408 1409 1410 Set to zero in chips not supporting FISA, e.g. Pine 1411 1412 <legal all> 1413 */ 1414 #define RX_MSDU_END_17_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x00000044 1415 #define RX_MSDU_END_17_FLOW_AGGREGATION_CONTINUATION_LSB 8 1416 #define RX_MSDU_END_17_FLOW_AGGREGATION_CONTINUATION_MASK 0x00000100 1417 1418 /* Description RX_MSDU_END_17_FISA_TIMEOUT 1419 1420 FISA: To indicate that the aggregation has restarted for 1421 this flow due to timeout 1422 1423 1424 1425 Set to zero in chips not supporting FISA, e.g. Pine 1426 1427 <legal all> 1428 */ 1429 #define RX_MSDU_END_17_FISA_TIMEOUT_OFFSET 0x00000044 1430 #define RX_MSDU_END_17_FISA_TIMEOUT_LSB 9 1431 #define RX_MSDU_END_17_FISA_TIMEOUT_MASK 0x00000200 1432 1433 /* Description RX_MSDU_END_17_RESERVE_17A 1434 1435 <legal 0> 1436 */ 1437 #define RX_MSDU_END_17_RESERVE_17A_OFFSET 0x00000044 1438 #define RX_MSDU_END_17_RESERVE_17A_LSB 10 1439 #define RX_MSDU_END_17_RESERVE_17A_MASK 0xfffffc00 1440 1441 /* Description RX_MSDU_END_18_CUMULATIVE_L4_CHECKSUM 1442 1443 FISA: checksum for MSDU's that is part of this flow 1444 aggregated so far 1445 1446 1447 1448 Set to zero in chips not supporting FISA, e.g. Pine 1449 1450 <legal all> 1451 */ 1452 #define RX_MSDU_END_18_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000048 1453 #define RX_MSDU_END_18_CUMULATIVE_L4_CHECKSUM_LSB 0 1454 #define RX_MSDU_END_18_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff 1455 1456 /* Description RX_MSDU_END_18_CUMULATIVE_IP_LENGTH 1457 1458 FISA: Total MSDU length that is part of this flow 1459 aggregated so far 1460 1461 1462 1463 Set to zero in chips not supporting FISA, e.g. Pine 1464 1465 <legal all> 1466 */ 1467 #define RX_MSDU_END_18_CUMULATIVE_IP_LENGTH_OFFSET 0x00000048 1468 #define RX_MSDU_END_18_CUMULATIVE_IP_LENGTH_LSB 16 1469 #define RX_MSDU_END_18_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 1470 1471 1472 #endif // _RX_MSDU_END_H_ 1473