1 2 /* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 23 24 25 26 27 28 29 30 #ifndef _RX_PPDU_END_USER_STATS_H_ 31 #define _RX_PPDU_END_USER_STATS_H_ 32 #if !defined(__ASSEMBLER__) 33 #endif 34 35 #include "rx_rxpcu_classification_overview.h" 36 #define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 24 37 38 #define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS 12 39 40 41 struct rx_ppdu_end_user_stats { 42 struct rx_rxpcu_classification_overview rxpcu_classification_details; 43 uint32_t sta_full_aid : 13, 44 mcs : 4, 45 nss : 3, 46 reserved_1a : 12; 47 uint32_t reserved_2a : 16, 48 mpdu_cnt_fcs_err : 11, 49 sw2rxdma0_buf_source_used : 1, 50 fw2rxdma_pmac0_buf_source_used : 1, 51 sw2rxdma1_buf_source_used : 1, 52 sw2rxdma_exception_buf_source_used : 1, 53 fw2rxdma_pmac1_buf_source_used : 1; 54 uint32_t mpdu_cnt_fcs_ok : 11, 55 frame_control_info_valid : 1, 56 qos_control_info_valid : 1, 57 ht_control_info_valid : 1, 58 data_sequence_control_info_valid : 1, 59 ht_control_info_null_valid : 1, 60 rxdma2fw_pmac1_ring_used : 1, 61 rxdma2reo_ring_used : 1, 62 rxdma2fw_pmac0_ring_used : 1, 63 rxdma2sw_ring_used : 1, 64 rxdma_release_ring_used : 1, 65 ht_control_field_pkt_type : 4, 66 reserved_3b : 7; 67 uint32_t ast_index : 16, 68 frame_control_field : 16; 69 uint32_t first_data_seq_ctrl : 16, 70 qos_control_field : 16; 71 uint32_t ht_control_field : 32; 72 uint32_t fcs_ok_bitmap_31_0 : 32; 73 uint32_t fcs_ok_bitmap_63_32 : 32; 74 uint32_t udp_msdu_count : 16, 75 tcp_msdu_count : 16; 76 uint32_t other_msdu_count : 16, 77 tcp_ack_msdu_count : 16; 78 uint32_t sw_response_reference_ptr : 32; 79 uint32_t received_qos_data_tid_bitmap : 16, 80 received_qos_data_tid_eosp_bitmap : 16; 81 uint32_t qosctrl_15_8_tid0 : 8, 82 qosctrl_15_8_tid1 : 8, 83 qosctrl_15_8_tid2 : 8, 84 qosctrl_15_8_tid3 : 8; 85 uint32_t qosctrl_15_8_tid4 : 8, 86 qosctrl_15_8_tid5 : 8, 87 qosctrl_15_8_tid6 : 8, 88 qosctrl_15_8_tid7 : 8; 89 uint32_t qosctrl_15_8_tid8 : 8, 90 qosctrl_15_8_tid9 : 8, 91 qosctrl_15_8_tid10 : 8, 92 qosctrl_15_8_tid11 : 8; 93 uint32_t qosctrl_15_8_tid12 : 8, 94 qosctrl_15_8_tid13 : 8, 95 qosctrl_15_8_tid14 : 8, 96 qosctrl_15_8_tid15 : 8; 97 uint32_t mpdu_ok_byte_count : 25, 98 ampdu_delim_ok_count_6_0 : 7; 99 uint32_t ampdu_delim_err_count : 25, 100 ampdu_delim_ok_count_13_7 : 7; 101 uint32_t mpdu_err_byte_count : 25, 102 ampdu_delim_ok_count_20_14 : 7; 103 uint32_t non_consecutive_delimiter_err : 16, 104 reserved_20a : 16; 105 uint32_t ht_control_null_field : 32; 106 uint32_t sw_response_reference_ptr_ext : 32; 107 uint32_t corrupted_due_to_fifo_delay : 1, 108 reserved_23a : 31; 109 }; 110 111 112 113 114 115 116 117 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 118 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 119 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 120 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 121 122 123 124 125 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 126 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 127 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 128 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 129 130 131 132 133 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 134 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 135 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 136 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 137 138 139 140 141 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 142 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 143 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 144 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 145 146 147 148 149 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 150 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 151 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 152 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 153 154 155 156 157 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 158 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 159 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 160 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 161 162 163 164 165 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 166 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 167 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 168 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 169 170 171 172 173 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 174 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 7 175 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 176 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000ff80 177 178 179 180 181 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 182 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 183 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 184 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 185 186 187 188 189 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x0000000000000000 190 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 32 191 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 44 192 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff00000000 193 194 195 196 197 #define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x0000000000000000 198 #define RX_PPDU_END_USER_STATS_MCS_LSB 45 199 #define RX_PPDU_END_USER_STATS_MCS_MSB 48 200 #define RX_PPDU_END_USER_STATS_MCS_MASK 0x0001e00000000000 201 202 203 204 205 #define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x0000000000000000 206 #define RX_PPDU_END_USER_STATS_NSS_LSB 49 207 #define RX_PPDU_END_USER_STATS_NSS_MSB 51 208 #define RX_PPDU_END_USER_STATS_NSS_MASK 0x000e000000000000 209 210 211 212 213 #define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x0000000000000000 214 #define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 52 215 #define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 63 216 #define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xfff0000000000000 217 218 219 220 221 #define RX_PPDU_END_USER_STATS_RESERVED_2A_OFFSET 0x0000000000000008 222 #define RX_PPDU_END_USER_STATS_RESERVED_2A_LSB 0 223 #define RX_PPDU_END_USER_STATS_RESERVED_2A_MSB 15 224 #define RX_PPDU_END_USER_STATS_RESERVED_2A_MASK 0x000000000000ffff 225 226 227 228 229 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x0000000000000008 230 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16 231 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26 232 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x0000000007ff0000 233 234 235 236 237 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 238 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27 239 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27 240 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000008000000 241 242 243 244 245 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 246 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_LSB 28 247 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MSB 28 248 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MASK 0x0000000010000000 249 250 251 252 253 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 254 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29 255 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29 256 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000020000000 257 258 259 260 261 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_OFFSET 0x0000000000000008 262 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_LSB 30 263 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MSB 30 264 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MASK 0x0000000040000000 265 266 267 268 269 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 270 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_LSB 31 271 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MSB 31 272 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MASK 0x0000000080000000 273 274 275 276 277 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000000000008 278 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 32 279 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 42 280 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff00000000 281 282 283 284 285 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 286 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 43 287 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 43 288 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x0000080000000000 289 290 291 292 293 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 294 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 44 295 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 44 296 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x0000100000000000 297 298 299 300 301 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 302 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 45 303 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 45 304 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x0000200000000000 305 306 307 308 309 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 310 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 46 311 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 46 312 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x0000400000000000 313 314 315 316 317 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000008 318 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 47 319 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 47 320 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x0000800000000000 321 322 323 324 325 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_OFFSET 0x0000000000000008 326 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_LSB 48 327 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MSB 48 328 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MASK 0x0001000000000000 329 330 331 332 333 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_OFFSET 0x0000000000000008 334 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_LSB 49 335 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MSB 49 336 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MASK 0x0002000000000000 337 338 339 340 341 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_OFFSET 0x0000000000000008 342 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_LSB 50 343 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MSB 50 344 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MASK 0x0004000000000000 345 346 347 348 349 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_OFFSET 0x0000000000000008 350 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_LSB 51 351 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MSB 51 352 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MASK 0x0008000000000000 353 354 355 356 357 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000000000008 358 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_LSB 52 359 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MSB 52 360 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MASK 0x0010000000000000 361 362 363 364 365 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000000000008 366 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 53 367 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 56 368 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e0000000000000 369 370 371 372 373 #define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000000000008 374 #define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 57 375 #define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 63 376 #define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xfe00000000000000 377 378 379 380 381 #define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x0000000000000010 382 #define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0 383 #define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15 384 #define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x000000000000ffff 385 386 387 388 389 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000010 390 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16 391 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31 392 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0x00000000ffff0000 393 394 395 396 397 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x0000000000000010 398 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 32 399 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 47 400 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff00000000 401 402 403 404 405 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x0000000000000010 406 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 48 407 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 63 408 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff000000000000 409 410 411 412 413 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x0000000000000018 414 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0 415 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31 416 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0x00000000ffffffff 417 418 419 420 421 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000000000000018 422 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 32 423 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 63 424 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff00000000 425 426 427 428 429 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x0000000000000020 430 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0 431 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31 432 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0x00000000ffffffff 433 434 435 436 437 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x0000000000000020 438 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 32 439 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 47 440 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff00000000 441 442 443 444 445 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x0000000000000020 446 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 48 447 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 63 448 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff000000000000 449 450 451 452 453 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x0000000000000028 454 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0 455 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15 456 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x000000000000ffff 457 458 459 460 461 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x0000000000000028 462 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16 463 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31 464 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0x00000000ffff0000 465 466 467 468 469 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000000000000028 470 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 32 471 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 63 472 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff00000000 473 474 475 476 477 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x0000000000000030 478 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 479 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15 480 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x000000000000ffff 481 482 483 484 485 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x0000000000000030 486 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 487 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31 488 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0x00000000ffff0000 489 490 491 492 493 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x0000000000000030 494 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 32 495 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 39 496 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff00000000 497 498 499 500 501 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x0000000000000030 502 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 40 503 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 47 504 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff0000000000 505 506 507 508 509 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x0000000000000030 510 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 48 511 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 55 512 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff000000000000 513 514 515 516 517 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x0000000000000030 518 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 56 519 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 63 520 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff00000000000000 521 522 523 524 525 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x0000000000000038 526 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0 527 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7 528 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x00000000000000ff 529 530 531 532 533 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x0000000000000038 534 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8 535 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15 536 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x000000000000ff00 537 538 539 540 541 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x0000000000000038 542 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16 543 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23 544 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x0000000000ff0000 545 546 547 548 549 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x0000000000000038 550 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24 551 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31 552 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0x00000000ff000000 553 554 555 556 557 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000000000000038 558 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 32 559 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 39 560 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff00000000 561 562 563 564 565 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000000000000038 566 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 40 567 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 47 568 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff0000000000 569 570 571 572 573 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000000000000038 574 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 48 575 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 55 576 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff000000000000 577 578 579 580 581 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000000000000038 582 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 56 583 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 63 584 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff00000000000000 585 586 587 588 589 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x0000000000000040 590 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0 591 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7 592 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x00000000000000ff 593 594 595 596 597 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x0000000000000040 598 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8 599 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15 600 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x000000000000ff00 601 602 603 604 605 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x0000000000000040 606 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16 607 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23 608 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x0000000000ff0000 609 610 611 612 613 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x0000000000000040 614 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24 615 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31 616 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0x00000000ff000000 617 618 619 620 621 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x0000000000000040 622 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 32 623 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 56 624 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff00000000 625 626 627 628 629 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x0000000000000040 630 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 57 631 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 63 632 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe00000000000000 633 634 635 636 637 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x0000000000000048 638 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0 639 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24 640 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x0000000001ffffff 641 642 643 644 645 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x0000000000000048 646 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 647 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31 648 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0x00000000fe000000 649 650 651 652 653 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000000000000048 654 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 32 655 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 56 656 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff00000000 657 658 659 660 661 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000000000000048 662 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 57 663 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 63 664 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe00000000000000 665 666 667 668 669 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x0000000000000050 670 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 671 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15 672 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x000000000000ffff 673 674 675 676 677 #define RX_PPDU_END_USER_STATS_RESERVED_20A_OFFSET 0x0000000000000050 678 #define RX_PPDU_END_USER_STATS_RESERVED_20A_LSB 16 679 #define RX_PPDU_END_USER_STATS_RESERVED_20A_MSB 31 680 #define RX_PPDU_END_USER_STATS_RESERVED_20A_MASK 0x00000000ffff0000 681 682 683 684 685 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x0000000000000050 686 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 32 687 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 63 688 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff00000000 689 690 691 692 693 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x0000000000000058 694 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 695 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31 696 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0x00000000ffffffff 697 698 699 700 701 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000058 702 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 703 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 704 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 705 706 707 708 709 #define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000000000000058 710 #define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 33 711 #define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 63 712 #define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xfffffffe00000000 713 714 715 716 #endif 717