1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /////////////////////////////////////////////////////////////////////////////////////////////// 20 // 21 // wcss_seq_hwiobase.h : automatically generated by Autoseq 3.1 10/27/2016 22 // User Name:kanalas 23 // 24 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 25 // 26 /////////////////////////////////////////////////////////////////////////////////////////////// 27 28 #ifndef __WCSS_SEQ_BASE_H__ 29 #define __WCSS_SEQ_BASE_H__ 30 31 #ifdef SCALE_INCLUDES 32 #include "../../../include/HALhwio.h" 33 #else 34 #include "msmhwio.h" 35 #endif 36 37 38 /////////////////////////////////////////////////////////////////////////////////////////////// 39 // Instance Relative Offsets from Block wcss 40 /////////////////////////////////////////////////////////////////////////////////////////////// 41 42 #define SEQ_WCSS_ECAHB_OFFSET 0x00008400 43 #define SEQ_WCSS_ECAHB_TSLV_OFFSET 0x00009000 44 #define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000 45 #define SEQ_WCSS_MPSS_OFFSET 0x00200000 46 #define SEQ_WCSS_MPSS_SEG0PDMEM_WFAX_PCSS_PDMEM_OFFSET 0x00200000 47 #define SEQ_WCSS_MPSS_SEG0_WFAX_PCSS_OFFSET 0x00280000 48 #define SEQ_WCSS_MPSS_SEG0_WFAX_PCSS_DUAL_TIMER_OFFSET 0x00281800 49 #define SEQ_WCSS_MPSS_SEG0_WFAX_PCSS_WATCHDOG_OFFSET 0x00281c00 50 #define SEQ_WCSS_PHYA_OFFSET 0x00400000 51 #define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00400000 52 #define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET 0x00480000 53 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00480400 54 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00480800 55 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00480c00 56 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00481000 57 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00481400 58 #define SEQ_WCSS_PHYA_WFAX_NOC_REG_MAP_OFFSET 0x00484000 59 #define SEQ_WCSS_PHYA_WFAX_TXTD_REG_MAP_OFFSET 0x00488000 60 #define SEQ_WCSS_PHYA_WFAX_TXFD_REG_MAP_OFFSET 0x00500000 61 #define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET 0x00520000 62 #define SEQ_WCSS_PHYA_WFAX_RXTD_REG_MAP_OFFSET 0x00528000 63 #define SEQ_WCSS_PHYA_WFAX_DEMFRONT_NPRA_REG_MAP_OFFSET 0x00530000 64 #define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET 0x005a0000 65 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_OFFSET 0x005c0000 66 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_DIG_OFFSET 0x005c0000 67 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_DIG_OTP_OFFSET 0x005c0000 68 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_DIG_TLMM_OFFSET 0x005c4000 69 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x005c8000 70 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x005d4000 71 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x005d4000 72 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x005d4400 73 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x005d4800 74 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6000 75 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6040 76 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PAL_OFFSET 0x005d6080 77 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d60e0 78 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d6100 79 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6140 80 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d6180 81 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x005d6800 82 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x005d6840 83 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PAL_OFFSET 0x005d6880 84 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x005d68e0 85 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x005d6900 86 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d6940 87 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d6980 88 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x005e0000 89 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x005e0000 90 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x005e0400 91 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x005e0800 92 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH0_OFFSET 0x005e1000 93 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH0_OFFSET 0x005e1200 94 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x005e2000 95 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x005e8000 96 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x005e8400 97 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x005e8800 98 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH1_OFFSET 0x005e9000 99 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH1_OFFSET 0x005e9200 100 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x005ea000 101 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x005f0000 102 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x005f0400 103 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x005f0800 104 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH2_OFFSET 0x005f1000 105 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH2_OFFSET 0x005f1200 106 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x005f2000 107 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x005f8000 108 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x005f8400 109 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x005f8800 110 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH3_OFFSET 0x005f9000 111 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH3_OFFSET 0x005f9200 112 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x005fa000 113 #define SEQ_WCSS_PHYB_OFFSET 0x00600000 114 #define SEQ_WCSS_PHYB_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00600000 115 #define SEQ_WCSS_PHYB_WFAX_PCSS_B_REG_MAP_OFFSET 0x00680000 116 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00680400 117 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00680800 118 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00680c00 119 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00681000 120 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00681400 121 #define SEQ_WCSS_PHYB_WFAX_NOC_B_REG_MAP_OFFSET 0x00684000 122 #define SEQ_WCSS_PHYB_WFAX_TXTD_B_REG_MAP_OFFSET 0x00688000 123 #define SEQ_WCSS_PHYB_WFAX_TXFD_B_REG_MAP_OFFSET 0x00700000 124 #define SEQ_WCSS_PHYB_WFAX_ROBE_B_REG_MAP_OFFSET 0x00720000 125 #define SEQ_WCSS_PHYB_WFAX_RXTD_B_REG_MAP_OFFSET 0x00728000 126 #define SEQ_WCSS_PHYB_WFAX_DEMFRONT_NPRB_B_REG_MAP_OFFSET 0x00730000 127 #define SEQ_WCSS_PHYB_WFAX_PHYRF_B_REG_MAP_OFFSET 0x007a0000 128 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_OFFSET 0x007c0000 129 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OFFSET 0x007c0000 130 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OTP_OFFSET 0x007c0000 131 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_TLMM_OFFSET 0x007c4000 132 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x007c8000 133 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x007d4000 134 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x007d4000 135 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x007d4400 136 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x007d4800 137 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x007d6000 138 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x007d6040 139 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PAL_OFFSET 0x007d6080 140 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x007d60e0 141 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x007d6100 142 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x007d6140 143 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x007d6180 144 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x007d6800 145 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x007d6840 146 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PAL_OFFSET 0x007d6880 147 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x007d68e0 148 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x007d6900 149 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x007d6940 150 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x007d6980 151 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET 0x007e0000 152 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x007e0000 153 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x007e0400 154 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x007e0800 155 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH0_OFFSET 0x007e1000 156 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH0_OFFSET 0x007e1200 157 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x007e2000 158 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x007e8000 159 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x007e8400 160 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x007e8800 161 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH1_OFFSET 0x007e9000 162 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH1_OFFSET 0x007e9200 163 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x007ea000 164 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x007f0000 165 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x007f0400 166 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x007f0800 167 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH2_OFFSET 0x007f1000 168 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH2_OFFSET 0x007f1200 169 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x007f2000 170 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x007f8000 171 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x007f8400 172 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x007f8800 173 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH3_OFFSET 0x007f9000 174 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH3_OFFSET 0x007f9200 175 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x007fa000 176 #define SEQ_WCSS_UMAC_OFFSET 0x00a00000 177 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_OFFSET 0x00a00000 178 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00a00000 179 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00a01000 180 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00a02000 181 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00a03000 182 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00a04000 183 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00a05000 184 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00a06000 185 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00a07000 186 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00a08000 187 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00a09000 188 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x00a0a000 189 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x00a0b000 190 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x00a0c000 191 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x00a0d000 192 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x00a0e000 193 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x00a0f000 194 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00a10000 195 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00a11000 196 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00a12000 197 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00a13000 198 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00a14000 199 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00a15000 200 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00a16000 201 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00a17000 202 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET 0x00a18000 203 #define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000 204 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000 205 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000 206 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000 207 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000 208 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000 209 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000 210 #define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000 211 #define SEQ_WCSS_UMAC_WBM_REG_OFFSET 0x00a34000 212 #define SEQ_WCSS_UMAC_REO_REG_OFFSET 0x00a38000 213 #define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000 214 #define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000 215 #define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET 0x00a44000 216 #define SEQ_WCSS_UMAC_MAC_CMN_PARSER_REG_OFFSET 0x00a47000 217 #define SEQ_WCSS_UMAC_MAC_CCE_REG_OFFSET 0x00a4a000 218 #define SEQ_WCSS_WMAC0_OFFSET 0x00a80000 219 #define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET 0x00a80000 220 #define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET 0x00a83000 221 #define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET 0x00a86000 222 #define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET 0x00a89000 223 #define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET 0x00a8c000 224 #define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET 0x00a8f000 225 #define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET 0x00a92000 226 #define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET 0x00a95000 227 #define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET 0x00a98000 228 #define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET 0x00a9b000 229 #define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET 0x00a9e000 230 #define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET 0x00aa1000 231 #define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET 0x00aa4000 232 #define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET 0x00aa7000 233 #define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET 0x00aaa000 234 #define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET 0x00ab0000 235 #define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000 236 #define SEQ_WCSS_WMAC0_MAC_RXDMA1_REG_OFFSET 0x00ab6000 237 #define SEQ_WCSS_WMAC0_MAC_LPEC_REG_OFFSET 0x00ab9000 238 #define SEQ_WCSS_WMAC1_OFFSET 0x00b00000 239 #define SEQ_WCSS_WMAC1_MAC_PDG_REG_OFFSET 0x00b00000 240 #define SEQ_WCSS_WMAC1_MAC_TXDMA_REG_OFFSET 0x00b03000 241 #define SEQ_WCSS_WMAC1_MAC_RXDMA_REG_OFFSET 0x00b06000 242 #define SEQ_WCSS_WMAC1_MAC_MCMN_REG_OFFSET 0x00b09000 243 #define SEQ_WCSS_WMAC1_MAC_RXPCU_REG_OFFSET 0x00b0c000 244 #define SEQ_WCSS_WMAC1_MAC_TXPCU_REG_OFFSET 0x00b0f000 245 #define SEQ_WCSS_WMAC1_MAC_AMPI_REG_OFFSET 0x00b12000 246 #define SEQ_WCSS_WMAC1_MAC_RXOLE_REG_OFFSET 0x00b15000 247 #define SEQ_WCSS_WMAC1_MAC_RXOLE_PARSER_REG_OFFSET 0x00b18000 248 #define SEQ_WCSS_WMAC1_MAC_CCE_REG_OFFSET 0x00b1b000 249 #define SEQ_WCSS_WMAC1_MAC_TXOLE_REG_OFFSET 0x00b1e000 250 #define SEQ_WCSS_WMAC1_MAC_TXOLE_PARSER_REG_OFFSET 0x00b21000 251 #define SEQ_WCSS_WMAC1_MAC_RRI_REG_OFFSET 0x00b24000 252 #define SEQ_WCSS_WMAC1_MAC_CRYPTO_REG_OFFSET 0x00b27000 253 #define SEQ_WCSS_WMAC1_MAC_HWSCH_REG_OFFSET 0x00b2a000 254 #define SEQ_WCSS_WMAC1_MAC_MXI_REG_OFFSET 0x00b30000 255 #define SEQ_WCSS_WMAC1_MAC_SFM_REG_OFFSET 0x00b33000 256 #define SEQ_WCSS_WMAC1_MAC_RXDMA1_REG_OFFSET 0x00b36000 257 #define SEQ_WCSS_WMAC1_MAC_LPEC_REG_OFFSET 0x00b39000 258 #define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000 259 #define SEQ_WCSS_WCMN_OFFSET 0x00b50000 260 #define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000 261 #define SEQ_WCSS_PMM_OFFSET 0x00b70000 262 #define SEQ_WCSS_DBG_OFFSET 0x00b90000 263 #define SEQ_WCSS_DBG_ROM_WCSS_DBG_DAPROM_OFFSET 0x00b90000 264 #define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000 265 #define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000 266 #define SEQ_WCSS_DBG_CTIDBG_QC_CTI_24T_8CH_OFFSET 0x00b94000 267 #define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000 268 #define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000 269 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET 0x00b98000 270 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00b98280 271 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00b98000 272 #define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET 0x00b99000 273 #define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00b99280 274 #define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00b99000 275 #define SEQ_WCSS_DBG_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET 0x00b9a000 276 #define SEQ_WCSS_DBG_FUN_CXATBFUNNEL_128W8SP_OFFSET 0x00b9b000 277 #define SEQ_WCSS_DBG_TMC_CXTMC_F128W8K_OFFSET 0x00b9c000 278 #define SEQ_WCSS_DBG_UMAC_NOC_UMAC_NOC_OFFSET 0x00ba0000 279 #define SEQ_WCSS_DBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bb0000 280 #define SEQ_WCSS_DBG_PHYA_CTI_QC_CTI_8T_8CH_OFFSET 0x00bb1000 281 #define SEQ_WCSS_DBG_PHYA_NOC_PHYA_NOC_OFFSET 0x00bb6000 282 #define SEQ_WCSS_DBG_PHYA_CPU0_M3_AHB_AP_OFFSET 0x00bbe000 283 #define SEQ_WCSS_DBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc0000 284 #define SEQ_WCSS_DBG_PHYB_CTI_QC_CTI_8T_8CH_OFFSET 0x00bc1000 285 #define SEQ_WCSS_DBG_PHYB_NOC_PHYB_NOC_OFFSET 0x00bc6000 286 #define SEQ_WCSS_DBG_PHYB_CPU0_M3_AHB_AP_OFFSET 0x00bce000 287 #define SEQ_WCSS_DBG_UMAC_CPU_M3_AHB_AP_OFFSET 0x00bf0000 288 #define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00bf1000 289 #define SEQ_WCSS_RET_AHB_OFFSET 0x00c10000 290 #define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00c20000 291 #define SEQ_WCSS_CC_OFFSET 0x00c30000 292 #define SEQ_WCSS_ACMT_OFFSET 0x00c40000 293 #define SEQ_WCSS_Q6SS_PUBCSR_OFFSET 0x00d00000 294 #define SEQ_WCSS_Q6SS_PUBCSR_QDSP6SS_PUB_OFFSET 0x00d00000 295 #define SEQ_WCSS_Q6SS_PRIVCSR_OFFSET 0x00d80000 296 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_CSR_OFFSET 0x00d80000 297 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_OFFSET 0x00d90000 298 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_QTMR_AC_OFFSET 0x00da0000 299 #define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F0_OFFSET 0x00da1000 300 #define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F1_OFFSET 0x00da2000 301 #define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F2_OFFSET 0x00da3000 302 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_OFFSET 0x00db0000 303 304 305 /////////////////////////////////////////////////////////////////////////////////////////////// 306 // Instance Relative Offsets from Block mpss_top 307 /////////////////////////////////////////////////////////////////////////////////////////////// 308 309 #define SEQ_MPSS_TOP_SEG0PDMEM_WFAX_PCSS_PDMEM_OFFSET 0x00000000 310 #define SEQ_MPSS_TOP_SEG0_WFAX_PCSS_OFFSET 0x00080000 311 #define SEQ_MPSS_TOP_SEG0_WFAX_PCSS_DUAL_TIMER_OFFSET 0x00081800 312 #define SEQ_MPSS_TOP_SEG0_WFAX_PCSS_WATCHDOG_OFFSET 0x00081c00 313 314 315 /////////////////////////////////////////////////////////////////////////////////////////////// 316 // Instance Relative Offsets from Block wfax_top 317 /////////////////////////////////////////////////////////////////////////////////////////////// 318 319 #define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00000000 320 #define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET 0x00080000 321 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00080400 322 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00080800 323 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00080c00 324 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00081000 325 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00081400 326 #define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00084000 327 #define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x00088000 328 #define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00100000 329 #define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x00120000 330 #define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x00128000 331 #define SEQ_WFAX_TOP_WFAX_DEMFRONT_NPRA_REG_MAP_OFFSET 0x00130000 332 #define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x001a0000 333 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET 0x001c0000 334 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_DIG_OFFSET 0x001c0000 335 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_DIG_OTP_OFFSET 0x001c0000 336 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_DIG_TLMM_OFFSET 0x001c4000 337 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x001c8000 338 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x001d4000 339 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x001d4000 340 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4400 341 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4800 342 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000 343 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040 344 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PAL_OFFSET 0x001d6080 345 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d60e0 346 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x001d6100 347 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x001d6140 348 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x001d6180 349 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x001d6800 350 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x001d6840 351 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PAL_OFFSET 0x001d6880 352 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x001d68e0 353 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x001d6900 354 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6940 355 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d6980 356 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x001e0000 357 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x001e0000 358 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x001e0400 359 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x001e0800 360 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH0_OFFSET 0x001e1000 361 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH0_OFFSET 0x001e1200 362 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x001e2000 363 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x001e8000 364 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x001e8400 365 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x001e8800 366 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH1_OFFSET 0x001e9000 367 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH1_OFFSET 0x001e9200 368 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x001ea000 369 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x001f0000 370 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x001f0400 371 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x001f0800 372 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH2_OFFSET 0x001f1000 373 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH2_OFFSET 0x001f1200 374 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x001f2000 375 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x001f8000 376 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x001f8400 377 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x001f8800 378 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH3_OFFSET 0x001f9000 379 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH3_OFFSET 0x001f9200 380 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x001fa000 381 382 383 /////////////////////////////////////////////////////////////////////////////////////////////// 384 // Instance Relative Offsets from Block iron2g 385 /////////////////////////////////////////////////////////////////////////////////////////////// 386 387 #define SEQ_IRON2G_RFA_DIG_OFFSET 0x00000000 388 #define SEQ_IRON2G_RFA_DIG_OTP_OFFSET 0x00000000 389 #define SEQ_IRON2G_RFA_DIG_TLMM_OFFSET 0x00004000 390 #define SEQ_IRON2G_RFA_DIG_SYSCTRL_OFFSET 0x00008000 391 #define SEQ_IRON2G_RFA_CMN_OFFSET 0x00014000 392 #define SEQ_IRON2G_RFA_CMN_AON_OFFSET 0x00014000 393 #define SEQ_IRON2G_RFA_CMN_CLKGEN_OFFSET 0x00014400 394 #define SEQ_IRON2G_RFA_CMN_RFFE_M_OFFSET 0x00014800 395 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016000 396 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016040 397 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_PAL_OFFSET 0x00016080 398 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x000160e0 399 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00016100 400 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016140 401 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x00016180 402 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00016800 403 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00016840 404 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_PAL_OFFSET 0x00016880 405 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x000168e0 406 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00016900 407 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00016940 408 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00016980 409 #define SEQ_IRON2G_RFA_WL_OFFSET 0x00020000 410 #define SEQ_IRON2G_RFA_WL_WL_MC_CH0_OFFSET 0x00020000 411 #define SEQ_IRON2G_RFA_WL_WL_RXBB_CH0_OFFSET 0x00020400 412 #define SEQ_IRON2G_RFA_WL_WL_TXBB_CH0_OFFSET 0x00020800 413 #define SEQ_IRON2G_RFA_WL_WL_TXFE_CH0_OFFSET 0x00021000 414 #define SEQ_IRON2G_RFA_WL_WL_RXFE_CH0_OFFSET 0x00021200 415 #define SEQ_IRON2G_RFA_WL_WL_TPC_CH0_OFFSET 0x00022000 416 #define SEQ_IRON2G_RFA_WL_WL_MC_CH1_OFFSET 0x00028000 417 #define SEQ_IRON2G_RFA_WL_WL_RXBB_CH1_OFFSET 0x00028400 418 #define SEQ_IRON2G_RFA_WL_WL_TXBB_CH1_OFFSET 0x00028800 419 #define SEQ_IRON2G_RFA_WL_WL_TXFE_CH1_OFFSET 0x00029000 420 #define SEQ_IRON2G_RFA_WL_WL_RXFE_CH1_OFFSET 0x00029200 421 #define SEQ_IRON2G_RFA_WL_WL_TPC_CH1_OFFSET 0x0002a000 422 #define SEQ_IRON2G_RFA_WL_WL_MC_CH2_OFFSET 0x00030000 423 #define SEQ_IRON2G_RFA_WL_WL_RXBB_CH2_OFFSET 0x00030400 424 #define SEQ_IRON2G_RFA_WL_WL_TXBB_CH2_OFFSET 0x00030800 425 #define SEQ_IRON2G_RFA_WL_WL_TXFE_CH2_OFFSET 0x00031000 426 #define SEQ_IRON2G_RFA_WL_WL_RXFE_CH2_OFFSET 0x00031200 427 #define SEQ_IRON2G_RFA_WL_WL_TPC_CH2_OFFSET 0x00032000 428 #define SEQ_IRON2G_RFA_WL_WL_MC_CH3_OFFSET 0x00038000 429 #define SEQ_IRON2G_RFA_WL_WL_RXBB_CH3_OFFSET 0x00038400 430 #define SEQ_IRON2G_RFA_WL_WL_TXBB_CH3_OFFSET 0x00038800 431 #define SEQ_IRON2G_RFA_WL_WL_TXFE_CH3_OFFSET 0x00039000 432 #define SEQ_IRON2G_RFA_WL_WL_RXFE_CH3_OFFSET 0x00039200 433 #define SEQ_IRON2G_RFA_WL_WL_TPC_CH3_OFFSET 0x0003a000 434 435 436 /////////////////////////////////////////////////////////////////////////////////////////////// 437 // Instance Relative Offsets from Block rfa_dig 438 /////////////////////////////////////////////////////////////////////////////////////////////// 439 440 #define SEQ_RFA_DIG_OTP_OFFSET 0x00000000 441 #define SEQ_RFA_DIG_TLMM_OFFSET 0x00004000 442 #define SEQ_RFA_DIG_SYSCTRL_OFFSET 0x00008000 443 444 445 /////////////////////////////////////////////////////////////////////////////////////////////// 446 // Instance Relative Offsets from Block rfa_cmn 447 /////////////////////////////////////////////////////////////////////////////////////////////// 448 449 #define SEQ_RFA_CMN_AON_OFFSET 0x00000000 450 #define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000400 451 #define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000800 452 #define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002000 453 #define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002040 454 #define SEQ_RFA_CMN_WL_SYNTH0_PAL_OFFSET 0x00002080 455 #define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x000020e0 456 #define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00002100 457 #define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002140 458 #define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x00002180 459 #define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00002800 460 #define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00002840 461 #define SEQ_RFA_CMN_WL_SYNTH1_PAL_OFFSET 0x00002880 462 #define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x000028e0 463 #define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00002900 464 #define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00002940 465 #define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00002980 466 467 468 /////////////////////////////////////////////////////////////////////////////////////////////// 469 // Instance Relative Offsets from Block rfa_wl 470 /////////////////////////////////////////////////////////////////////////////////////////////// 471 472 #define SEQ_RFA_WL_WL_MC_CH0_OFFSET 0x00000000 473 #define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET 0x00000400 474 #define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET 0x00000800 475 #define SEQ_RFA_WL_WL_TXFE_CH0_OFFSET 0x00001000 476 #define SEQ_RFA_WL_WL_RXFE_CH0_OFFSET 0x00001200 477 #define SEQ_RFA_WL_WL_TPC_CH0_OFFSET 0x00002000 478 #define SEQ_RFA_WL_WL_MC_CH1_OFFSET 0x00008000 479 #define SEQ_RFA_WL_WL_RXBB_CH1_OFFSET 0x00008400 480 #define SEQ_RFA_WL_WL_TXBB_CH1_OFFSET 0x00008800 481 #define SEQ_RFA_WL_WL_TXFE_CH1_OFFSET 0x00009000 482 #define SEQ_RFA_WL_WL_RXFE_CH1_OFFSET 0x00009200 483 #define SEQ_RFA_WL_WL_TPC_CH1_OFFSET 0x0000a000 484 #define SEQ_RFA_WL_WL_MC_CH2_OFFSET 0x00010000 485 #define SEQ_RFA_WL_WL_RXBB_CH2_OFFSET 0x00010400 486 #define SEQ_RFA_WL_WL_TXBB_CH2_OFFSET 0x00010800 487 #define SEQ_RFA_WL_WL_TXFE_CH2_OFFSET 0x00011000 488 #define SEQ_RFA_WL_WL_RXFE_CH2_OFFSET 0x00011200 489 #define SEQ_RFA_WL_WL_TPC_CH2_OFFSET 0x00012000 490 #define SEQ_RFA_WL_WL_MC_CH3_OFFSET 0x00018000 491 #define SEQ_RFA_WL_WL_RXBB_CH3_OFFSET 0x00018400 492 #define SEQ_RFA_WL_WL_TXBB_CH3_OFFSET 0x00018800 493 #define SEQ_RFA_WL_WL_TXFE_CH3_OFFSET 0x00019000 494 #define SEQ_RFA_WL_WL_RXFE_CH3_OFFSET 0x00019200 495 #define SEQ_RFA_WL_WL_TPC_CH3_OFFSET 0x0001a000 496 497 498 /////////////////////////////////////////////////////////////////////////////////////////////// 499 // Instance Relative Offsets from Block wfax_top_b 500 /////////////////////////////////////////////////////////////////////////////////////////////// 501 502 #define SEQ_WFAX_TOP_B_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00000000 503 #define SEQ_WFAX_TOP_B_WFAX_PCSS_B_REG_MAP_OFFSET 0x00080000 504 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00080400 505 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00080800 506 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00080c00 507 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00081000 508 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00081400 509 #define SEQ_WFAX_TOP_B_WFAX_NOC_B_REG_MAP_OFFSET 0x00084000 510 #define SEQ_WFAX_TOP_B_WFAX_TXTD_B_REG_MAP_OFFSET 0x00088000 511 #define SEQ_WFAX_TOP_B_WFAX_TXFD_B_REG_MAP_OFFSET 0x00100000 512 #define SEQ_WFAX_TOP_B_WFAX_ROBE_B_REG_MAP_OFFSET 0x00120000 513 #define SEQ_WFAX_TOP_B_WFAX_RXTD_B_REG_MAP_OFFSET 0x00128000 514 #define SEQ_WFAX_TOP_B_WFAX_DEMFRONT_NPRB_B_REG_MAP_OFFSET 0x00130000 515 #define SEQ_WFAX_TOP_B_WFAX_PHYRF_B_REG_MAP_OFFSET 0x001a0000 516 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_OFFSET 0x001c0000 517 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OFFSET 0x001c0000 518 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OTP_OFFSET 0x001c0000 519 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_TLMM_OFFSET 0x001c4000 520 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x001c8000 521 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x001d4000 522 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x001d4000 523 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4400 524 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4800 525 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000 526 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040 527 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PAL_OFFSET 0x001d6080 528 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d60e0 529 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x001d6100 530 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x001d6140 531 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x001d6180 532 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x001d6800 533 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x001d6840 534 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PAL_OFFSET 0x001d6880 535 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x001d68e0 536 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x001d6900 537 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6940 538 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d6980 539 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET 0x001e0000 540 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x001e0000 541 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x001e0400 542 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x001e0800 543 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH0_OFFSET 0x001e1000 544 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH0_OFFSET 0x001e1200 545 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x001e2000 546 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x001e8000 547 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x001e8400 548 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x001e8800 549 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH1_OFFSET 0x001e9000 550 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH1_OFFSET 0x001e9200 551 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x001ea000 552 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x001f0000 553 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x001f0400 554 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x001f0800 555 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH2_OFFSET 0x001f1000 556 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH2_OFFSET 0x001f1200 557 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x001f2000 558 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x001f8000 559 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x001f8400 560 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x001f8800 561 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH3_OFFSET 0x001f9000 562 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH3_OFFSET 0x001f9200 563 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x001fa000 564 565 566 /////////////////////////////////////////////////////////////////////////////////////////////// 567 // Instance Relative Offsets from Block umac_top_reg 568 /////////////////////////////////////////////////////////////////////////////////////////////// 569 570 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_OFFSET 0x00000000 571 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000 572 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000 573 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000 574 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000 575 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000 576 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000 577 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000 578 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000 579 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000 580 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000 581 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000 582 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000 583 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000 584 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000 585 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000 586 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000 587 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000 588 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000 589 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000 590 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000 591 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000 592 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000 593 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000 594 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000 595 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000 596 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000 597 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000 598 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000 599 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000 600 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000 601 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000 602 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000 603 #define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000 604 #define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET 0x00034000 605 #define SEQ_UMAC_TOP_REG_REO_REG_OFFSET 0x00038000 606 #define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000 607 #define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000 608 #define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET 0x00044000 609 #define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_REG_OFFSET 0x00047000 610 #define SEQ_UMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0004a000 611 612 613 /////////////////////////////////////////////////////////////////////////////////////////////// 614 // Instance Relative Offsets from Block wfss_ce_reg 615 /////////////////////////////////////////////////////////////////////////////////////////////// 616 617 #define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000 618 #define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000 619 #define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000 620 #define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000 621 #define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000 622 #define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000 623 #define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000 624 #define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000 625 #define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000 626 #define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000 627 #define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000 628 #define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000 629 #define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000 630 #define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000 631 #define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000 632 #define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000 633 #define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000 634 #define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000 635 #define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000 636 #define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000 637 #define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000 638 #define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000 639 #define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000 640 #define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000 641 #define SEQ_WFSS_CE_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000 642 643 644 /////////////////////////////////////////////////////////////////////////////////////////////// 645 // Instance Relative Offsets from Block cxc_top_reg 646 /////////////////////////////////////////////////////////////////////////////////////////////// 647 648 #define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000 649 #define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000 650 #define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000 651 #define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000 652 #define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000 653 #define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000 654 655 656 /////////////////////////////////////////////////////////////////////////////////////////////// 657 // Instance Relative Offsets from Block wmac_top_reg_28lp 658 /////////////////////////////////////////////////////////////////////////////////////////////// 659 660 #define SEQ_WMAC_TOP_REG_28LP_MAC_PDG_REG_OFFSET 0x00000000 661 #define SEQ_WMAC_TOP_REG_28LP_MAC_TXDMA_REG_OFFSET 0x00003000 662 #define SEQ_WMAC_TOP_REG_28LP_MAC_RXDMA_REG_OFFSET 0x00006000 663 #define SEQ_WMAC_TOP_REG_28LP_MAC_MCMN_REG_OFFSET 0x00009000 664 #define SEQ_WMAC_TOP_REG_28LP_MAC_RXPCU_REG_OFFSET 0x0000c000 665 #define SEQ_WMAC_TOP_REG_28LP_MAC_TXPCU_REG_OFFSET 0x0000f000 666 #define SEQ_WMAC_TOP_REG_28LP_MAC_AMPI_REG_OFFSET 0x00012000 667 #define SEQ_WMAC_TOP_REG_28LP_MAC_RXOLE_REG_OFFSET 0x00015000 668 #define SEQ_WMAC_TOP_REG_28LP_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000 669 #define SEQ_WMAC_TOP_REG_28LP_MAC_CCE_REG_OFFSET 0x0001b000 670 #define SEQ_WMAC_TOP_REG_28LP_MAC_TXOLE_REG_OFFSET 0x0001e000 671 #define SEQ_WMAC_TOP_REG_28LP_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000 672 #define SEQ_WMAC_TOP_REG_28LP_MAC_RRI_REG_OFFSET 0x00024000 673 #define SEQ_WMAC_TOP_REG_28LP_MAC_CRYPTO_REG_OFFSET 0x00027000 674 #define SEQ_WMAC_TOP_REG_28LP_MAC_HWSCH_REG_OFFSET 0x0002a000 675 #define SEQ_WMAC_TOP_REG_28LP_MAC_MXI_REG_OFFSET 0x00030000 676 #define SEQ_WMAC_TOP_REG_28LP_MAC_SFM_REG_OFFSET 0x00033000 677 #define SEQ_WMAC_TOP_REG_28LP_MAC_RXDMA1_REG_OFFSET 0x00036000 678 #define SEQ_WMAC_TOP_REG_28LP_MAC_LPEC_REG_OFFSET 0x00039000 679 680 #define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_PDG_REG_OFFSET 681 #define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_TXDMA_REG_OFFSET 682 #define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_RXDMA_REG_OFFSET 683 #define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_MCMN_REG_OFFSET 684 #define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_RXPCU_REG_OFFSET 685 #define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_TXPCU_REG_OFFSET 686 #define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_AMPI_REG_OFFSET 687 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_RXOLE_REG_OFFSET 688 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_RXOLE_PARSER_REG_OFFSET 689 #define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_CCE_REG_OFFSET 690 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_TXOLE_REG_OFFSET 691 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_TXOLE_PARSER_REG_OFFSET 692 #define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_RRI_REG_OFFSET 693 #define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_CRYPTO_REG_OFFSET 694 #define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_HWSCH_REG_OFFSET 695 #define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_MXI_REG_OFFSET 696 #define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_SFM_REG_OFFSET 697 #define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_RXDMA1_REG_OFFSET 698 #define SEQ_WMAC_TOP_REG_MAC_LPEC_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_LPEC_REG_OFFSET 699 700 /////////////////////////////////////////////////////////////////////////////////////////////// 701 // Instance Relative Offsets from Block wcssdbg_napier 702 /////////////////////////////////////////////////////////////////////////////////////////////// 703 704 #define SEQ_WCSSDBG_NAPIER_ROM_WCSS_DBG_DAPROM_OFFSET 0x00000000 705 #define SEQ_WCSSDBG_NAPIER_CSR_WCSS_DBG_CSR_OFFSET 0x00001000 706 #define SEQ_WCSSDBG_NAPIER_TSGEN_CXTSGEN_OFFSET 0x00002000 707 #define SEQ_WCSSDBG_NAPIER_CTIDBG_QC_CTI_24T_8CH_OFFSET 0x00004000 708 #define SEQ_WCSSDBG_NAPIER_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000 709 #define SEQ_WCSSDBG_NAPIER_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000 710 #define SEQ_WCSSDBG_NAPIER_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET 0x00008000 711 #define SEQ_WCSSDBG_NAPIER_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00008280 712 #define SEQ_WCSSDBG_NAPIER_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00008000 713 #define SEQ_WCSSDBG_NAPIER_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET 0x00009000 714 #define SEQ_WCSSDBG_NAPIER_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00009280 715 #define SEQ_WCSSDBG_NAPIER_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00009000 716 #define SEQ_WCSSDBG_NAPIER_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET 0x0000a000 717 #define SEQ_WCSSDBG_NAPIER_FUN_CXATBFUNNEL_128W8SP_OFFSET 0x0000b000 718 #define SEQ_WCSSDBG_NAPIER_TMC_CXTMC_F128W8K_OFFSET 0x0000c000 719 #define SEQ_WCSSDBG_NAPIER_UMAC_NOC_UMAC_NOC_OFFSET 0x00010000 720 #define SEQ_WCSSDBG_NAPIER_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00020000 721 #define SEQ_WCSSDBG_NAPIER_PHYA_CTI_QC_CTI_8T_8CH_OFFSET 0x00021000 722 #define SEQ_WCSSDBG_NAPIER_PHYA_NOC_PHYA_NOC_OFFSET 0x00026000 723 #define SEQ_WCSSDBG_NAPIER_PHYA_CPU0_M3_AHB_AP_OFFSET 0x0002e000 724 #define SEQ_WCSSDBG_NAPIER_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00030000 725 #define SEQ_WCSSDBG_NAPIER_PHYB_CTI_QC_CTI_8T_8CH_OFFSET 0x00031000 726 #define SEQ_WCSSDBG_NAPIER_PHYB_NOC_PHYB_NOC_OFFSET 0x00036000 727 #define SEQ_WCSSDBG_NAPIER_PHYB_CPU0_M3_AHB_AP_OFFSET 0x0003e000 728 #define SEQ_WCSSDBG_NAPIER_UMAC_CPU_M3_AHB_AP_OFFSET 0x00060000 729 #define SEQ_WCSSDBG_NAPIER_BUS_TIMEOUT_OFFSET 0x00061000 730 731 732 /////////////////////////////////////////////////////////////////////////////////////////////// 733 // Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7 734 /////////////////////////////////////////////////////////////////////////////////////////////// 735 736 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280 737 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000 738 739 740 /////////////////////////////////////////////////////////////////////////////////////////////// 741 // Instance Relative Offsets from Block tpdm_atb32_dsb64_csf49237bd 742 /////////////////////////////////////////////////////////////////////////////////////////////// 743 744 #define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00000280 745 #define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00000000 746 747 748 /////////////////////////////////////////////////////////////////////////////////////////////// 749 // Instance Relative Offsets from Block qdsp6ss_public 750 /////////////////////////////////////////////////////////////////////////////////////////////// 751 752 #define SEQ_QDSP6SS_PUBLIC_QDSP6SS_PUB_OFFSET 0x00000000 753 754 755 /////////////////////////////////////////////////////////////////////////////////////////////// 756 // Instance Relative Offsets from Block qdsp6ss_private 757 /////////////////////////////////////////////////////////////////////////////////////////////// 758 759 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_CSR_OFFSET 0x00000000 760 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_L2VIC_OFFSET 0x00010000 761 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00020000 762 #define SEQ_QDSP6SS_PRIVATE_QTMR_F0_OFFSET 0x00021000 763 #define SEQ_QDSP6SS_PRIVATE_QTMR_F1_OFFSET 0x00022000 764 #define SEQ_QDSP6SS_PRIVATE_QTMR_F2_OFFSET 0x00023000 765 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_SAW2_OFFSET 0x00030000 766 767 768 #endif 769 770