1 2 /* 3 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /////////////////////////////////////////////////////////////////////////////////////////////// 21 // 22 // wcss_seq_hwiobase.h : automatically generated by Autoseq 3.6 3/21/2017 23 // User Name:pgohil 24 // 25 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 26 // 27 /////////////////////////////////////////////////////////////////////////////////////////////// 28 29 #ifndef __WCSS_SEQ_BASE_H__ 30 #define __WCSS_SEQ_BASE_H__ 31 32 #ifdef SCALE_INCLUDES 33 #include "HALhwio.h" 34 #else 35 #include "msmhwio.h" 36 #endif 37 38 39 /////////////////////////////////////////////////////////////////////////////////////////////// 40 // Instance Relative Offsets from Block wcss 41 /////////////////////////////////////////////////////////////////////////////////////////////// 42 43 #define SEQ_WCSS_ECAHB_OFFSET 0x00008000 44 #define SEQ_WCSS_ECAHB_TSLV_OFFSET 0x00009000 45 #define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000 46 #define SEQ_WCSS_MPSS_OFFSET 0x00200000 47 #define SEQ_WCSS_MPSS_SEG0PDMEM_WFAX_PCSS_PDMEM_OFFSET 0x00200000 48 #define SEQ_WCSS_MPSS_SEG0_WFAX_PCSS_OFFSET 0x00280000 49 #define SEQ_WCSS_MPSS_SEG0_WFAX_PCSS_DUAL_TIMER_OFFSET 0x00281800 50 #define SEQ_WCSS_MPSS_SEG0_WFAX_PCSS_WATCHDOG_OFFSET 0x00281c00 51 #define SEQ_WCSS_PHYA0_OFFSET 0x00400000 52 #define SEQ_WCSS_PHYA0_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00400000 53 #define SEQ_WCSS_PHYA0_WFAX_PCSS_REG_MAP_OFFSET 0x00480000 54 #define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00480400 55 #define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00480800 56 #define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00480c00 57 #define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00481000 58 #define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00481400 59 #define SEQ_WCSS_PHYA0_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00481800 60 #define SEQ_WCSS_PHYA0_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00481c00 61 #define SEQ_WCSS_PHYA0_WFAX_NOC_REG_MAP_OFFSET 0x00484000 62 #define SEQ_WCSS_PHYA0_WFAX_TXTD_REG_MAP_OFFSET 0x00488000 63 #define SEQ_WCSS_PHYA0_WFAX_TXFD_REG_MAP_OFFSET 0x00500000 64 #define SEQ_WCSS_PHYA0_WFAX_ROBE_REG_MAP_OFFSET 0x00520000 65 #define SEQ_WCSS_PHYA0_WFAX_RXTD_REG_MAP_OFFSET 0x00528000 66 #define SEQ_WCSS_PHYA0_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00530000 67 #define SEQ_WCSS_PHYA0_WFAX_PHYRF_REG_MAP_OFFSET 0x005a0000 68 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_OFFSET 0x005c0000 69 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_DIG_OFFSET 0x005c0000 70 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_DIG_RFA_TLMM_OFFSET 0x005c0000 71 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x005c8000 72 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x005d4000 73 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x005d4000 74 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x005d4300 75 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x005d4800 76 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6000 77 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6040 78 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d6080 79 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d60c0 80 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6100 81 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d6140 82 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x005d6200 83 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x005d6800 84 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x005d6840 85 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x005d6880 86 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x005d68c0 87 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d6900 88 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d6940 89 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x005d6a00 90 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_DRM_REG_OFFSET 0x005d7c00 91 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x005e0000 92 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x005e0000 93 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x005e0400 94 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x005e0800 95 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH0_OFFSET 0x005e1000 96 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH0_OFFSET 0x005e1180 97 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH0_OFFSET 0x005e1300 98 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH0_OFFSET 0x005e1480 99 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x005e2000 100 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH0_OFFSET 0x005e4000 101 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x005e8000 102 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x005e8400 103 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x005e8800 104 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH1_OFFSET 0x005e9000 105 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH1_OFFSET 0x005e9180 106 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH1_OFFSET 0x005e9300 107 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH1_OFFSET 0x005e9480 108 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x005ea000 109 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH1_OFFSET 0x005ec000 110 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x005f0000 111 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x005f0400 112 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x005f0800 113 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH2_OFFSET 0x005f1000 114 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH2_OFFSET 0x005f1180 115 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH2_OFFSET 0x005f1300 116 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH2_OFFSET 0x005f1480 117 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x005f2000 118 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH2_OFFSET 0x005f4000 119 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x005f8000 120 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x005f8400 121 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x005f8800 122 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH3_OFFSET 0x005f9000 123 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH3_OFFSET 0x005f9180 124 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH3_OFFSET 0x005f9300 125 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH3_OFFSET 0x005f9480 126 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x005fa000 127 #define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH3_OFFSET 0x005fc000 128 #define SEQ_WCSS_IRONA0_OFFSET 0x005c0000 129 #define SEQ_WCSS_IRONA0_RFA_DIG_OFFSET 0x005c0000 130 #define SEQ_WCSS_IRONA0_RFA_DIG_RFA_TLMM_OFFSET 0x005c0000 131 #define SEQ_WCSS_IRONA0_RFA_DIG_SYSCTRL_OFFSET 0x005c8000 132 #define SEQ_WCSS_IRONA0_RFA_CMN_OFFSET 0x005d4000 133 #define SEQ_WCSS_IRONA0_RFA_CMN_AON_OFFSET 0x005d4000 134 #define SEQ_WCSS_IRONA0_RFA_CMN_RFFE_M_OFFSET 0x005d4300 135 #define SEQ_WCSS_IRONA0_RFA_CMN_CLKGEN_OFFSET 0x005d4800 136 #define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6000 137 #define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6040 138 #define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d6080 139 #define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d60c0 140 #define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6100 141 #define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d6140 142 #define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x005d6200 143 #define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x005d6800 144 #define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x005d6840 145 #define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x005d6880 146 #define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x005d68c0 147 #define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d6900 148 #define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d6940 149 #define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x005d6a00 150 #define SEQ_WCSS_IRONA0_RFA_CMN_DRM_REG_OFFSET 0x005d7c00 151 #define SEQ_WCSS_IRONA0_RFA_WL_OFFSET 0x005e0000 152 #define SEQ_WCSS_IRONA0_RFA_WL_WL_MC_CH0_OFFSET 0x005e0000 153 #define SEQ_WCSS_IRONA0_RFA_WL_WL_RXBB_CH0_OFFSET 0x005e0400 154 #define SEQ_WCSS_IRONA0_RFA_WL_WL_TXBB_CH0_OFFSET 0x005e0800 155 #define SEQ_WCSS_IRONA0_RFA_WL_WL_RXFE2_CH0_OFFSET 0x005e1000 156 #define SEQ_WCSS_IRONA0_RFA_WL_WL_RXFE5_CH0_OFFSET 0x005e1180 157 #define SEQ_WCSS_IRONA0_RFA_WL_WL_TXFE2_CH0_OFFSET 0x005e1300 158 #define SEQ_WCSS_IRONA0_RFA_WL_WL_TXFE5_CH0_OFFSET 0x005e1480 159 #define SEQ_WCSS_IRONA0_RFA_WL_WL_TPC_CH0_OFFSET 0x005e2000 160 #define SEQ_WCSS_IRONA0_RFA_WL_WL_MEM_CH0_OFFSET 0x005e4000 161 #define SEQ_WCSS_IRONA0_RFA_WL_WL_MC_CH1_OFFSET 0x005e8000 162 #define SEQ_WCSS_IRONA0_RFA_WL_WL_RXBB_CH1_OFFSET 0x005e8400 163 #define SEQ_WCSS_IRONA0_RFA_WL_WL_TXBB_CH1_OFFSET 0x005e8800 164 #define SEQ_WCSS_IRONA0_RFA_WL_WL_RXFE2_CH1_OFFSET 0x005e9000 165 #define SEQ_WCSS_IRONA0_RFA_WL_WL_RXFE5_CH1_OFFSET 0x005e9180 166 #define SEQ_WCSS_IRONA0_RFA_WL_WL_TXFE2_CH1_OFFSET 0x005e9300 167 #define SEQ_WCSS_IRONA0_RFA_WL_WL_TXFE5_CH1_OFFSET 0x005e9480 168 #define SEQ_WCSS_IRONA0_RFA_WL_WL_TPC_CH1_OFFSET 0x005ea000 169 #define SEQ_WCSS_IRONA0_RFA_WL_WL_MEM_CH1_OFFSET 0x005ec000 170 #define SEQ_WCSS_IRONA0_RFA_WL_WL_MC_CH2_OFFSET 0x005f0000 171 #define SEQ_WCSS_IRONA0_RFA_WL_WL_RXBB_CH2_OFFSET 0x005f0400 172 #define SEQ_WCSS_IRONA0_RFA_WL_WL_TXBB_CH2_OFFSET 0x005f0800 173 #define SEQ_WCSS_IRONA0_RFA_WL_WL_RXFE2_CH2_OFFSET 0x005f1000 174 #define SEQ_WCSS_IRONA0_RFA_WL_WL_RXFE5_CH2_OFFSET 0x005f1180 175 #define SEQ_WCSS_IRONA0_RFA_WL_WL_TXFE2_CH2_OFFSET 0x005f1300 176 #define SEQ_WCSS_IRONA0_RFA_WL_WL_TXFE5_CH2_OFFSET 0x005f1480 177 #define SEQ_WCSS_IRONA0_RFA_WL_WL_TPC_CH2_OFFSET 0x005f2000 178 #define SEQ_WCSS_IRONA0_RFA_WL_WL_MEM_CH2_OFFSET 0x005f4000 179 #define SEQ_WCSS_IRONA0_RFA_WL_WL_MC_CH3_OFFSET 0x005f8000 180 #define SEQ_WCSS_IRONA0_RFA_WL_WL_RXBB_CH3_OFFSET 0x005f8400 181 #define SEQ_WCSS_IRONA0_RFA_WL_WL_TXBB_CH3_OFFSET 0x005f8800 182 #define SEQ_WCSS_IRONA0_RFA_WL_WL_RXFE2_CH3_OFFSET 0x005f9000 183 #define SEQ_WCSS_IRONA0_RFA_WL_WL_RXFE5_CH3_OFFSET 0x005f9180 184 #define SEQ_WCSS_IRONA0_RFA_WL_WL_TXFE2_CH3_OFFSET 0x005f9300 185 #define SEQ_WCSS_IRONA0_RFA_WL_WL_TXFE5_CH3_OFFSET 0x005f9480 186 #define SEQ_WCSS_IRONA0_RFA_WL_WL_TPC_CH3_OFFSET 0x005fa000 187 #define SEQ_WCSS_IRONA0_RFA_WL_WL_MEM_CH3_OFFSET 0x005fc000 188 #define SEQ_WCSS_PHYA1_OFFSET 0x00600000 189 #define SEQ_WCSS_PHYA1_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00600000 190 #define SEQ_WCSS_PHYA1_WFAX_PCSS_REG_MAP_OFFSET 0x00680000 191 #define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00680400 192 #define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00680800 193 #define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00680c00 194 #define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00681000 195 #define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00681400 196 #define SEQ_WCSS_PHYA1_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00681800 197 #define SEQ_WCSS_PHYA1_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00681c00 198 #define SEQ_WCSS_PHYA1_WFAX_NOC_REG_MAP_OFFSET 0x00684000 199 #define SEQ_WCSS_PHYA1_WFAX_TXTD_REG_MAP_OFFSET 0x00688000 200 #define SEQ_WCSS_PHYA1_WFAX_TXFD_REG_MAP_OFFSET 0x00700000 201 #define SEQ_WCSS_PHYA1_WFAX_ROBE_REG_MAP_OFFSET 0x00720000 202 #define SEQ_WCSS_PHYA1_WFAX_RXTD_REG_MAP_OFFSET 0x00728000 203 #define SEQ_WCSS_PHYA1_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00730000 204 #define SEQ_WCSS_PHYA1_WFAX_PHYRF_REG_MAP_OFFSET 0x007a0000 205 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_OFFSET 0x007c0000 206 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_DIG_OFFSET 0x007c0000 207 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_DIG_RFA_TLMM_OFFSET 0x007c0000 208 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x007c8000 209 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x007d4000 210 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x007d4000 211 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x007d4300 212 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x007d4800 213 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x007d6000 214 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x007d6040 215 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x007d6080 216 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x007d60c0 217 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x007d6100 218 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x007d6140 219 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x007d6200 220 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x007d6800 221 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x007d6840 222 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x007d6880 223 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x007d68c0 224 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x007d6900 225 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x007d6940 226 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x007d6a00 227 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_DRM_REG_OFFSET 0x007d7c00 228 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x007e0000 229 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x007e0000 230 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x007e0400 231 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x007e0800 232 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH0_OFFSET 0x007e1000 233 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH0_OFFSET 0x007e1180 234 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH0_OFFSET 0x007e1300 235 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH0_OFFSET 0x007e1480 236 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x007e2000 237 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH0_OFFSET 0x007e4000 238 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x007e8000 239 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x007e8400 240 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x007e8800 241 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH1_OFFSET 0x007e9000 242 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH1_OFFSET 0x007e9180 243 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH1_OFFSET 0x007e9300 244 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH1_OFFSET 0x007e9480 245 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x007ea000 246 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH1_OFFSET 0x007ec000 247 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x007f0000 248 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x007f0400 249 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x007f0800 250 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH2_OFFSET 0x007f1000 251 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH2_OFFSET 0x007f1180 252 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH2_OFFSET 0x007f1300 253 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH2_OFFSET 0x007f1480 254 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x007f2000 255 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH2_OFFSET 0x007f4000 256 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x007f8000 257 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x007f8400 258 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x007f8800 259 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH3_OFFSET 0x007f9000 260 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH3_OFFSET 0x007f9180 261 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH3_OFFSET 0x007f9300 262 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH3_OFFSET 0x007f9480 263 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x007fa000 264 #define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH3_OFFSET 0x007fc000 265 #define SEQ_WCSS_IRONA1_OFFSET 0x007c0000 266 #define SEQ_WCSS_IRONA1_RFA_DIG_OFFSET 0x007c0000 267 #define SEQ_WCSS_IRONA1_RFA_DIG_RFA_TLMM_OFFSET 0x007c0000 268 #define SEQ_WCSS_IRONA1_RFA_DIG_SYSCTRL_OFFSET 0x007c8000 269 #define SEQ_WCSS_IRONA1_RFA_CMN_OFFSET 0x007d4000 270 #define SEQ_WCSS_IRONA1_RFA_CMN_AON_OFFSET 0x007d4000 271 #define SEQ_WCSS_IRONA1_RFA_CMN_RFFE_M_OFFSET 0x007d4300 272 #define SEQ_WCSS_IRONA1_RFA_CMN_CLKGEN_OFFSET 0x007d4800 273 #define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x007d6000 274 #define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x007d6040 275 #define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x007d6080 276 #define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x007d60c0 277 #define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x007d6100 278 #define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x007d6140 279 #define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x007d6200 280 #define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x007d6800 281 #define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x007d6840 282 #define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x007d6880 283 #define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x007d68c0 284 #define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x007d6900 285 #define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x007d6940 286 #define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x007d6a00 287 #define SEQ_WCSS_IRONA1_RFA_CMN_DRM_REG_OFFSET 0x007d7c00 288 #define SEQ_WCSS_IRONA1_RFA_WL_OFFSET 0x007e0000 289 #define SEQ_WCSS_IRONA1_RFA_WL_WL_MC_CH0_OFFSET 0x007e0000 290 #define SEQ_WCSS_IRONA1_RFA_WL_WL_RXBB_CH0_OFFSET 0x007e0400 291 #define SEQ_WCSS_IRONA1_RFA_WL_WL_TXBB_CH0_OFFSET 0x007e0800 292 #define SEQ_WCSS_IRONA1_RFA_WL_WL_RXFE2_CH0_OFFSET 0x007e1000 293 #define SEQ_WCSS_IRONA1_RFA_WL_WL_RXFE5_CH0_OFFSET 0x007e1180 294 #define SEQ_WCSS_IRONA1_RFA_WL_WL_TXFE2_CH0_OFFSET 0x007e1300 295 #define SEQ_WCSS_IRONA1_RFA_WL_WL_TXFE5_CH0_OFFSET 0x007e1480 296 #define SEQ_WCSS_IRONA1_RFA_WL_WL_TPC_CH0_OFFSET 0x007e2000 297 #define SEQ_WCSS_IRONA1_RFA_WL_WL_MEM_CH0_OFFSET 0x007e4000 298 #define SEQ_WCSS_IRONA1_RFA_WL_WL_MC_CH1_OFFSET 0x007e8000 299 #define SEQ_WCSS_IRONA1_RFA_WL_WL_RXBB_CH1_OFFSET 0x007e8400 300 #define SEQ_WCSS_IRONA1_RFA_WL_WL_TXBB_CH1_OFFSET 0x007e8800 301 #define SEQ_WCSS_IRONA1_RFA_WL_WL_RXFE2_CH1_OFFSET 0x007e9000 302 #define SEQ_WCSS_IRONA1_RFA_WL_WL_RXFE5_CH1_OFFSET 0x007e9180 303 #define SEQ_WCSS_IRONA1_RFA_WL_WL_TXFE2_CH1_OFFSET 0x007e9300 304 #define SEQ_WCSS_IRONA1_RFA_WL_WL_TXFE5_CH1_OFFSET 0x007e9480 305 #define SEQ_WCSS_IRONA1_RFA_WL_WL_TPC_CH1_OFFSET 0x007ea000 306 #define SEQ_WCSS_IRONA1_RFA_WL_WL_MEM_CH1_OFFSET 0x007ec000 307 #define SEQ_WCSS_IRONA1_RFA_WL_WL_MC_CH2_OFFSET 0x007f0000 308 #define SEQ_WCSS_IRONA1_RFA_WL_WL_RXBB_CH2_OFFSET 0x007f0400 309 #define SEQ_WCSS_IRONA1_RFA_WL_WL_TXBB_CH2_OFFSET 0x007f0800 310 #define SEQ_WCSS_IRONA1_RFA_WL_WL_RXFE2_CH2_OFFSET 0x007f1000 311 #define SEQ_WCSS_IRONA1_RFA_WL_WL_RXFE5_CH2_OFFSET 0x007f1180 312 #define SEQ_WCSS_IRONA1_RFA_WL_WL_TXFE2_CH2_OFFSET 0x007f1300 313 #define SEQ_WCSS_IRONA1_RFA_WL_WL_TXFE5_CH2_OFFSET 0x007f1480 314 #define SEQ_WCSS_IRONA1_RFA_WL_WL_TPC_CH2_OFFSET 0x007f2000 315 #define SEQ_WCSS_IRONA1_RFA_WL_WL_MEM_CH2_OFFSET 0x007f4000 316 #define SEQ_WCSS_IRONA1_RFA_WL_WL_MC_CH3_OFFSET 0x007f8000 317 #define SEQ_WCSS_IRONA1_RFA_WL_WL_RXBB_CH3_OFFSET 0x007f8400 318 #define SEQ_WCSS_IRONA1_RFA_WL_WL_TXBB_CH3_OFFSET 0x007f8800 319 #define SEQ_WCSS_IRONA1_RFA_WL_WL_RXFE2_CH3_OFFSET 0x007f9000 320 #define SEQ_WCSS_IRONA1_RFA_WL_WL_RXFE5_CH3_OFFSET 0x007f9180 321 #define SEQ_WCSS_IRONA1_RFA_WL_WL_TXFE2_CH3_OFFSET 0x007f9300 322 #define SEQ_WCSS_IRONA1_RFA_WL_WL_TXFE5_CH3_OFFSET 0x007f9480 323 #define SEQ_WCSS_IRONA1_RFA_WL_WL_TPC_CH3_OFFSET 0x007fa000 324 #define SEQ_WCSS_IRONA1_RFA_WL_WL_MEM_CH3_OFFSET 0x007fc000 325 #define SEQ_WCSS_PHYB_OFFSET 0x00800000 326 #define SEQ_WCSS_PHYB_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00800000 327 #define SEQ_WCSS_PHYB_WFAX_PCSS_B_REG_MAP_OFFSET 0x00880000 328 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00880400 329 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00880800 330 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00880c00 331 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00881000 332 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00881400 333 #define SEQ_WCSS_PHYB_WFAX_PCSS_DUAL_TIMER_B_REG_MAP_OFFSET 0x00881800 334 #define SEQ_WCSS_PHYB_WFAX_PCSS_WATCHDOG_B_REG_MAP_OFFSET 0x00881c00 335 #define SEQ_WCSS_PHYB_WFAX_NOC_B_REG_MAP_OFFSET 0x00884000 336 #define SEQ_WCSS_PHYB_WFAX_TXTD_B_REG_MAP_OFFSET 0x00888000 337 #define SEQ_WCSS_PHYB_WFAX_TXFD_B_REG_MAP_OFFSET 0x00900000 338 #define SEQ_WCSS_PHYB_WFAX_ROBE_B_REG_MAP_OFFSET 0x00920000 339 #define SEQ_WCSS_PHYB_WFAX_RXTD_B_REG_MAP_OFFSET 0x00928000 340 #define SEQ_WCSS_PHYB_WFAX_DEMFRONT_B_REG_MAP_OFFSET 0x00930000 341 #define SEQ_WCSS_PHYB_WFAX_PHYRF_B_REG_MAP_OFFSET 0x009a0000 342 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_OFFSET 0x009c0000 343 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OFFSET 0x009c0000 344 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_RFA_TLMM_OFFSET 0x009c0000 345 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x009c8000 346 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x009d4000 347 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x009d4000 348 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x009d4300 349 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x009d4800 350 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x009d6000 351 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x009d6040 352 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x009d6080 353 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x009d60c0 354 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x009d6100 355 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x009d6140 356 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x009d6200 357 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x009d6800 358 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x009d6840 359 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x009d6880 360 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x009d68c0 361 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x009d6900 362 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x009d6940 363 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x009d6a00 364 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_DRM_REG_OFFSET 0x009d7c00 365 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET 0x009e0000 366 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x009e0000 367 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x009e0400 368 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x009e0800 369 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH0_OFFSET 0x009e1000 370 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH0_OFFSET 0x009e1180 371 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH0_OFFSET 0x009e1300 372 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH0_OFFSET 0x009e1480 373 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x009e2000 374 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH0_OFFSET 0x009e4000 375 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x009e8000 376 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x009e8400 377 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x009e8800 378 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH1_OFFSET 0x009e9000 379 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH1_OFFSET 0x009e9180 380 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH1_OFFSET 0x009e9300 381 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH1_OFFSET 0x009e9480 382 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x009ea000 383 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH1_OFFSET 0x009ec000 384 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x009f0000 385 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x009f0400 386 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x009f0800 387 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH2_OFFSET 0x009f1000 388 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH2_OFFSET 0x009f1180 389 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH2_OFFSET 0x009f1300 390 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH2_OFFSET 0x009f1480 391 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x009f2000 392 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH2_OFFSET 0x009f4000 393 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x009f8000 394 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x009f8400 395 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x009f8800 396 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH3_OFFSET 0x009f9000 397 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH3_OFFSET 0x009f9180 398 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH3_OFFSET 0x009f9300 399 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH3_OFFSET 0x009f9480 400 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x009fa000 401 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH3_OFFSET 0x009fc000 402 #define SEQ_WCSS_IRONB_OFFSET 0x009c0000 403 #define SEQ_WCSS_IRONB_RFA_DIG_OFFSET 0x009c0000 404 #define SEQ_WCSS_IRONB_RFA_DIG_RFA_TLMM_OFFSET 0x009c0000 405 #define SEQ_WCSS_IRONB_RFA_DIG_SYSCTRL_OFFSET 0x009c8000 406 #define SEQ_WCSS_IRONB_RFA_CMN_OFFSET 0x009d4000 407 #define SEQ_WCSS_IRONB_RFA_CMN_AON_OFFSET 0x009d4000 408 #define SEQ_WCSS_IRONB_RFA_CMN_RFFE_M_OFFSET 0x009d4300 409 #define SEQ_WCSS_IRONB_RFA_CMN_CLKGEN_OFFSET 0x009d4800 410 #define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x009d6000 411 #define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x009d6040 412 #define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x009d6080 413 #define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x009d60c0 414 #define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x009d6100 415 #define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x009d6140 416 #define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x009d6200 417 #define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x009d6800 418 #define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x009d6840 419 #define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x009d6880 420 #define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x009d68c0 421 #define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x009d6900 422 #define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x009d6940 423 #define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x009d6a00 424 #define SEQ_WCSS_IRONB_RFA_CMN_DRM_REG_OFFSET 0x009d7c00 425 #define SEQ_WCSS_IRONB_RFA_WL_OFFSET 0x009e0000 426 #define SEQ_WCSS_IRONB_RFA_WL_WL_MC_CH0_OFFSET 0x009e0000 427 #define SEQ_WCSS_IRONB_RFA_WL_WL_RXBB_CH0_OFFSET 0x009e0400 428 #define SEQ_WCSS_IRONB_RFA_WL_WL_TXBB_CH0_OFFSET 0x009e0800 429 #define SEQ_WCSS_IRONB_RFA_WL_WL_RXFE2_CH0_OFFSET 0x009e1000 430 #define SEQ_WCSS_IRONB_RFA_WL_WL_RXFE5_CH0_OFFSET 0x009e1180 431 #define SEQ_WCSS_IRONB_RFA_WL_WL_TXFE2_CH0_OFFSET 0x009e1300 432 #define SEQ_WCSS_IRONB_RFA_WL_WL_TXFE5_CH0_OFFSET 0x009e1480 433 #define SEQ_WCSS_IRONB_RFA_WL_WL_TPC_CH0_OFFSET 0x009e2000 434 #define SEQ_WCSS_IRONB_RFA_WL_WL_MEM_CH0_OFFSET 0x009e4000 435 #define SEQ_WCSS_IRONB_RFA_WL_WL_MC_CH1_OFFSET 0x009e8000 436 #define SEQ_WCSS_IRONB_RFA_WL_WL_RXBB_CH1_OFFSET 0x009e8400 437 #define SEQ_WCSS_IRONB_RFA_WL_WL_TXBB_CH1_OFFSET 0x009e8800 438 #define SEQ_WCSS_IRONB_RFA_WL_WL_RXFE2_CH1_OFFSET 0x009e9000 439 #define SEQ_WCSS_IRONB_RFA_WL_WL_RXFE5_CH1_OFFSET 0x009e9180 440 #define SEQ_WCSS_IRONB_RFA_WL_WL_TXFE2_CH1_OFFSET 0x009e9300 441 #define SEQ_WCSS_IRONB_RFA_WL_WL_TXFE5_CH1_OFFSET 0x009e9480 442 #define SEQ_WCSS_IRONB_RFA_WL_WL_TPC_CH1_OFFSET 0x009ea000 443 #define SEQ_WCSS_IRONB_RFA_WL_WL_MEM_CH1_OFFSET 0x009ec000 444 #define SEQ_WCSS_IRONB_RFA_WL_WL_MC_CH2_OFFSET 0x009f0000 445 #define SEQ_WCSS_IRONB_RFA_WL_WL_RXBB_CH2_OFFSET 0x009f0400 446 #define SEQ_WCSS_IRONB_RFA_WL_WL_TXBB_CH2_OFFSET 0x009f0800 447 #define SEQ_WCSS_IRONB_RFA_WL_WL_RXFE2_CH2_OFFSET 0x009f1000 448 #define SEQ_WCSS_IRONB_RFA_WL_WL_RXFE5_CH2_OFFSET 0x009f1180 449 #define SEQ_WCSS_IRONB_RFA_WL_WL_TXFE2_CH2_OFFSET 0x009f1300 450 #define SEQ_WCSS_IRONB_RFA_WL_WL_TXFE5_CH2_OFFSET 0x009f1480 451 #define SEQ_WCSS_IRONB_RFA_WL_WL_TPC_CH2_OFFSET 0x009f2000 452 #define SEQ_WCSS_IRONB_RFA_WL_WL_MEM_CH2_OFFSET 0x009f4000 453 #define SEQ_WCSS_IRONB_RFA_WL_WL_MC_CH3_OFFSET 0x009f8000 454 #define SEQ_WCSS_IRONB_RFA_WL_WL_RXBB_CH3_OFFSET 0x009f8400 455 #define SEQ_WCSS_IRONB_RFA_WL_WL_TXBB_CH3_OFFSET 0x009f8800 456 #define SEQ_WCSS_IRONB_RFA_WL_WL_RXFE2_CH3_OFFSET 0x009f9000 457 #define SEQ_WCSS_IRONB_RFA_WL_WL_RXFE5_CH3_OFFSET 0x009f9180 458 #define SEQ_WCSS_IRONB_RFA_WL_WL_TXFE2_CH3_OFFSET 0x009f9300 459 #define SEQ_WCSS_IRONB_RFA_WL_WL_TXFE5_CH3_OFFSET 0x009f9480 460 #define SEQ_WCSS_IRONB_RFA_WL_WL_TPC_CH3_OFFSET 0x009fa000 461 #define SEQ_WCSS_IRONB_RFA_WL_WL_MEM_CH3_OFFSET 0x009fc000 462 #define SEQ_WCSS_UMAC_OFFSET 0x00a00000 463 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_OFFSET 0x00a00000 464 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00a00000 465 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00a01000 466 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00a02000 467 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00a03000 468 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00a04000 469 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00a05000 470 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00a06000 471 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00a07000 472 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00a08000 473 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00a09000 474 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x00a0a000 475 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x00a0b000 476 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x00a0c000 477 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x00a0d000 478 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x00a0e000 479 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x00a0f000 480 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00a10000 481 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00a11000 482 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00a12000 483 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00a13000 484 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00a14000 485 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00a15000 486 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00a16000 487 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00a17000 488 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET 0x00a18000 489 #define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000 490 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000 491 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000 492 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000 493 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000 494 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000 495 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000 496 #define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000 497 #define SEQ_WCSS_UMAC_WBM_REG_OFFSET 0x00a34000 498 #define SEQ_WCSS_UMAC_REO_REG_OFFSET 0x00a38000 499 #define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000 500 #define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000 501 #define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET 0x00a44000 502 #define SEQ_WCSS_UMAC_MAC_CMN_PARSER_REG_OFFSET 0x00a47000 503 #define SEQ_WCSS_UMAC_MAC_CCE_REG_OFFSET 0x00a4a000 504 #define SEQ_WCSS_WMAC0_OFFSET 0x00a80000 505 #define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET 0x00a80000 506 #define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET 0x00a83000 507 #define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET 0x00a86000 508 #define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET 0x00a89000 509 #define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET 0x00a8c000 510 #define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET 0x00a8f000 511 #define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET 0x00a92000 512 #define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET 0x00a95000 513 #define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET 0x00a98000 514 #define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET 0x00a9b000 515 #define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET 0x00a9e000 516 #define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET 0x00aa1000 517 #define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET 0x00aa4000 518 #define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET 0x00aa7000 519 #define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET 0x00aaa000 520 #define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET 0x00ab0000 521 #define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000 522 #define SEQ_WCSS_WMAC0_MAC_RXDMA1_REG_OFFSET 0x00ab6000 523 #define SEQ_WCSS_WMAC0_MAC_LPEC_REG_OFFSET 0x00ab9000 524 #define SEQ_WCSS_WMAC1_OFFSET 0x00ac0000 525 #define SEQ_WCSS_WMAC1_MAC_PDG_REG_OFFSET 0x00ac0000 526 #define SEQ_WCSS_WMAC1_MAC_TXDMA_REG_OFFSET 0x00ac3000 527 #define SEQ_WCSS_WMAC1_MAC_RXDMA_REG_OFFSET 0x00ac6000 528 #define SEQ_WCSS_WMAC1_MAC_MCMN_REG_OFFSET 0x00ac9000 529 #define SEQ_WCSS_WMAC1_MAC_RXPCU_REG_OFFSET 0x00acc000 530 #define SEQ_WCSS_WMAC1_MAC_TXPCU_REG_OFFSET 0x00acf000 531 #define SEQ_WCSS_WMAC1_MAC_AMPI_REG_OFFSET 0x00ad2000 532 #define SEQ_WCSS_WMAC1_MAC_RXOLE_REG_OFFSET 0x00ad5000 533 #define SEQ_WCSS_WMAC1_MAC_RXOLE_PARSER_REG_OFFSET 0x00ad8000 534 #define SEQ_WCSS_WMAC1_MAC_CCE_REG_OFFSET 0x00adb000 535 #define SEQ_WCSS_WMAC1_MAC_TXOLE_REG_OFFSET 0x00ade000 536 #define SEQ_WCSS_WMAC1_MAC_TXOLE_PARSER_REG_OFFSET 0x00ae1000 537 #define SEQ_WCSS_WMAC1_MAC_RRI_REG_OFFSET 0x00ae4000 538 #define SEQ_WCSS_WMAC1_MAC_CRYPTO_REG_OFFSET 0x00ae7000 539 #define SEQ_WCSS_WMAC1_MAC_HWSCH_REG_OFFSET 0x00aea000 540 #define SEQ_WCSS_WMAC1_MAC_MXI_REG_OFFSET 0x00af0000 541 #define SEQ_WCSS_WMAC1_MAC_SFM_REG_OFFSET 0x00af3000 542 #define SEQ_WCSS_WMAC1_MAC_RXDMA1_REG_OFFSET 0x00af6000 543 #define SEQ_WCSS_WMAC1_MAC_LPEC_REG_OFFSET 0x00af9000 544 #define SEQ_WCSS_WMAC2_OFFSET 0x00b00000 545 #define SEQ_WCSS_WMAC2_MAC_PDG_REG_OFFSET 0x00b00000 546 #define SEQ_WCSS_WMAC2_MAC_TXDMA_REG_OFFSET 0x00b03000 547 #define SEQ_WCSS_WMAC2_MAC_RXDMA_REG_OFFSET 0x00b06000 548 #define SEQ_WCSS_WMAC2_MAC_MCMN_REG_OFFSET 0x00b09000 549 #define SEQ_WCSS_WMAC2_MAC_RXPCU_REG_OFFSET 0x00b0c000 550 #define SEQ_WCSS_WMAC2_MAC_TXPCU_REG_OFFSET 0x00b0f000 551 #define SEQ_WCSS_WMAC2_MAC_AMPI_REG_OFFSET 0x00b12000 552 #define SEQ_WCSS_WMAC2_MAC_RXOLE_REG_OFFSET 0x00b15000 553 #define SEQ_WCSS_WMAC2_MAC_RXOLE_PARSER_REG_OFFSET 0x00b18000 554 #define SEQ_WCSS_WMAC2_MAC_CCE_REG_OFFSET 0x00b1b000 555 #define SEQ_WCSS_WMAC2_MAC_TXOLE_REG_OFFSET 0x00b1e000 556 #define SEQ_WCSS_WMAC2_MAC_TXOLE_PARSER_REG_OFFSET 0x00b21000 557 #define SEQ_WCSS_WMAC2_MAC_RRI_REG_OFFSET 0x00b24000 558 #define SEQ_WCSS_WMAC2_MAC_CRYPTO_REG_OFFSET 0x00b27000 559 #define SEQ_WCSS_WMAC2_MAC_HWSCH_REG_OFFSET 0x00b2a000 560 #define SEQ_WCSS_WMAC2_MAC_MXI_REG_OFFSET 0x00b30000 561 #define SEQ_WCSS_WMAC2_MAC_SFM_REG_OFFSET 0x00b33000 562 #define SEQ_WCSS_WMAC2_MAC_RXDMA1_REG_OFFSET 0x00b36000 563 #define SEQ_WCSS_WMAC2_MAC_LPEC_REG_OFFSET 0x00b39000 564 #define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000 565 #define SEQ_WCSS_WCMN_OFFSET 0x00b50000 566 #define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000 567 #define SEQ_WCSS_PMM_OFFSET 0x00b70000 568 #define SEQ_WCSS_ZINC_RFA_CMN_OFFSET 0x00b80000 569 #define SEQ_WCSS_ZINC_RFA_CMN_PLL_A_OFFSET 0x00b80000 570 #define SEQ_WCSS_ZINC_RFA_CMN_BIASCLKS_A_OFFSET 0x00b80100 571 #define SEQ_WCSS_ZINC_RFA_CMN_PLL_B_OFFSET 0x00b82000 572 #define SEQ_WCSS_ZINC_RFA_CMN_BIASCLKS_B_OFFSET 0x00b82100 573 #define SEQ_WCSS_ZINC_RFA_CMN_PHYB_ROOTCLKGEN_OFFSET 0x00b84000 574 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH0_OFFSET 0x00b88000 575 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH0_OFFSET 0x00b88100 576 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH0_OFFSET 0x00b88180 577 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA0_CH0_OFFSET 0x00b881c0 578 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYA0_CH0_OFFSET 0x00b882c0 579 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH0_OFFSET 0x00b88340 580 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH0_OFFSET 0x00b88400 581 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH0_OFFSET 0x00b88440 582 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH0_OFFSET 0x00b88480 583 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH0_OFFSET 0x00b884c0 584 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH0_OFFSET 0x00b88500 585 #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH0_OFFSET 0x00b88600 586 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH1_OFFSET 0x00b88800 587 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH1_OFFSET 0x00b88900 588 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH1_OFFSET 0x00b88980 589 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA0_CH1_OFFSET 0x00b889c0 590 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYA0_CH1_OFFSET 0x00b88ac0 591 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH1_OFFSET 0x00b88b40 592 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH1_OFFSET 0x00b88c00 593 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH1_OFFSET 0x00b88c40 594 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH1_OFFSET 0x00b88c80 595 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH1_OFFSET 0x00b88cc0 596 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH1_OFFSET 0x00b88d00 597 #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH1_OFFSET 0x00b88e00 598 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH2_OFFSET 0x00b89000 599 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH2_OFFSET 0x00b89100 600 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH2_OFFSET 0x00b89180 601 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA0_CH2_OFFSET 0x00b891c0 602 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYA0_CH2_OFFSET 0x00b892c0 603 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH2_OFFSET 0x00b89340 604 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH2_OFFSET 0x00b89400 605 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH2_OFFSET 0x00b89440 606 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH2_OFFSET 0x00b89480 607 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH2_OFFSET 0x00b894c0 608 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH2_OFFSET 0x00b89500 609 #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH2_OFFSET 0x00b89600 610 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH3_OFFSET 0x00b89800 611 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH3_OFFSET 0x00b89900 612 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH3_OFFSET 0x00b89980 613 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA0_CH3_OFFSET 0x00b899c0 614 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYA0_CH3_OFFSET 0x00b89ac0 615 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH3_OFFSET 0x00b89b40 616 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH3_OFFSET 0x00b89c00 617 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH3_OFFSET 0x00b89c40 618 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH3_OFFSET 0x00b89c80 619 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH3_OFFSET 0x00b89cc0 620 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH3_OFFSET 0x00b89d00 621 #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH3_OFFSET 0x00b89e00 622 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH0_OFFSET 0x00b8a000 623 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH0_OFFSET 0x00b8a100 624 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH0_OFFSET 0x00b8a180 625 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA1_CH0_OFFSET 0x00b8a1c0 626 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYA1_CH0_OFFSET 0x00b8a2c0 627 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH0_OFFSET 0x00b8a340 628 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH0_OFFSET 0x00b8a400 629 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH0_OFFSET 0x00b8a440 630 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH0_OFFSET 0x00b8a480 631 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH0_OFFSET 0x00b8a4c0 632 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH0_OFFSET 0x00b8a500 633 #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH0_OFFSET 0x00b8a600 634 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH1_OFFSET 0x00b8a800 635 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH1_OFFSET 0x00b8a900 636 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH1_OFFSET 0x00b8a980 637 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA1_CH1_OFFSET 0x00b8a9c0 638 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYA1_CH1_OFFSET 0x00b8aac0 639 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH1_OFFSET 0x00b8ab40 640 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH1_OFFSET 0x00b8ac00 641 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH1_OFFSET 0x00b8ac40 642 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH1_OFFSET 0x00b8ac80 643 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH1_OFFSET 0x00b8acc0 644 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH1_OFFSET 0x00b8ad00 645 #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH1_OFFSET 0x00b8ae00 646 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH2_OFFSET 0x00b8b000 647 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH2_OFFSET 0x00b8b100 648 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH2_OFFSET 0x00b8b180 649 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA1_CH2_OFFSET 0x00b8b1c0 650 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYA1_CH2_OFFSET 0x00b8b2c0 651 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH2_OFFSET 0x00b8b340 652 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH2_OFFSET 0x00b8b400 653 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH2_OFFSET 0x00b8b440 654 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH2_OFFSET 0x00b8b480 655 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH2_OFFSET 0x00b8b4c0 656 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH2_OFFSET 0x00b8b500 657 #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH2_OFFSET 0x00b8b600 658 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH3_OFFSET 0x00b8b800 659 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH3_OFFSET 0x00b8b900 660 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH3_OFFSET 0x00b8b980 661 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA1_CH3_OFFSET 0x00b8b9c0 662 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYA1_CH3_OFFSET 0x00b8bac0 663 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH3_OFFSET 0x00b8bb40 664 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH3_OFFSET 0x00b8bc00 665 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH3_OFFSET 0x00b8bc40 666 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH3_OFFSET 0x00b8bc80 667 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH3_OFFSET 0x00b8bcc0 668 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH3_OFFSET 0x00b8bd00 669 #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH3_OFFSET 0x00b8be00 670 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH0_OFFSET 0x00b8c000 671 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH0_OFFSET 0x00b8c100 672 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH0_OFFSET 0x00b8c180 673 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYB_CH0_OFFSET 0x00b8c1c0 674 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYB_CH0_OFFSET 0x00b8c2c0 675 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH0_OFFSET 0x00b8c340 676 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH0_OFFSET 0x00b8c400 677 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH0_OFFSET 0x00b8c440 678 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH0_OFFSET 0x00b8c480 679 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH0_OFFSET 0x00b8c4c0 680 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH0_OFFSET 0x00b8c500 681 #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH0_OFFSET 0x00b8c600 682 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH1_OFFSET 0x00b8c800 683 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH1_OFFSET 0x00b8c900 684 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH1_OFFSET 0x00b8c980 685 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYB_CH1_OFFSET 0x00b8c9c0 686 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYB_CH1_OFFSET 0x00b8cac0 687 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH1_OFFSET 0x00b8cb40 688 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH1_OFFSET 0x00b8cc00 689 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH1_OFFSET 0x00b8cc40 690 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH1_OFFSET 0x00b8cc80 691 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH1_OFFSET 0x00b8ccc0 692 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH1_OFFSET 0x00b8cd00 693 #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH1_OFFSET 0x00b8ce00 694 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH2_OFFSET 0x00b8d000 695 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH2_OFFSET 0x00b8d100 696 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH2_OFFSET 0x00b8d180 697 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYB_CH2_OFFSET 0x00b8d1c0 698 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYB_CH2_OFFSET 0x00b8d2c0 699 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH2_OFFSET 0x00b8d340 700 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH2_OFFSET 0x00b8d400 701 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH2_OFFSET 0x00b8d440 702 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH2_OFFSET 0x00b8d480 703 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH2_OFFSET 0x00b8d4c0 704 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH2_OFFSET 0x00b8d500 705 #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH2_OFFSET 0x00b8d600 706 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH3_OFFSET 0x00b8d800 707 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH3_OFFSET 0x00b8d900 708 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH3_OFFSET 0x00b8d980 709 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYB_CH3_OFFSET 0x00b8d9c0 710 #define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYB_CH3_OFFSET 0x00b8dac0 711 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH3_OFFSET 0x00b8db40 712 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH3_OFFSET 0x00b8dc00 713 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH3_OFFSET 0x00b8dc40 714 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH3_OFFSET 0x00b8dc80 715 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH3_OFFSET 0x00b8dcc0 716 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH3_OFFSET 0x00b8dd00 717 #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH3_OFFSET 0x00b8de00 718 #define SEQ_WCSS_DBG_OFFSET 0x00b90000 719 #define SEQ_WCSS_DBG_ROM_WCSS_DBG_DAPROM_OFFSET 0x00b90000 720 #define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000 721 #define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000 722 #define SEQ_WCSS_DBG_CTIDBG_QC_CTI_24T_8CH_OFFSET 0x00b94000 723 #define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000 724 #define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000 725 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET 0x00b98000 726 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00b98280 727 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00b98000 728 #define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET 0x00b99000 729 #define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00b99280 730 #define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00b99000 731 #define SEQ_WCSS_DBG_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET 0x00b9a000 732 #define SEQ_WCSS_DBG_FUN_CXATBFUNNEL_128W8SP_OFFSET 0x00b9b000 733 #define SEQ_WCSS_DBG_TMC_CXTMC_F128W8K_OFFSET 0x00b9c000 734 #define SEQ_WCSS_DBG_UMAC_NOC_UMAC_NOC_OFFSET 0x00ba0000 735 #define SEQ_WCSS_DBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bb0000 736 #define SEQ_WCSS_DBG_PHYA_CTI_QC_CTI_8T_8CH_OFFSET 0x00bb1000 737 #define SEQ_WCSS_DBG_PHYA_NOC_PHYA_NOC_OFFSET 0x00bb6000 738 #define SEQ_WCSS_DBG_PHYA_CPU0_M3_AHB_AP_OFFSET 0x00bbe000 739 #define SEQ_WCSS_DBG_PHYA_CPU1_M3_AHB_AP_OFFSET 0x00bbf000 740 #define SEQ_WCSS_DBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc0000 741 #define SEQ_WCSS_DBG_PHYB_CTI_QC_CTI_8T_8CH_OFFSET 0x00bc1000 742 #define SEQ_WCSS_DBG_PHYB_NOC_PHYB_NOC_OFFSET 0x00bc6000 743 #define SEQ_WCSS_DBG_PHYB_CPU0_M3_AHB_AP_OFFSET 0x00bce000 744 #define SEQ_WCSS_DBG_UMAC_CPU_M3_AHB_AP_OFFSET 0x00bf0000 745 #define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00bf1000 746 #define SEQ_WCSS_RET_AHB_OFFSET 0x00c10000 747 #define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00c20000 748 #define SEQ_WCSS_CC_OFFSET 0x00c30000 749 #define SEQ_WCSS_ACMT_OFFSET 0x00c40000 750 #define SEQ_WCSS_WRAPPER_ACMT_OFFSET 0x00c60000 751 #define SEQ_WCSS_Q6SS_PUBCSR_OFFSET 0x00d00000 752 #define SEQ_WCSS_Q6SS_PUBCSR_QDSP6SS_PUB_OFFSET 0x00d00000 753 #define SEQ_WCSS_Q6SS_PRIVCSR_OFFSET 0x00d80000 754 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_CSR_OFFSET 0x00d80000 755 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_OFFSET 0x00d90000 756 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_QTMR_AC_OFFSET 0x00da0000 757 #define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F0_OFFSET 0x00da1000 758 #define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F1_OFFSET 0x00da2000 759 #define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F2_OFFSET 0x00da3000 760 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_OFFSET 0x00db0000 761 762 763 /////////////////////////////////////////////////////////////////////////////////////////////// 764 // Instance Relative Offsets from Block mpss_top 765 /////////////////////////////////////////////////////////////////////////////////////////////// 766 767 #define SEQ_MPSS_TOP_SEG0PDMEM_WFAX_PCSS_PDMEM_OFFSET 0x00000000 768 #define SEQ_MPSS_TOP_SEG0_WFAX_PCSS_OFFSET 0x00080000 769 #define SEQ_MPSS_TOP_SEG0_WFAX_PCSS_DUAL_TIMER_OFFSET 0x00081800 770 #define SEQ_MPSS_TOP_SEG0_WFAX_PCSS_WATCHDOG_OFFSET 0x00081c00 771 772 773 /////////////////////////////////////////////////////////////////////////////////////////////// 774 // Instance Relative Offsets from Block wfax_top 775 /////////////////////////////////////////////////////////////////////////////////////////////// 776 777 #define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00000000 778 #define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET 0x00080000 779 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00080400 780 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00080800 781 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00080c00 782 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00081000 783 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00081400 784 #define SEQ_WFAX_TOP_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00081800 785 #define SEQ_WFAX_TOP_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00081c00 786 #define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00084000 787 #define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x00088000 788 #define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00100000 789 #define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x00120000 790 #define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x00128000 791 #define SEQ_WFAX_TOP_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00130000 792 #define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x001a0000 793 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET 0x001c0000 794 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_DIG_OFFSET 0x001c0000 795 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_DIG_RFA_TLMM_OFFSET 0x001c0000 796 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x001c8000 797 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x001d4000 798 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x001d4000 799 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4300 800 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4800 801 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000 802 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040 803 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d6080 804 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x001d60c0 805 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x001d6100 806 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x001d6140 807 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x001d6200 808 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x001d6800 809 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x001d6840 810 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x001d6880 811 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x001d68c0 812 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6900 813 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d6940 814 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x001d6a00 815 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_DRM_REG_OFFSET 0x001d7c00 816 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x001e0000 817 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x001e0000 818 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x001e0400 819 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x001e0800 820 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH0_OFFSET 0x001e1000 821 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH0_OFFSET 0x001e1180 822 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH0_OFFSET 0x001e1300 823 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH0_OFFSET 0x001e1480 824 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x001e2000 825 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH0_OFFSET 0x001e4000 826 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x001e8000 827 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x001e8400 828 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x001e8800 829 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH1_OFFSET 0x001e9000 830 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH1_OFFSET 0x001e9180 831 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH1_OFFSET 0x001e9300 832 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH1_OFFSET 0x001e9480 833 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x001ea000 834 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH1_OFFSET 0x001ec000 835 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x001f0000 836 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x001f0400 837 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x001f0800 838 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH2_OFFSET 0x001f1000 839 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH2_OFFSET 0x001f1180 840 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH2_OFFSET 0x001f1300 841 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH2_OFFSET 0x001f1480 842 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x001f2000 843 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH2_OFFSET 0x001f4000 844 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x001f8000 845 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x001f8400 846 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x001f8800 847 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH3_OFFSET 0x001f9000 848 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH3_OFFSET 0x001f9180 849 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH3_OFFSET 0x001f9300 850 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH3_OFFSET 0x001f9480 851 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x001fa000 852 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH3_OFFSET 0x001fc000 853 854 855 /////////////////////////////////////////////////////////////////////////////////////////////// 856 // Instance Relative Offsets from Block iron2g 857 /////////////////////////////////////////////////////////////////////////////////////////////// 858 859 #define SEQ_IRON2G_RFA_DIG_OFFSET 0x00000000 860 #define SEQ_IRON2G_RFA_DIG_RFA_TLMM_OFFSET 0x00000000 861 #define SEQ_IRON2G_RFA_DIG_SYSCTRL_OFFSET 0x00008000 862 #define SEQ_IRON2G_RFA_CMN_OFFSET 0x00014000 863 #define SEQ_IRON2G_RFA_CMN_AON_OFFSET 0x00014000 864 #define SEQ_IRON2G_RFA_CMN_RFFE_M_OFFSET 0x00014300 865 #define SEQ_IRON2G_RFA_CMN_CLKGEN_OFFSET 0x00014800 866 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016000 867 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016040 868 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016080 869 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x000160c0 870 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016100 871 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x00016140 872 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00016200 873 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00016800 874 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00016840 875 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00016880 876 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x000168c0 877 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00016900 878 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00016940 879 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00016a00 880 #define SEQ_IRON2G_RFA_CMN_DRM_REG_OFFSET 0x00017c00 881 #define SEQ_IRON2G_RFA_WL_OFFSET 0x00020000 882 #define SEQ_IRON2G_RFA_WL_WL_MC_CH0_OFFSET 0x00020000 883 #define SEQ_IRON2G_RFA_WL_WL_RXBB_CH0_OFFSET 0x00020400 884 #define SEQ_IRON2G_RFA_WL_WL_TXBB_CH0_OFFSET 0x00020800 885 #define SEQ_IRON2G_RFA_WL_WL_RXFE2_CH0_OFFSET 0x00021000 886 #define SEQ_IRON2G_RFA_WL_WL_RXFE5_CH0_OFFSET 0x00021180 887 #define SEQ_IRON2G_RFA_WL_WL_TXFE2_CH0_OFFSET 0x00021300 888 #define SEQ_IRON2G_RFA_WL_WL_TXFE5_CH0_OFFSET 0x00021480 889 #define SEQ_IRON2G_RFA_WL_WL_TPC_CH0_OFFSET 0x00022000 890 #define SEQ_IRON2G_RFA_WL_WL_MEM_CH0_OFFSET 0x00024000 891 #define SEQ_IRON2G_RFA_WL_WL_MC_CH1_OFFSET 0x00028000 892 #define SEQ_IRON2G_RFA_WL_WL_RXBB_CH1_OFFSET 0x00028400 893 #define SEQ_IRON2G_RFA_WL_WL_TXBB_CH1_OFFSET 0x00028800 894 #define SEQ_IRON2G_RFA_WL_WL_RXFE2_CH1_OFFSET 0x00029000 895 #define SEQ_IRON2G_RFA_WL_WL_RXFE5_CH1_OFFSET 0x00029180 896 #define SEQ_IRON2G_RFA_WL_WL_TXFE2_CH1_OFFSET 0x00029300 897 #define SEQ_IRON2G_RFA_WL_WL_TXFE5_CH1_OFFSET 0x00029480 898 #define SEQ_IRON2G_RFA_WL_WL_TPC_CH1_OFFSET 0x0002a000 899 #define SEQ_IRON2G_RFA_WL_WL_MEM_CH1_OFFSET 0x0002c000 900 #define SEQ_IRON2G_RFA_WL_WL_MC_CH2_OFFSET 0x00030000 901 #define SEQ_IRON2G_RFA_WL_WL_RXBB_CH2_OFFSET 0x00030400 902 #define SEQ_IRON2G_RFA_WL_WL_TXBB_CH2_OFFSET 0x00030800 903 #define SEQ_IRON2G_RFA_WL_WL_RXFE2_CH2_OFFSET 0x00031000 904 #define SEQ_IRON2G_RFA_WL_WL_RXFE5_CH2_OFFSET 0x00031180 905 #define SEQ_IRON2G_RFA_WL_WL_TXFE2_CH2_OFFSET 0x00031300 906 #define SEQ_IRON2G_RFA_WL_WL_TXFE5_CH2_OFFSET 0x00031480 907 #define SEQ_IRON2G_RFA_WL_WL_TPC_CH2_OFFSET 0x00032000 908 #define SEQ_IRON2G_RFA_WL_WL_MEM_CH2_OFFSET 0x00034000 909 #define SEQ_IRON2G_RFA_WL_WL_MC_CH3_OFFSET 0x00038000 910 #define SEQ_IRON2G_RFA_WL_WL_RXBB_CH3_OFFSET 0x00038400 911 #define SEQ_IRON2G_RFA_WL_WL_TXBB_CH3_OFFSET 0x00038800 912 #define SEQ_IRON2G_RFA_WL_WL_RXFE2_CH3_OFFSET 0x00039000 913 #define SEQ_IRON2G_RFA_WL_WL_RXFE5_CH3_OFFSET 0x00039180 914 #define SEQ_IRON2G_RFA_WL_WL_TXFE2_CH3_OFFSET 0x00039300 915 #define SEQ_IRON2G_RFA_WL_WL_TXFE5_CH3_OFFSET 0x00039480 916 #define SEQ_IRON2G_RFA_WL_WL_TPC_CH3_OFFSET 0x0003a000 917 #define SEQ_IRON2G_RFA_WL_WL_MEM_CH3_OFFSET 0x0003c000 918 919 920 /////////////////////////////////////////////////////////////////////////////////////////////// 921 // Instance Relative Offsets from Block rfa_dig 922 /////////////////////////////////////////////////////////////////////////////////////////////// 923 924 #define SEQ_RFA_DIG_RFA_TLMM_OFFSET 0x00000000 925 #define SEQ_RFA_DIG_SYSCTRL_OFFSET 0x00008000 926 927 928 /////////////////////////////////////////////////////////////////////////////////////////////// 929 // Instance Relative Offsets from Block rfa_cmn 930 /////////////////////////////////////////////////////////////////////////////////////////////// 931 932 #define SEQ_RFA_CMN_AON_OFFSET 0x00000000 933 #define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300 934 #define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000800 935 #define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002000 936 #define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002040 937 #define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002080 938 #define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x000020c0 939 #define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002100 940 #define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x00002140 941 #define SEQ_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00002200 942 #define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00002800 943 #define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00002840 944 #define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00002880 945 #define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x000028c0 946 #define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00002900 947 #define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00002940 948 #define SEQ_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00002a00 949 #define SEQ_RFA_CMN_DRM_REG_OFFSET 0x00003c00 950 951 952 /////////////////////////////////////////////////////////////////////////////////////////////// 953 // Instance Relative Offsets from Block rfa_wl 954 /////////////////////////////////////////////////////////////////////////////////////////////// 955 956 #define SEQ_RFA_WL_WL_MC_CH0_OFFSET 0x00000000 957 #define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET 0x00000400 958 #define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET 0x00000800 959 #define SEQ_RFA_WL_WL_RXFE2_CH0_OFFSET 0x00001000 960 #define SEQ_RFA_WL_WL_RXFE5_CH0_OFFSET 0x00001180 961 #define SEQ_RFA_WL_WL_TXFE2_CH0_OFFSET 0x00001300 962 #define SEQ_RFA_WL_WL_TXFE5_CH0_OFFSET 0x00001480 963 #define SEQ_RFA_WL_WL_TPC_CH0_OFFSET 0x00002000 964 #define SEQ_RFA_WL_WL_MEM_CH0_OFFSET 0x00004000 965 #define SEQ_RFA_WL_WL_MC_CH1_OFFSET 0x00008000 966 #define SEQ_RFA_WL_WL_RXBB_CH1_OFFSET 0x00008400 967 #define SEQ_RFA_WL_WL_TXBB_CH1_OFFSET 0x00008800 968 #define SEQ_RFA_WL_WL_RXFE2_CH1_OFFSET 0x00009000 969 #define SEQ_RFA_WL_WL_RXFE5_CH1_OFFSET 0x00009180 970 #define SEQ_RFA_WL_WL_TXFE2_CH1_OFFSET 0x00009300 971 #define SEQ_RFA_WL_WL_TXFE5_CH1_OFFSET 0x00009480 972 #define SEQ_RFA_WL_WL_TPC_CH1_OFFSET 0x0000a000 973 #define SEQ_RFA_WL_WL_MEM_CH1_OFFSET 0x0000c000 974 #define SEQ_RFA_WL_WL_MC_CH2_OFFSET 0x00010000 975 #define SEQ_RFA_WL_WL_RXBB_CH2_OFFSET 0x00010400 976 #define SEQ_RFA_WL_WL_TXBB_CH2_OFFSET 0x00010800 977 #define SEQ_RFA_WL_WL_RXFE2_CH2_OFFSET 0x00011000 978 #define SEQ_RFA_WL_WL_RXFE5_CH2_OFFSET 0x00011180 979 #define SEQ_RFA_WL_WL_TXFE2_CH2_OFFSET 0x00011300 980 #define SEQ_RFA_WL_WL_TXFE5_CH2_OFFSET 0x00011480 981 #define SEQ_RFA_WL_WL_TPC_CH2_OFFSET 0x00012000 982 #define SEQ_RFA_WL_WL_MEM_CH2_OFFSET 0x00014000 983 #define SEQ_RFA_WL_WL_MC_CH3_OFFSET 0x00018000 984 #define SEQ_RFA_WL_WL_RXBB_CH3_OFFSET 0x00018400 985 #define SEQ_RFA_WL_WL_TXBB_CH3_OFFSET 0x00018800 986 #define SEQ_RFA_WL_WL_RXFE2_CH3_OFFSET 0x00019000 987 #define SEQ_RFA_WL_WL_RXFE5_CH3_OFFSET 0x00019180 988 #define SEQ_RFA_WL_WL_TXFE2_CH3_OFFSET 0x00019300 989 #define SEQ_RFA_WL_WL_TXFE5_CH3_OFFSET 0x00019480 990 #define SEQ_RFA_WL_WL_TPC_CH3_OFFSET 0x0001a000 991 #define SEQ_RFA_WL_WL_MEM_CH3_OFFSET 0x0001c000 992 993 994 /////////////////////////////////////////////////////////////////////////////////////////////// 995 // Instance Relative Offsets from Block wfax_top_b 996 /////////////////////////////////////////////////////////////////////////////////////////////// 997 998 #define SEQ_WFAX_TOP_B_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00000000 999 #define SEQ_WFAX_TOP_B_WFAX_PCSS_B_REG_MAP_OFFSET 0x00080000 1000 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00080400 1001 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00080800 1002 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00080c00 1003 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00081000 1004 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00081400 1005 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DUAL_TIMER_B_REG_MAP_OFFSET 0x00081800 1006 #define SEQ_WFAX_TOP_B_WFAX_PCSS_WATCHDOG_B_REG_MAP_OFFSET 0x00081c00 1007 #define SEQ_WFAX_TOP_B_WFAX_NOC_B_REG_MAP_OFFSET 0x00084000 1008 #define SEQ_WFAX_TOP_B_WFAX_TXTD_B_REG_MAP_OFFSET 0x00088000 1009 #define SEQ_WFAX_TOP_B_WFAX_TXFD_B_REG_MAP_OFFSET 0x00100000 1010 #define SEQ_WFAX_TOP_B_WFAX_ROBE_B_REG_MAP_OFFSET 0x00120000 1011 #define SEQ_WFAX_TOP_B_WFAX_RXTD_B_REG_MAP_OFFSET 0x00128000 1012 #define SEQ_WFAX_TOP_B_WFAX_DEMFRONT_B_REG_MAP_OFFSET 0x00130000 1013 #define SEQ_WFAX_TOP_B_WFAX_PHYRF_B_REG_MAP_OFFSET 0x001a0000 1014 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_OFFSET 0x001c0000 1015 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OFFSET 0x001c0000 1016 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_RFA_TLMM_OFFSET 0x001c0000 1017 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x001c8000 1018 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x001d4000 1019 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x001d4000 1020 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4300 1021 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4800 1022 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000 1023 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040 1024 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d6080 1025 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x001d60c0 1026 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x001d6100 1027 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x001d6140 1028 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x001d6200 1029 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x001d6800 1030 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x001d6840 1031 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x001d6880 1032 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x001d68c0 1033 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6900 1034 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d6940 1035 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x001d6a00 1036 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_DRM_REG_OFFSET 0x001d7c00 1037 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET 0x001e0000 1038 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x001e0000 1039 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x001e0400 1040 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x001e0800 1041 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH0_OFFSET 0x001e1000 1042 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH0_OFFSET 0x001e1180 1043 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH0_OFFSET 0x001e1300 1044 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH0_OFFSET 0x001e1480 1045 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x001e2000 1046 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH0_OFFSET 0x001e4000 1047 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x001e8000 1048 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x001e8400 1049 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x001e8800 1050 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH1_OFFSET 0x001e9000 1051 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH1_OFFSET 0x001e9180 1052 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH1_OFFSET 0x001e9300 1053 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH1_OFFSET 0x001e9480 1054 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x001ea000 1055 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH1_OFFSET 0x001ec000 1056 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x001f0000 1057 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x001f0400 1058 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x001f0800 1059 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH2_OFFSET 0x001f1000 1060 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH2_OFFSET 0x001f1180 1061 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH2_OFFSET 0x001f1300 1062 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH2_OFFSET 0x001f1480 1063 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x001f2000 1064 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH2_OFFSET 0x001f4000 1065 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x001f8000 1066 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x001f8400 1067 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x001f8800 1068 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH3_OFFSET 0x001f9000 1069 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH3_OFFSET 0x001f9180 1070 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH3_OFFSET 0x001f9300 1071 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH3_OFFSET 0x001f9480 1072 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x001fa000 1073 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH3_OFFSET 0x001fc000 1074 1075 1076 /////////////////////////////////////////////////////////////////////////////////////////////// 1077 // Instance Relative Offsets from Block umac_top_reg 1078 /////////////////////////////////////////////////////////////////////////////////////////////// 1079 1080 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_OFFSET 0x00000000 1081 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000 1082 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000 1083 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000 1084 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000 1085 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000 1086 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000 1087 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000 1088 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000 1089 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000 1090 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000 1091 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000 1092 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000 1093 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000 1094 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000 1095 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000 1096 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000 1097 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000 1098 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000 1099 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000 1100 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000 1101 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000 1102 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000 1103 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000 1104 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000 1105 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000 1106 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000 1107 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000 1108 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000 1109 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000 1110 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000 1111 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000 1112 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000 1113 #define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000 1114 #define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET 0x00034000 1115 #define SEQ_UMAC_TOP_REG_REO_REG_OFFSET 0x00038000 1116 #define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000 1117 #define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000 1118 #define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET 0x00044000 1119 #define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_REG_OFFSET 0x00047000 1120 #define SEQ_UMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0004a000 1121 1122 1123 /////////////////////////////////////////////////////////////////////////////////////////////// 1124 // Instance Relative Offsets from Block wfss_ce_reg 1125 /////////////////////////////////////////////////////////////////////////////////////////////// 1126 1127 #define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000 1128 #define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000 1129 #define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000 1130 #define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000 1131 #define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000 1132 #define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000 1133 #define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000 1134 #define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000 1135 #define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000 1136 #define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000 1137 #define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000 1138 #define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000 1139 #define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000 1140 #define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000 1141 #define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000 1142 #define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000 1143 #define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000 1144 #define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000 1145 #define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000 1146 #define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000 1147 #define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000 1148 #define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000 1149 #define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000 1150 #define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000 1151 #define SEQ_WFSS_CE_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000 1152 1153 1154 /////////////////////////////////////////////////////////////////////////////////////////////// 1155 // Instance Relative Offsets from Block cxc_top_reg 1156 /////////////////////////////////////////////////////////////////////////////////////////////// 1157 1158 #define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000 1159 #define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000 1160 #define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000 1161 #define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000 1162 #define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000 1163 #define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000 1164 1165 1166 /////////////////////////////////////////////////////////////////////////////////////////////// 1167 // Instance Relative Offsets from Block wmac_top_reg 1168 /////////////////////////////////////////////////////////////////////////////////////////////// 1169 1170 #define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000 1171 #define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000 1172 #define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000 1173 #define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000 1174 #define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000 1175 #define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000 1176 #define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000 1177 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000 1178 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000 1179 #define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000 1180 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000 1181 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000 1182 #define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000 1183 #define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000 1184 #define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000 1185 #define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000 1186 #define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000 1187 #define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET 0x00036000 1188 #define SEQ_WMAC_TOP_REG_MAC_LPEC_REG_OFFSET 0x00039000 1189 1190 1191 /////////////////////////////////////////////////////////////////////////////////////////////// 1192 // Instance Relative Offsets from Block zinc_rfa_cmn 1193 /////////////////////////////////////////////////////////////////////////////////////////////// 1194 1195 #define SEQ_ZINC_RFA_CMN_PLL_A_OFFSET 0x00000000 1196 #define SEQ_ZINC_RFA_CMN_BIASCLKS_A_OFFSET 0x00000100 1197 #define SEQ_ZINC_RFA_CMN_PLL_B_OFFSET 0x00002000 1198 #define SEQ_ZINC_RFA_CMN_BIASCLKS_B_OFFSET 0x00002100 1199 #define SEQ_ZINC_RFA_CMN_PHYB_ROOTCLKGEN_OFFSET 0x00004000 1200 #define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH0_OFFSET 0x00008000 1201 #define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH0_OFFSET 0x00008100 1202 #define SEQ_ZINC_RFA_CMN_WL_DAC_PHYA0_CH0_OFFSET 0x00008180 1203 #define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA0_CH0_OFFSET 0x000081c0 1204 #define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYA0_CH0_OFFSET 0x000082c0 1205 #define SEQ_ZINC_RFA_CMN_WL_ADC_PHYA0_CH0_OFFSET 0x00008340 1206 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH0_OFFSET 0x00008400 1207 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH0_OFFSET 0x00008440 1208 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH0_OFFSET 0x00008480 1209 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH0_OFFSET 0x000084c0 1210 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH0_OFFSET 0x00008500 1211 #define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH0_OFFSET 0x00008600 1212 #define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH1_OFFSET 0x00008800 1213 #define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH1_OFFSET 0x00008900 1214 #define SEQ_ZINC_RFA_CMN_WL_DAC_PHYA0_CH1_OFFSET 0x00008980 1215 #define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA0_CH1_OFFSET 0x000089c0 1216 #define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYA0_CH1_OFFSET 0x00008ac0 1217 #define SEQ_ZINC_RFA_CMN_WL_ADC_PHYA0_CH1_OFFSET 0x00008b40 1218 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH1_OFFSET 0x00008c00 1219 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH1_OFFSET 0x00008c40 1220 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH1_OFFSET 0x00008c80 1221 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH1_OFFSET 0x00008cc0 1222 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH1_OFFSET 0x00008d00 1223 #define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH1_OFFSET 0x00008e00 1224 #define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH2_OFFSET 0x00009000 1225 #define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH2_OFFSET 0x00009100 1226 #define SEQ_ZINC_RFA_CMN_WL_DAC_PHYA0_CH2_OFFSET 0x00009180 1227 #define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA0_CH2_OFFSET 0x000091c0 1228 #define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYA0_CH2_OFFSET 0x000092c0 1229 #define SEQ_ZINC_RFA_CMN_WL_ADC_PHYA0_CH2_OFFSET 0x00009340 1230 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH2_OFFSET 0x00009400 1231 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH2_OFFSET 0x00009440 1232 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH2_OFFSET 0x00009480 1233 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH2_OFFSET 0x000094c0 1234 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH2_OFFSET 0x00009500 1235 #define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH2_OFFSET 0x00009600 1236 #define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH3_OFFSET 0x00009800 1237 #define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH3_OFFSET 0x00009900 1238 #define SEQ_ZINC_RFA_CMN_WL_DAC_PHYA0_CH3_OFFSET 0x00009980 1239 #define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA0_CH3_OFFSET 0x000099c0 1240 #define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYA0_CH3_OFFSET 0x00009ac0 1241 #define SEQ_ZINC_RFA_CMN_WL_ADC_PHYA0_CH3_OFFSET 0x00009b40 1242 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH3_OFFSET 0x00009c00 1243 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH3_OFFSET 0x00009c40 1244 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH3_OFFSET 0x00009c80 1245 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH3_OFFSET 0x00009cc0 1246 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH3_OFFSET 0x00009d00 1247 #define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH3_OFFSET 0x00009e00 1248 #define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH0_OFFSET 0x0000a000 1249 #define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH0_OFFSET 0x0000a100 1250 #define SEQ_ZINC_RFA_CMN_WL_DAC_PHYA1_CH0_OFFSET 0x0000a180 1251 #define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA1_CH0_OFFSET 0x0000a1c0 1252 #define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYA1_CH0_OFFSET 0x0000a2c0 1253 #define SEQ_ZINC_RFA_CMN_WL_ADC_PHYA1_CH0_OFFSET 0x0000a340 1254 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH0_OFFSET 0x0000a400 1255 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH0_OFFSET 0x0000a440 1256 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH0_OFFSET 0x0000a480 1257 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH0_OFFSET 0x0000a4c0 1258 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH0_OFFSET 0x0000a500 1259 #define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH0_OFFSET 0x0000a600 1260 #define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH1_OFFSET 0x0000a800 1261 #define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH1_OFFSET 0x0000a900 1262 #define SEQ_ZINC_RFA_CMN_WL_DAC_PHYA1_CH1_OFFSET 0x0000a980 1263 #define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA1_CH1_OFFSET 0x0000a9c0 1264 #define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYA1_CH1_OFFSET 0x0000aac0 1265 #define SEQ_ZINC_RFA_CMN_WL_ADC_PHYA1_CH1_OFFSET 0x0000ab40 1266 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH1_OFFSET 0x0000ac00 1267 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH1_OFFSET 0x0000ac40 1268 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH1_OFFSET 0x0000ac80 1269 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH1_OFFSET 0x0000acc0 1270 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH1_OFFSET 0x0000ad00 1271 #define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH1_OFFSET 0x0000ae00 1272 #define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH2_OFFSET 0x0000b000 1273 #define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH2_OFFSET 0x0000b100 1274 #define SEQ_ZINC_RFA_CMN_WL_DAC_PHYA1_CH2_OFFSET 0x0000b180 1275 #define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA1_CH2_OFFSET 0x0000b1c0 1276 #define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYA1_CH2_OFFSET 0x0000b2c0 1277 #define SEQ_ZINC_RFA_CMN_WL_ADC_PHYA1_CH2_OFFSET 0x0000b340 1278 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH2_OFFSET 0x0000b400 1279 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH2_OFFSET 0x0000b440 1280 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH2_OFFSET 0x0000b480 1281 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH2_OFFSET 0x0000b4c0 1282 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH2_OFFSET 0x0000b500 1283 #define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH2_OFFSET 0x0000b600 1284 #define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH3_OFFSET 0x0000b800 1285 #define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH3_OFFSET 0x0000b900 1286 #define SEQ_ZINC_RFA_CMN_WL_DAC_PHYA1_CH3_OFFSET 0x0000b980 1287 #define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA1_CH3_OFFSET 0x0000b9c0 1288 #define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYA1_CH3_OFFSET 0x0000bac0 1289 #define SEQ_ZINC_RFA_CMN_WL_ADC_PHYA1_CH3_OFFSET 0x0000bb40 1290 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH3_OFFSET 0x0000bc00 1291 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH3_OFFSET 0x0000bc40 1292 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH3_OFFSET 0x0000bc80 1293 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH3_OFFSET 0x0000bcc0 1294 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH3_OFFSET 0x0000bd00 1295 #define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH3_OFFSET 0x0000be00 1296 #define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH0_OFFSET 0x0000c000 1297 #define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYB_CH0_OFFSET 0x0000c100 1298 #define SEQ_ZINC_RFA_CMN_WL_DAC_PHYB_CH0_OFFSET 0x0000c180 1299 #define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYB_CH0_OFFSET 0x0000c1c0 1300 #define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYB_CH0_OFFSET 0x0000c2c0 1301 #define SEQ_ZINC_RFA_CMN_WL_ADC_PHYB_CH0_OFFSET 0x0000c340 1302 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH0_OFFSET 0x0000c400 1303 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH0_OFFSET 0x0000c440 1304 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH0_OFFSET 0x0000c480 1305 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH0_OFFSET 0x0000c4c0 1306 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH0_OFFSET 0x0000c500 1307 #define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH0_OFFSET 0x0000c600 1308 #define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH1_OFFSET 0x0000c800 1309 #define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYB_CH1_OFFSET 0x0000c900 1310 #define SEQ_ZINC_RFA_CMN_WL_DAC_PHYB_CH1_OFFSET 0x0000c980 1311 #define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYB_CH1_OFFSET 0x0000c9c0 1312 #define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYB_CH1_OFFSET 0x0000cac0 1313 #define SEQ_ZINC_RFA_CMN_WL_ADC_PHYB_CH1_OFFSET 0x0000cb40 1314 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH1_OFFSET 0x0000cc00 1315 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH1_OFFSET 0x0000cc40 1316 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH1_OFFSET 0x0000cc80 1317 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH1_OFFSET 0x0000ccc0 1318 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH1_OFFSET 0x0000cd00 1319 #define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH1_OFFSET 0x0000ce00 1320 #define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH2_OFFSET 0x0000d000 1321 #define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYB_CH2_OFFSET 0x0000d100 1322 #define SEQ_ZINC_RFA_CMN_WL_DAC_PHYB_CH2_OFFSET 0x0000d180 1323 #define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYB_CH2_OFFSET 0x0000d1c0 1324 #define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYB_CH2_OFFSET 0x0000d2c0 1325 #define SEQ_ZINC_RFA_CMN_WL_ADC_PHYB_CH2_OFFSET 0x0000d340 1326 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH2_OFFSET 0x0000d400 1327 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH2_OFFSET 0x0000d440 1328 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH2_OFFSET 0x0000d480 1329 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH2_OFFSET 0x0000d4c0 1330 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH2_OFFSET 0x0000d500 1331 #define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH2_OFFSET 0x0000d600 1332 #define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH3_OFFSET 0x0000d800 1333 #define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYB_CH3_OFFSET 0x0000d900 1334 #define SEQ_ZINC_RFA_CMN_WL_DAC_PHYB_CH3_OFFSET 0x0000d980 1335 #define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYB_CH3_OFFSET 0x0000d9c0 1336 #define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYB_CH3_OFFSET 0x0000dac0 1337 #define SEQ_ZINC_RFA_CMN_WL_ADC_PHYB_CH3_OFFSET 0x0000db40 1338 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH3_OFFSET 0x0000dc00 1339 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH3_OFFSET 0x0000dc40 1340 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH3_OFFSET 0x0000dc80 1341 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH3_OFFSET 0x0000dcc0 1342 #define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH3_OFFSET 0x0000dd00 1343 #define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH3_OFFSET 0x0000de00 1344 1345 1346 /////////////////////////////////////////////////////////////////////////////////////////////// 1347 // Instance Relative Offsets from Block wcssdbg 1348 /////////////////////////////////////////////////////////////////////////////////////////////// 1349 1350 #define SEQ_WCSSDBG_ROM_WCSS_DBG_DAPROM_OFFSET 0x00000000 1351 #define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET 0x00001000 1352 #define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET 0x00002000 1353 #define SEQ_WCSSDBG_CTIDBG_QC_CTI_24T_8CH_OFFSET 0x00004000 1354 #define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000 1355 #define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000 1356 #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET 0x00008000 1357 #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00008280 1358 #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00008000 1359 #define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET 0x00009000 1360 #define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00009280 1361 #define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00009000 1362 #define SEQ_WCSSDBG_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET 0x0000a000 1363 #define SEQ_WCSSDBG_FUN_CXATBFUNNEL_128W8SP_OFFSET 0x0000b000 1364 #define SEQ_WCSSDBG_TMC_CXTMC_F128W8K_OFFSET 0x0000c000 1365 #define SEQ_WCSSDBG_UMAC_NOC_UMAC_NOC_OFFSET 0x00010000 1366 #define SEQ_WCSSDBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00020000 1367 #define SEQ_WCSSDBG_PHYA_CTI_QC_CTI_8T_8CH_OFFSET 0x00021000 1368 #define SEQ_WCSSDBG_PHYA_NOC_PHYA_NOC_OFFSET 0x00026000 1369 #define SEQ_WCSSDBG_PHYA_CPU0_M3_AHB_AP_OFFSET 0x0002e000 1370 #define SEQ_WCSSDBG_PHYA_CPU1_M3_AHB_AP_OFFSET 0x0002f000 1371 #define SEQ_WCSSDBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00030000 1372 #define SEQ_WCSSDBG_PHYB_CTI_QC_CTI_8T_8CH_OFFSET 0x00031000 1373 #define SEQ_WCSSDBG_PHYB_NOC_PHYB_NOC_OFFSET 0x00036000 1374 #define SEQ_WCSSDBG_PHYB_CPU0_M3_AHB_AP_OFFSET 0x0003e000 1375 #define SEQ_WCSSDBG_UMAC_CPU_M3_AHB_AP_OFFSET 0x00060000 1376 #define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET 0x00061000 1377 1378 1379 /////////////////////////////////////////////////////////////////////////////////////////////// 1380 // Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7 1381 /////////////////////////////////////////////////////////////////////////////////////////////// 1382 1383 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280 1384 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000 1385 1386 1387 /////////////////////////////////////////////////////////////////////////////////////////////// 1388 // Instance Relative Offsets from Block tpdm_atb32_dsb64_csf49237bd 1389 /////////////////////////////////////////////////////////////////////////////////////////////// 1390 1391 #define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00000280 1392 #define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00000000 1393 1394 1395 /////////////////////////////////////////////////////////////////////////////////////////////// 1396 // Instance Relative Offsets from Block qdsp6ss_public 1397 /////////////////////////////////////////////////////////////////////////////////////////////// 1398 1399 #define SEQ_QDSP6SS_PUBLIC_QDSP6SS_PUB_OFFSET 0x00000000 1400 1401 1402 /////////////////////////////////////////////////////////////////////////////////////////////// 1403 // Instance Relative Offsets from Block qdsp6ss_private 1404 /////////////////////////////////////////////////////////////////////////////////////////////// 1405 1406 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_CSR_OFFSET 0x00000000 1407 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_L2VIC_OFFSET 0x00010000 1408 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00020000 1409 #define SEQ_QDSP6SS_PRIVATE_QTMR_F0_OFFSET 0x00021000 1410 #define SEQ_QDSP6SS_PRIVATE_QTMR_F1_OFFSET 0x00022000 1411 #define SEQ_QDSP6SS_PRIVATE_QTMR_F2_OFFSET 0x00023000 1412 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_SAW2_OFFSET 0x00030000 1413 1414 1415 #endif 1416 1417