1 /* 2 * Copyright (c) 2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /////////////////////////////////////////////////////////////////////////////////////////////// 20 // 21 // wcss_seq_hwiobase.h : automatically generated by Autoseq 3.8 3/26/2019 22 // User Name:c_landav 23 // 24 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 25 // 26 /////////////////////////////////////////////////////////////////////////////////////////////// 27 28 #ifndef __WCSS_SEQ_BASE_H__ 29 #define __WCSS_SEQ_BASE_H__ 30 31 #ifdef SCALE_INCLUDES 32 #include "HALhwio.h" 33 #else 34 #include "msmhwio.h" 35 #endif 36 37 #ifndef SOC_WCSS_BASE_ADDR 38 #if defined(WCSS_BASE) 39 #if ( WCSS_BASE != 0xC000000 ) 40 #error WCSS_BASE incorrectly redefined! 41 #endif 42 #endif 43 #define SOC_WCSS_BASE_ADDR 0x000000 44 #else 45 #endif 46 47 /////////////////////////////////////////////////////////////////////////////////////////////// 48 // Instance Relative Offsets from Block wcss 49 /////////////////////////////////////////////////////////////////////////////////////////////// 50 51 #define SEQ_WCSS_ECAHB_OFFSET 0x00008400 52 #define SEQ_WCSS_ECAHB_TSLV_OFFSET 0x00009000 53 #define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000 54 #define SEQ_WCSS_PHYA_OFFSET 0x00300000 55 #define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00300000 56 #define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET 0x00380000 57 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00380400 58 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00380800 59 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00380c00 60 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00381000 61 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00381400 62 #define SEQ_WCSS_PHYA_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00381800 63 #define SEQ_WCSS_PHYA_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00381c00 64 #define SEQ_WCSS_PHYA_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00382c00 65 #define SEQ_WCSS_PHYA_WFAX_PCSS_XDMAC6_REG_MAP_OFFSET 0x00383000 66 #define SEQ_WCSS_PHYA_WFAX_NOC_REG_MAP_OFFSET 0x00388000 67 #define SEQ_WCSS_PHYA_WFAX_TXFD_REG_MAP_OFFSET 0x00390000 68 #define SEQ_WCSS_PHYA_WFAX_RXTD_REG_MAP_OFFSET 0x003a0000 69 #define SEQ_WCSS_PHYA_WFAX_TXTD_REG_MAP_OFFSET 0x003b0000 70 #define SEQ_WCSS_PHYA_WFAX_TXBF_REG_MAP_OFFSET 0x003c0000 71 #define SEQ_WCSS_PHYA_WFAX_DEMFRONT_0_REG_MAP_OFFSET 0x00400000 72 #define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET 0x00480000 73 #define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET 0x004b0000 74 #define SEQ_WCSS_PHYA_WFAX_DEMFRONT_1_REG_MAP_OFFSET 0x00500000 75 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_OFFSET 0x005c0000 76 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET 0x005c0000 77 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET 0x005cf000 78 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET 0x005cf400 79 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x005cf800 80 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET 0x005cfc00 81 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET 0x005c0000 82 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TRC_OFFSET 0x005c0200 83 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_LTE_REG_OFFSET 0x005c5000 84 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET 0x005d1000 85 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x005c7000 86 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x005c9b00 87 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x005c7000 88 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x005cb000 89 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x005d4000 90 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x005d4000 91 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x005d4240 92 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x005d42c0 93 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x005d4300 94 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x005d4400 95 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x005d4480 96 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x005d4800 97 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x005d4c00 98 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_OFFSET 0x005d5000 99 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x005d5400 100 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6000 101 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6040 102 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d6100 103 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d6140 104 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6180 105 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d61c0 106 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x005d6280 107 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x005d6800 108 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x005d6840 109 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x005d6900 110 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x005d6940 111 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d6980 112 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d69c0 113 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x005d6a80 114 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_BS_OFFSET 0x005d7000 115 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_CLBS_OFFSET 0x005d7040 116 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_BIST_OFFSET 0x005d7100 117 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_PC_OFFSET 0x005d7140 118 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x005d7180 119 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x005d71c0 120 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x005d7280 121 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x005d7c00 122 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET 0x005da000 123 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x005dc000 124 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET 0x005dc000 125 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x005de800 126 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET 0x005de980 127 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x005de9c0 128 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET 0x005deac0 129 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TX_OFFSET 0x005dec00 130 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RX_CH0_OFFSET 0x005df000 131 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RX_CH1_OFFSET 0x005df200 132 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x005dfc00 133 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x005dfc40 134 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x005dfc80 135 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x005dfcc0 136 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x005e0000 137 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x005e0000 138 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x005e0400 139 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x005e0800 140 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x005e1000 141 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x005e1300 142 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x005e2000 143 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x005e2400 144 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x005e2580 145 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET 0x005e25c0 146 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET 0x005e26c0 147 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_2G_CH0_OFFSET 0x005e2734 148 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x005e2740 149 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH0_OFFSET 0x005e2800 150 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH0_OFFSET 0x005e2840 151 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH0_OFFSET 0x005e2880 152 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH0_OFFSET 0x005e28c0 153 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH0_OFFSET 0x005e2900 154 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH0_OFFSET 0x005e299c 155 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x005e4000 156 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x005e8000 157 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x005e8400 158 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x005e8800 159 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x005e9000 160 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x005e9300 161 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x005ea000 162 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x005ea400 163 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x005ea580 164 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET 0x005ea5c0 165 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET 0x005ea6c0 166 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_5G_CH0_OFFSET 0x005ea734 167 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x005ea740 168 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH0_OFFSET 0x005ea800 169 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH0_OFFSET 0x005ea840 170 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH0_OFFSET 0x005ea880 171 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH0_OFFSET 0x005ea8c0 172 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH0_OFFSET 0x005ea900 173 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_5G_CH0_OFFSET 0x005ea99c 174 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x005ec000 175 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x005f0000 176 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x005f0400 177 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x005f0800 178 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x005f1000 179 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x005f1300 180 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x005f2000 181 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x005f2400 182 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x005f2580 183 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x005f25c0 184 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x005f26c0 185 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_2G_CH1_OFFSET 0x005f2734 186 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x005f2740 187 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH1_OFFSET 0x005f2800 188 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH1_OFFSET 0x005f2840 189 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH1_OFFSET 0x005f2880 190 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x005f28c0 191 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x005f2900 192 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x005f299c 193 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x005f4000 194 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x005f8000 195 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x005f8400 196 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x005f8800 197 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x005f9000 198 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x005f9300 199 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x005fa000 200 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x005fa400 201 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x005fa580 202 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET 0x005fa5c0 203 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET 0x005fa6c0 204 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_5G_CH1_OFFSET 0x005fa734 205 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x005fa740 206 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH1_OFFSET 0x005fa800 207 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH1_OFFSET 0x005fa840 208 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH1_OFFSET 0x005fa880 209 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH1_OFFSET 0x005fa8c0 210 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH1_OFFSET 0x005fa900 211 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_5G_CH1_OFFSET 0x005fa99c 212 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x005fc000 213 #define SEQ_WCSS_PHYB_OFFSET 0x00600000 214 #define SEQ_WCSS_PHYB_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00600000 215 #define SEQ_WCSS_PHYB_WFAX_PCSS_B_REG_MAP_OFFSET 0x00680000 216 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00680400 217 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00680800 218 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00680c00 219 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00681000 220 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00681400 221 #define SEQ_WCSS_PHYB_WFAX_PCSS_DUAL_TIMER_B_REG_MAP_OFFSET 0x00681800 222 #define SEQ_WCSS_PHYB_WFAX_PCSS_WATCHDOG_B_REG_MAP_OFFSET 0x00681c00 223 #define SEQ_WCSS_PHYB_WFAX_PCSS_XDMAC5_B_REG_MAP_OFFSET 0x00682c00 224 #define SEQ_WCSS_PHYB_WFAX_PCSS_XDMAC6_B_REG_MAP_OFFSET 0x00683000 225 #define SEQ_WCSS_PHYB_WFAX_NOC_B_REG_MAP_OFFSET 0x00688000 226 #define SEQ_WCSS_PHYB_WFAX_TXFD_B_REG_MAP_OFFSET 0x00690000 227 #define SEQ_WCSS_PHYB_WFAX_RXTD_B_REG_MAP_OFFSET 0x006a0000 228 #define SEQ_WCSS_PHYB_WFAX_TXTD_B_REG_MAP_OFFSET 0x006b0000 229 #define SEQ_WCSS_PHYB_WFAX_TXBF_B_REG_MAP_OFFSET 0x006c0000 230 #define SEQ_WCSS_PHYB_WFAX_DEMFRONT_NPRB_B_REG_MAP_OFFSET 0x00700000 231 #define SEQ_WCSS_PHYB_WFAX_PHYRF_B_REG_MAP_OFFSET 0x00780000 232 #define SEQ_WCSS_PHYB_WFAX_ROBE_B_REG_MAP_OFFSET 0x007b0000 233 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_OFFSET 0x007c0000 234 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET 0x007c0000 235 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET 0x007cf000 236 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET 0x007cf400 237 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x007cf800 238 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET 0x007cfc00 239 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET 0x007c0000 240 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TRC_OFFSET 0x007c0200 241 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_LTE_REG_OFFSET 0x007c5000 242 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET 0x007d1000 243 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x007c7000 244 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x007c9b00 245 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x007c7000 246 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x007cb000 247 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x007d4000 248 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x007d4000 249 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x007d4240 250 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x007d42c0 251 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x007d4300 252 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x007d4400 253 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x007d4480 254 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x007d4800 255 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x007d4c00 256 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_OFFSET 0x007d5000 257 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x007d5400 258 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x007d6000 259 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x007d6040 260 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x007d6100 261 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x007d6140 262 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x007d6180 263 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x007d61c0 264 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x007d6280 265 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x007d6800 266 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x007d6840 267 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x007d6900 268 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x007d6940 269 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x007d6980 270 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x007d69c0 271 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x007d6a80 272 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_BS_OFFSET 0x007d7000 273 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_CLBS_OFFSET 0x007d7040 274 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_BIST_OFFSET 0x007d7100 275 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_PC_OFFSET 0x007d7140 276 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x007d7180 277 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x007d71c0 278 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x007d7280 279 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x007d7c00 280 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET 0x007da000 281 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x007dc000 282 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET 0x007dc000 283 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x007de800 284 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET 0x007de980 285 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x007de9c0 286 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET 0x007deac0 287 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TX_OFFSET 0x007dec00 288 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RX_CH0_OFFSET 0x007df000 289 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RX_CH1_OFFSET 0x007df200 290 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x007dfc00 291 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x007dfc40 292 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x007dfc80 293 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x007dfcc0 294 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x007e0000 295 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x007e0000 296 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x007e0400 297 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x007e0800 298 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x007e1000 299 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x007e1300 300 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x007e2000 301 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x007e2400 302 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x007e2580 303 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET 0x007e25c0 304 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET 0x007e26c0 305 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_2G_CH0_OFFSET 0x007e2734 306 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x007e2740 307 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH0_OFFSET 0x007e2800 308 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH0_OFFSET 0x007e2840 309 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH0_OFFSET 0x007e2880 310 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH0_OFFSET 0x007e28c0 311 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH0_OFFSET 0x007e2900 312 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH0_OFFSET 0x007e299c 313 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x007e4000 314 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x007e8000 315 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x007e8400 316 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x007e8800 317 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x007e9000 318 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x007e9300 319 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x007ea000 320 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x007ea400 321 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x007ea580 322 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET 0x007ea5c0 323 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET 0x007ea6c0 324 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_5G_CH0_OFFSET 0x007ea734 325 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x007ea740 326 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH0_OFFSET 0x007ea800 327 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH0_OFFSET 0x007ea840 328 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH0_OFFSET 0x007ea880 329 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH0_OFFSET 0x007ea8c0 330 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH0_OFFSET 0x007ea900 331 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_5G_CH0_OFFSET 0x007ea99c 332 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x007ec000 333 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x007f0000 334 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x007f0400 335 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x007f0800 336 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x007f1000 337 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x007f1300 338 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x007f2000 339 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x007f2400 340 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x007f2580 341 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x007f25c0 342 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x007f26c0 343 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_2G_CH1_OFFSET 0x007f2734 344 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x007f2740 345 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH1_OFFSET 0x007f2800 346 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH1_OFFSET 0x007f2840 347 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH1_OFFSET 0x007f2880 348 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x007f28c0 349 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x007f2900 350 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x007f299c 351 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x007f4000 352 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x007f8000 353 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x007f8400 354 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x007f8800 355 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x007f9000 356 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x007f9300 357 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x007fa000 358 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x007fa400 359 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x007fa580 360 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET 0x007fa5c0 361 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET 0x007fa6c0 362 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_5G_CH1_OFFSET 0x007fa734 363 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x007fa740 364 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH1_OFFSET 0x007fa800 365 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH1_OFFSET 0x007fa840 366 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH1_OFFSET 0x007fa880 367 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH1_OFFSET 0x007fa8c0 368 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH1_OFFSET 0x007fa900 369 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_5G_CH1_OFFSET 0x007fa99c 370 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x007fc000 371 #define SEQ_WCSS_UMAC_OFFSET 0x00a00000 372 #define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000 373 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000 374 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000 375 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000 376 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000 377 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000 378 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000 379 #define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000 380 #define SEQ_WCSS_UMAC_WBM_REG_OFFSET 0x00a34000 381 #define SEQ_WCSS_UMAC_REO_REG_OFFSET 0x00a38000 382 #define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000 383 #define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000 384 #define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET 0x00a44000 385 #define SEQ_WCSS_UMAC_MAC_CMN_PARSER_CE_REG_OFFSET 0x00a47000 386 #define SEQ_WCSS_WMAC0_OFFSET 0x00a80000 387 #define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET 0x00a80000 388 #define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET 0x00a83000 389 #define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET 0x00a86000 390 #define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET 0x00a89000 391 #define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET 0x00a8c000 392 #define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET 0x00a8f000 393 #define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET 0x00a92000 394 #define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET 0x00a95000 395 #define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET 0x00a98000 396 #define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET 0x00a9b000 397 #define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET 0x00a9e000 398 #define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET 0x00aa1000 399 #define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET 0x00aa4000 400 #define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET 0x00aa7000 401 #define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET 0x00aaa000 402 #define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET 0x00ab0000 403 #define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000 404 #define SEQ_WCSS_WMAC1_OFFSET 0x00b00000 405 #define SEQ_WCSS_WMAC1_MAC_PDG_REG_OFFSET 0x00b00000 406 #define SEQ_WCSS_WMAC1_MAC_TXDMA_REG_OFFSET 0x00b03000 407 #define SEQ_WCSS_WMAC1_MAC_RXDMA_REG_OFFSET 0x00b06000 408 #define SEQ_WCSS_WMAC1_MAC_MCMN_REG_OFFSET 0x00b09000 409 #define SEQ_WCSS_WMAC1_MAC_RXPCU_REG_OFFSET 0x00b0c000 410 #define SEQ_WCSS_WMAC1_MAC_TXPCU_REG_OFFSET 0x00b0f000 411 #define SEQ_WCSS_WMAC1_MAC_AMPI_REG_OFFSET 0x00b12000 412 #define SEQ_WCSS_WMAC1_MAC_RXOLE_REG_OFFSET 0x00b15000 413 #define SEQ_WCSS_WMAC1_MAC_RXOLE_PARSER_REG_OFFSET 0x00b18000 414 #define SEQ_WCSS_WMAC1_MAC_CCE_REG_OFFSET 0x00b1b000 415 #define SEQ_WCSS_WMAC1_MAC_TXOLE_REG_OFFSET 0x00b1e000 416 #define SEQ_WCSS_WMAC1_MAC_TXOLE_PARSER_REG_OFFSET 0x00b21000 417 #define SEQ_WCSS_WMAC1_MAC_RRI_REG_OFFSET 0x00b24000 418 #define SEQ_WCSS_WMAC1_MAC_CRYPTO_REG_OFFSET 0x00b27000 419 #define SEQ_WCSS_WMAC1_MAC_HWSCH_REG_OFFSET 0x00b2a000 420 #define SEQ_WCSS_WMAC1_MAC_MXI_REG_OFFSET 0x00b30000 421 #define SEQ_WCSS_WMAC1_MAC_SFM_REG_OFFSET 0x00b33000 422 #define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000 423 #define SEQ_WCSS_TOP_CMN_OFFSET 0x00b50000 424 #define SEQ_WCSS_WCMN_CORE_OFFSET 0x00b58000 425 #define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000 426 #define SEQ_WCSS_PMM_TOP_OFFSET 0x00b70000 427 #define SEQ_WCSS_DBG_OFFSET 0x00b90000 428 #define SEQ_WCSS_DBG_WCSS_DBG_DAPROM_OFFSET 0x00b90000 429 #define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000 430 #define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000 431 #define SEQ_WCSS_DBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00b94000 432 #define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000 433 #define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000 434 #define SEQ_WCSS_DBG_EVENT_MACEVENT_OFFSET 0x00bb0000 435 #define SEQ_WCSS_DBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb1000 436 #define SEQ_WCSS_DBG_TLV_MACTLV_OFFSET 0x00bb2000 437 #define SEQ_WCSS_DBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb3000 438 #define SEQ_WCSS_DBG_TBUS_MACTBUS_OFFSET 0x00bb4000 439 #define SEQ_WCSS_DBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb5000 440 #define SEQ_WCSS_DBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00bb6000 441 #define SEQ_WCSS_DBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00bb8000 442 #define SEQ_WCSS_DBG_TPDM_OFFSET 0x00bb9000 443 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00bb9280 444 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00bb9000 445 #define SEQ_WCSS_DBG_TPDA_OFFSET 0x00bba000 446 #define SEQ_WCSS_DBG_CXATBFUNNEL_128W8SP_OFFSET 0x00bbb000 447 #define SEQ_WCSS_DBG_TMC_CXTMC_F128W32K_OFFSET 0x00bbc000 448 #define SEQ_WCSS_DBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbe000 449 #define SEQ_WCSS_DBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbf000 450 #define SEQ_WCSS_DBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00bc0000 451 #define SEQ_WCSS_DBG_TRCCNTRS_OFFSET 0x00bc1000 452 #define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_OFFSET 0x00bc2000 453 #define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00bc2280 454 #define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00bc2000 455 #define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_OFFSET 0x00bc3000 456 #define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00bc3280 457 #define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00bc3000 458 #define SEQ_WCSS_DBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00bc4000 459 #define SEQ_WCSS_DBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00bc5000 460 #define SEQ_WCSS_DBG_PHYADMUX_ATB_DEMUX_OFFSET 0x00bc6000 461 #define SEQ_WCSS_DBG_PHYBDMUX_ATB_DEMUX_OFFSET 0x00bc7000 462 #define SEQ_WCSS_DBG_MISCFUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc8000 463 #define SEQ_WCSS_DBG_UNOC_UMAC_NOC_OFFSET 0x00bd0000 464 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_OFFSET 0x00be0000 465 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00be0000 466 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00be4000 467 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00be5000 468 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00be6000 469 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_ITM_OFFSET 0x00be8000 470 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_DWT_OFFSET 0x00be9000 471 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FPB_OFFSET 0x00bea000 472 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_SCS_OFFSET 0x00beb000 473 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_M3_ETM_OFFSET 0x00bec000 474 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x00bed000 475 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET 0x00bee000 476 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_OFFSET 0x00bf0000 477 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_PHYB_NOC_OFFSET 0x00bf0000 478 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bf4000 479 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00bf5000 480 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00bf6000 481 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_ITM_OFFSET 0x00bf8000 482 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_DWT_OFFSET 0x00bf9000 483 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_FPB_OFFSET 0x00bfa000 484 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_SCS_OFFSET 0x00bfb000 485 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_ETM_OFFSET 0x00bfc000 486 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x00bfd000 487 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_CPU0_M3_AHB_AP_OFFSET 0x00bfe000 488 #define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00c31000 489 #define SEQ_WCSS_RET_AHB_OFFSET 0x00c90000 490 #define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00ca0000 491 #define SEQ_WCSS_CC_OFFSET 0x00cb0000 492 #define SEQ_WCSS_UMAC_ACMT_OFFSET 0x00cc0000 493 #define SEQ_WCSS_Q6SS_WLAN_OFFSET 0x00d00000 494 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_OFFSET 0x00d00000 495 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00d00000 496 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00d00000 497 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00d80000 498 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00d80000 499 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00d90000 500 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00da0000 501 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x00da1000 502 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x00da2000 503 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x00da3000 504 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x00db0000 505 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x00db0000 506 507 508 /////////////////////////////////////////////////////////////////////////////////////////////// 509 // Instance Relative Offsets from Block wfax_top 510 /////////////////////////////////////////////////////////////////////////////////////////////// 511 512 #define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00000000 513 #define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET 0x00080000 514 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00080400 515 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00080800 516 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00080c00 517 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00081000 518 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00081400 519 #define SEQ_WFAX_TOP_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00081800 520 #define SEQ_WFAX_TOP_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00081c00 521 #define SEQ_WFAX_TOP_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00082c00 522 #define SEQ_WFAX_TOP_WFAX_PCSS_XDMAC6_REG_MAP_OFFSET 0x00083000 523 #define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00088000 524 #define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00090000 525 #define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x000a0000 526 #define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x000b0000 527 #define SEQ_WFAX_TOP_WFAX_TXBF_REG_MAP_OFFSET 0x000c0000 528 #define SEQ_WFAX_TOP_WFAX_DEMFRONT_0_REG_MAP_OFFSET 0x00100000 529 #define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x00180000 530 #define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x001b0000 531 #define SEQ_WFAX_TOP_WFAX_DEMFRONT_1_REG_MAP_OFFSET 0x00200000 532 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET 0x002c0000 533 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET 0x002c0000 534 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET 0x002cf000 535 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET 0x002cf400 536 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x002cf800 537 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET 0x002cfc00 538 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET 0x002c0000 539 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TRC_OFFSET 0x002c0200 540 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_LTE_REG_OFFSET 0x002c5000 541 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET 0x002d1000 542 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x002c7000 543 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x002c9b00 544 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x002c7000 545 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x002cb000 546 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x002d4000 547 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x002d4000 548 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x002d4240 549 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x002d42c0 550 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x002d4300 551 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x002d4400 552 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x002d4480 553 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x002d4800 554 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x002d4c00 555 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_OFFSET 0x002d5000 556 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x002d5400 557 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x002d6000 558 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x002d6040 559 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x002d6100 560 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x002d6140 561 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x002d6180 562 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x002d61c0 563 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x002d6280 564 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x002d6800 565 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x002d6840 566 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x002d6900 567 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x002d6940 568 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x002d6980 569 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x002d69c0 570 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x002d6a80 571 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_BS_OFFSET 0x002d7000 572 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_CLBS_OFFSET 0x002d7040 573 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_BIST_OFFSET 0x002d7100 574 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_PC_OFFSET 0x002d7140 575 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x002d7180 576 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x002d71c0 577 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x002d7280 578 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x002d7c00 579 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET 0x002da000 580 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x002dc000 581 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET 0x002dc000 582 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x002de800 583 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET 0x002de980 584 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x002de9c0 585 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET 0x002deac0 586 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TX_OFFSET 0x002dec00 587 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RX_CH0_OFFSET 0x002df000 588 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RX_CH1_OFFSET 0x002df200 589 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x002dfc00 590 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x002dfc40 591 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x002dfc80 592 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x002dfcc0 593 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x002e0000 594 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x002e0000 595 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x002e0400 596 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x002e0800 597 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x002e1000 598 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x002e1300 599 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x002e2000 600 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x002e2400 601 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x002e2580 602 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET 0x002e25c0 603 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET 0x002e26c0 604 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_2G_CH0_OFFSET 0x002e2734 605 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x002e2740 606 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH0_OFFSET 0x002e2800 607 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH0_OFFSET 0x002e2840 608 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH0_OFFSET 0x002e2880 609 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH0_OFFSET 0x002e28c0 610 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH0_OFFSET 0x002e2900 611 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH0_OFFSET 0x002e299c 612 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x002e4000 613 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x002e8000 614 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x002e8400 615 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x002e8800 616 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x002e9000 617 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x002e9300 618 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x002ea000 619 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x002ea400 620 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x002ea580 621 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET 0x002ea5c0 622 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET 0x002ea6c0 623 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_5G_CH0_OFFSET 0x002ea734 624 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x002ea740 625 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH0_OFFSET 0x002ea800 626 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH0_OFFSET 0x002ea840 627 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH0_OFFSET 0x002ea880 628 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH0_OFFSET 0x002ea8c0 629 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH0_OFFSET 0x002ea900 630 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_5G_CH0_OFFSET 0x002ea99c 631 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x002ec000 632 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x002f0000 633 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x002f0400 634 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x002f0800 635 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x002f1000 636 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x002f1300 637 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x002f2000 638 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x002f2400 639 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x002f2580 640 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x002f25c0 641 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x002f26c0 642 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_2G_CH1_OFFSET 0x002f2734 643 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x002f2740 644 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH1_OFFSET 0x002f2800 645 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH1_OFFSET 0x002f2840 646 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH1_OFFSET 0x002f2880 647 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x002f28c0 648 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x002f2900 649 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x002f299c 650 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x002f4000 651 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x002f8000 652 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x002f8400 653 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x002f8800 654 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x002f9000 655 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x002f9300 656 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x002fa000 657 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x002fa400 658 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x002fa580 659 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET 0x002fa5c0 660 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET 0x002fa6c0 661 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_5G_CH1_OFFSET 0x002fa734 662 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x002fa740 663 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH1_OFFSET 0x002fa800 664 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH1_OFFSET 0x002fa840 665 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH1_OFFSET 0x002fa880 666 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH1_OFFSET 0x002fa8c0 667 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH1_OFFSET 0x002fa900 668 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_5G_CH1_OFFSET 0x002fa99c 669 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x002fc000 670 671 672 /////////////////////////////////////////////////////////////////////////////////////////////// 673 // Instance Relative Offsets from Block rfa_from_wsi 674 /////////////////////////////////////////////////////////////////////////////////////////////// 675 676 #define SEQ_RFA_FROM_WSI_RFA_SOC_OFFSET 0x00000000 677 #define SEQ_RFA_FROM_WSI_RFA_SOC_AO_SYSCTRL_OFFSET 0x0000f000 678 #define SEQ_RFA_FROM_WSI_RFA_SOC_AO_TLMM_OFFSET 0x0000f400 679 #define SEQ_RFA_FROM_WSI_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x0000f800 680 #define SEQ_RFA_FROM_WSI_RFA_SOC_AON_1P8_REG_OFFSET 0x0000fc00 681 #define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_TLMM_OFFSET 0x00000000 682 #define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_TRC_OFFSET 0x00000200 683 #define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_COEX_LTE_REG_OFFSET 0x00005000 684 #define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_OFFSET 0x00011000 685 #define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x00007000 686 #define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x00009b00 687 #define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x00007000 688 #define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x0000b000 689 #define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET 0x00014000 690 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET 0x00014000 691 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_XFEM_OFFSET 0x00014240 692 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_OFFSET 0x000142c0 693 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET 0x00014300 694 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00014400 695 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET 0x00014480 696 #define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET 0x00014800 697 #define SEQ_RFA_FROM_WSI_RFA_CMN_BTFMPLL_OFFSET 0x00014c00 698 #define SEQ_RFA_FROM_WSI_RFA_CMN_BBPLL_OFFSET 0x00015000 699 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x00015400 700 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016000 701 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016040 702 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016100 703 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00016140 704 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016180 705 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000161c0 706 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00016280 707 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00016800 708 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00016840 709 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00016900 710 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00016940 711 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00016980 712 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x000169c0 713 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00016a80 714 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_BS_OFFSET 0x00017000 715 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_CLBS_OFFSET 0x00017040 716 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_BIST_OFFSET 0x00017100 717 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_PC_OFFSET 0x00017140 718 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x00017180 719 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x000171c0 720 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x00017280 721 #define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00017c00 722 #define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_OFFSET 0x0001a000 723 #define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET 0x0001c000 724 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_TOP_OFFSET 0x0001c000 725 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x0001e800 726 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_OFFSET 0x0001e980 727 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x0001e9c0 728 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_MISC_OFFSET 0x0001eac0 729 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_TX_OFFSET 0x0001ec00 730 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_RX_CH0_OFFSET 0x0001f000 731 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_RX_CH1_OFFSET 0x0001f200 732 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BS_OFFSET 0x0001fc00 733 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BIST_OFFSET 0x0001fc40 734 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_PC_OFFSET 0x0001fc80 735 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_AC_OFFSET 0x0001fcc0 736 #define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET 0x00020000 737 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH0_OFFSET 0x00020000 738 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x00020400 739 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x00020800 740 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x00021000 741 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00021300 742 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x00022000 743 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x00022400 744 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x00022580 745 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET 0x000225c0 746 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET 0x000226c0 747 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BBCLKGEN_2G_CH0_OFFSET 0x00022734 748 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x00022740 749 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH0_OFFSET 0x00022800 750 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH0_OFFSET 0x00022840 751 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH0_OFFSET 0x00022880 752 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH0_OFFSET 0x000228c0 753 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH0_OFFSET 0x00022900 754 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_2G_CH0_OFFSET 0x0002299c 755 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x00024000 756 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH0_OFFSET 0x00028000 757 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x00028400 758 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x00028800 759 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00029000 760 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00029300 761 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0002a000 762 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x0002a400 763 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x0002a580 764 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET 0x0002a5c0 765 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET 0x0002a6c0 766 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BBCLKGEN_5G_CH0_OFFSET 0x0002a734 767 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x0002a740 768 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH0_OFFSET 0x0002a800 769 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH0_OFFSET 0x0002a840 770 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH0_OFFSET 0x0002a880 771 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH0_OFFSET 0x0002a8c0 772 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH0_OFFSET 0x0002a900 773 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_5G_CH0_OFFSET 0x0002a99c 774 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x0002c000 775 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH1_OFFSET 0x00030000 776 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x00030400 777 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x00030800 778 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x00031000 779 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x00031300 780 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x00032000 781 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x00032400 782 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x00032580 783 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x000325c0 784 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x000326c0 785 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BBCLKGEN_2G_CH1_OFFSET 0x00032734 786 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x00032740 787 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH1_OFFSET 0x00032800 788 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH1_OFFSET 0x00032840 789 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH1_OFFSET 0x00032880 790 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x000328c0 791 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x00032900 792 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x0003299c 793 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x00034000 794 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH1_OFFSET 0x00038000 795 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x00038400 796 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x00038800 797 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x00039000 798 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x00039300 799 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x0003a000 800 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x0003a400 801 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x0003a580 802 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET 0x0003a5c0 803 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET 0x0003a6c0 804 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BBCLKGEN_5G_CH1_OFFSET 0x0003a734 805 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x0003a740 806 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH1_OFFSET 0x0003a800 807 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH1_OFFSET 0x0003a840 808 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH1_OFFSET 0x0003a880 809 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH1_OFFSET 0x0003a8c0 810 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH1_OFFSET 0x0003a900 811 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_5G_CH1_OFFSET 0x0003a99c 812 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x0003c000 813 814 815 /////////////////////////////////////////////////////////////////////////////////////////////// 816 // Instance Relative Offsets from Block rfa_soc 817 /////////////////////////////////////////////////////////////////////////////////////////////// 818 819 #define SEQ_RFA_SOC_AO_SYSCTRL_OFFSET 0x0000f000 820 #define SEQ_RFA_SOC_AO_TLMM_OFFSET 0x0000f400 821 #define SEQ_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x0000f800 822 #define SEQ_RFA_SOC_AON_1P8_REG_OFFSET 0x0000fc00 823 #define SEQ_RFA_SOC_HZ_TLMM_OFFSET 0x00000000 824 #define SEQ_RFA_SOC_HZ_TRC_OFFSET 0x00000200 825 #define SEQ_RFA_SOC_HZ_COEX_LTE_REG_OFFSET 0x00005000 826 #define SEQ_RFA_SOC_PMU_OFFSET 0x00011000 827 #define SEQ_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x00007000 828 #define SEQ_RFA_SOC_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x00009b00 829 #define SEQ_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x00007000 830 #define SEQ_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x0000b000 831 832 833 /////////////////////////////////////////////////////////////////////////////////////////////// 834 // Instance Relative Offsets from Block security_control_bt 835 /////////////////////////////////////////////////////////////////////////////////////////////// 836 837 #define SEQ_SECURITY_CONTROL_BT_BT_SECURITY_CONTROL_CORE_OFFSET 0x00002b00 838 #define SEQ_SECURITY_CONTROL_BT_BT_QFPROM_RAW_FUSE_OFFSET 0x00000000 839 #define SEQ_SECURITY_CONTROL_BT_BT_QFPROM_CORR_FUSE_OFFSET 0x00004000 840 841 842 /////////////////////////////////////////////////////////////////////////////////////////////// 843 // Instance Relative Offsets from Block rfa_cmn 844 /////////////////////////////////////////////////////////////////////////////////////////////// 845 846 #define SEQ_RFA_CMN_AON_OFFSET 0x00000000 847 #define SEQ_RFA_CMN_AON_XFEM_OFFSET 0x00000240 848 #define SEQ_RFA_CMN_AON_COEX_OFFSET 0x000002c0 849 #define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300 850 #define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00000400 851 #define SEQ_RFA_CMN_RFA_OTP_OFFSET 0x00000480 852 #define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000800 853 #define SEQ_RFA_CMN_BTFMPLL_OFFSET 0x00000c00 854 #define SEQ_RFA_CMN_BBPLL_OFFSET 0x00001000 855 #define SEQ_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x00001400 856 #define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002000 857 #define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002040 858 #define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002100 859 #define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00002140 860 #define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002180 861 #define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000021c0 862 #define SEQ_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00002280 863 #define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00002800 864 #define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00002840 865 #define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00002900 866 #define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00002940 867 #define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00002980 868 #define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x000029c0 869 #define SEQ_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00002a80 870 #define SEQ_RFA_CMN_WL_SYNTH2_BS_OFFSET 0x00003000 871 #define SEQ_RFA_CMN_WL_SYNTH2_CLBS_OFFSET 0x00003040 872 #define SEQ_RFA_CMN_WL_SYNTH2_BIST_OFFSET 0x00003100 873 #define SEQ_RFA_CMN_WL_SYNTH2_PC_OFFSET 0x00003140 874 #define SEQ_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x00003180 875 #define SEQ_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x000031c0 876 #define SEQ_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x00003280 877 #define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00003c00 878 #define SEQ_RFA_CMN_PMU_TEST_OFFSET 0x00006000 879 880 881 /////////////////////////////////////////////////////////////////////////////////////////////// 882 // Instance Relative Offsets from Block rfa_bt 883 /////////////////////////////////////////////////////////////////////////////////////////////// 884 885 #define SEQ_RFA_BT_BT_TOP_OFFSET 0x00000000 886 #define SEQ_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x00002800 887 #define SEQ_RFA_BT_BT_DAC_OFFSET 0x00002980 888 #define SEQ_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x000029c0 889 #define SEQ_RFA_BT_BT_DAC_MISC_OFFSET 0x00002ac0 890 #define SEQ_RFA_BT_BT_TX_OFFSET 0x00002c00 891 #define SEQ_RFA_BT_BT_RX_CH0_OFFSET 0x00003000 892 #define SEQ_RFA_BT_BT_RX_CH1_OFFSET 0x00003200 893 #define SEQ_RFA_BT_BT_SYNTH_BS_OFFSET 0x00003c00 894 #define SEQ_RFA_BT_BT_SYNTH_BIST_OFFSET 0x00003c40 895 #define SEQ_RFA_BT_BT_SYNTH_PC_OFFSET 0x00003c80 896 #define SEQ_RFA_BT_BT_SYNTH_AC_OFFSET 0x00003cc0 897 898 899 /////////////////////////////////////////////////////////////////////////////////////////////// 900 // Instance Relative Offsets from Block rfa_wl 901 /////////////////////////////////////////////////////////////////////////////////////////////// 902 903 #define SEQ_RFA_WL_WL_MC_2G_CH0_OFFSET 0x00000000 904 #define SEQ_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x00000400 905 #define SEQ_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x00000800 906 #define SEQ_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x00001000 907 #define SEQ_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00001300 908 #define SEQ_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x00002000 909 #define SEQ_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x00002400 910 #define SEQ_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x00002580 911 #define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET 0x000025c0 912 #define SEQ_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET 0x000026c0 913 #define SEQ_RFA_WL_WL_DAC_BBCLKGEN_2G_CH0_OFFSET 0x00002734 914 #define SEQ_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x00002740 915 #define SEQ_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH0_OFFSET 0x00002800 916 #define SEQ_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH0_OFFSET 0x00002840 917 #define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH0_OFFSET 0x00002880 918 #define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH0_OFFSET 0x000028c0 919 #define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH0_OFFSET 0x00002900 920 #define SEQ_RFA_WL_WL_ADC_BBCLKGEN_2G_CH0_OFFSET 0x0000299c 921 #define SEQ_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x00004000 922 #define SEQ_RFA_WL_WL_MC_5G_CH0_OFFSET 0x00008000 923 #define SEQ_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x00008400 924 #define SEQ_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x00008800 925 #define SEQ_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00009000 926 #define SEQ_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00009300 927 #define SEQ_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0000a000 928 #define SEQ_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x0000a400 929 #define SEQ_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x0000a580 930 #define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET 0x0000a5c0 931 #define SEQ_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET 0x0000a6c0 932 #define SEQ_RFA_WL_WL_DAC_BBCLKGEN_5G_CH0_OFFSET 0x0000a734 933 #define SEQ_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x0000a740 934 #define SEQ_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH0_OFFSET 0x0000a800 935 #define SEQ_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH0_OFFSET 0x0000a840 936 #define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH0_OFFSET 0x0000a880 937 #define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH0_OFFSET 0x0000a8c0 938 #define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH0_OFFSET 0x0000a900 939 #define SEQ_RFA_WL_WL_ADC_BBCLKGEN_5G_CH0_OFFSET 0x0000a99c 940 #define SEQ_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x0000c000 941 #define SEQ_RFA_WL_WL_MC_2G_CH1_OFFSET 0x00010000 942 #define SEQ_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x00010400 943 #define SEQ_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x00010800 944 #define SEQ_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x00011000 945 #define SEQ_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x00011300 946 #define SEQ_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x00012000 947 #define SEQ_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x00012400 948 #define SEQ_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x00012580 949 #define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x000125c0 950 #define SEQ_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x000126c0 951 #define SEQ_RFA_WL_WL_DAC_BBCLKGEN_2G_CH1_OFFSET 0x00012734 952 #define SEQ_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x00012740 953 #define SEQ_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH1_OFFSET 0x00012800 954 #define SEQ_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH1_OFFSET 0x00012840 955 #define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH1_OFFSET 0x00012880 956 #define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x000128c0 957 #define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x00012900 958 #define SEQ_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x0001299c 959 #define SEQ_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x00014000 960 #define SEQ_RFA_WL_WL_MC_5G_CH1_OFFSET 0x00018000 961 #define SEQ_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x00018400 962 #define SEQ_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x00018800 963 #define SEQ_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x00019000 964 #define SEQ_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x00019300 965 #define SEQ_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x0001a000 966 #define SEQ_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x0001a400 967 #define SEQ_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x0001a580 968 #define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET 0x0001a5c0 969 #define SEQ_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET 0x0001a6c0 970 #define SEQ_RFA_WL_WL_DAC_BBCLKGEN_5G_CH1_OFFSET 0x0001a734 971 #define SEQ_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x0001a740 972 #define SEQ_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH1_OFFSET 0x0001a800 973 #define SEQ_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH1_OFFSET 0x0001a840 974 #define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH1_OFFSET 0x0001a880 975 #define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH1_OFFSET 0x0001a8c0 976 #define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH1_OFFSET 0x0001a900 977 #define SEQ_RFA_WL_WL_ADC_BBCLKGEN_5G_CH1_OFFSET 0x0001a99c 978 #define SEQ_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x0001c000 979 980 981 /////////////////////////////////////////////////////////////////////////////////////////////// 982 // Instance Relative Offsets from Block wfax_top_b 983 /////////////////////////////////////////////////////////////////////////////////////////////// 984 985 #define SEQ_WFAX_TOP_B_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00000000 986 #define SEQ_WFAX_TOP_B_WFAX_PCSS_B_REG_MAP_OFFSET 0x00080000 987 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00080400 988 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00080800 989 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00080c00 990 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00081000 991 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00081400 992 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DUAL_TIMER_B_REG_MAP_OFFSET 0x00081800 993 #define SEQ_WFAX_TOP_B_WFAX_PCSS_WATCHDOG_B_REG_MAP_OFFSET 0x00081c00 994 #define SEQ_WFAX_TOP_B_WFAX_PCSS_XDMAC5_B_REG_MAP_OFFSET 0x00082c00 995 #define SEQ_WFAX_TOP_B_WFAX_PCSS_XDMAC6_B_REG_MAP_OFFSET 0x00083000 996 #define SEQ_WFAX_TOP_B_WFAX_NOC_B_REG_MAP_OFFSET 0x00088000 997 #define SEQ_WFAX_TOP_B_WFAX_TXFD_B_REG_MAP_OFFSET 0x00090000 998 #define SEQ_WFAX_TOP_B_WFAX_RXTD_B_REG_MAP_OFFSET 0x000a0000 999 #define SEQ_WFAX_TOP_B_WFAX_TXTD_B_REG_MAP_OFFSET 0x000b0000 1000 #define SEQ_WFAX_TOP_B_WFAX_TXBF_B_REG_MAP_OFFSET 0x000c0000 1001 #define SEQ_WFAX_TOP_B_WFAX_DEMFRONT_NPRB_B_REG_MAP_OFFSET 0x00100000 1002 #define SEQ_WFAX_TOP_B_WFAX_PHYRF_B_REG_MAP_OFFSET 0x00180000 1003 #define SEQ_WFAX_TOP_B_WFAX_ROBE_B_REG_MAP_OFFSET 0x001b0000 1004 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_OFFSET 0x001c0000 1005 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET 0x001c0000 1006 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET 0x001cf000 1007 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET 0x001cf400 1008 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x001cf800 1009 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET 0x001cfc00 1010 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET 0x001c0000 1011 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TRC_OFFSET 0x001c0200 1012 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_LTE_REG_OFFSET 0x001c5000 1013 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET 0x001d1000 1014 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x001c7000 1015 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x001c9b00 1016 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x001c7000 1017 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x001cb000 1018 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x001d4000 1019 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x001d4000 1020 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x001d4240 1021 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x001d42c0 1022 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4300 1023 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x001d4400 1024 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x001d4480 1025 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4800 1026 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x001d4c00 1027 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_OFFSET 0x001d5000 1028 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x001d5400 1029 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000 1030 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040 1031 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d6100 1032 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x001d6140 1033 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x001d6180 1034 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x001d61c0 1035 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x001d6280 1036 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x001d6800 1037 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x001d6840 1038 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x001d6900 1039 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x001d6940 1040 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6980 1041 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d69c0 1042 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x001d6a80 1043 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_BS_OFFSET 0x001d7000 1044 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_CLBS_OFFSET 0x001d7040 1045 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_BIST_OFFSET 0x001d7100 1046 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_PC_OFFSET 0x001d7140 1047 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x001d7180 1048 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x001d71c0 1049 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x001d7280 1050 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x001d7c00 1051 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET 0x001da000 1052 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x001dc000 1053 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET 0x001dc000 1054 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x001de800 1055 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET 0x001de980 1056 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x001de9c0 1057 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET 0x001deac0 1058 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TX_OFFSET 0x001dec00 1059 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RX_CH0_OFFSET 0x001df000 1060 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RX_CH1_OFFSET 0x001df200 1061 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x001dfc00 1062 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x001dfc40 1063 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x001dfc80 1064 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x001dfcc0 1065 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x001e0000 1066 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x001e0000 1067 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x001e0400 1068 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x001e0800 1069 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x001e1000 1070 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x001e1300 1071 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x001e2000 1072 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x001e2400 1073 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x001e2580 1074 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET 0x001e25c0 1075 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET 0x001e26c0 1076 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_2G_CH0_OFFSET 0x001e2734 1077 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x001e2740 1078 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH0_OFFSET 0x001e2800 1079 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH0_OFFSET 0x001e2840 1080 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH0_OFFSET 0x001e2880 1081 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH0_OFFSET 0x001e28c0 1082 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH0_OFFSET 0x001e2900 1083 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH0_OFFSET 0x001e299c 1084 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x001e4000 1085 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x001e8000 1086 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x001e8400 1087 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x001e8800 1088 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x001e9000 1089 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x001e9300 1090 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x001ea000 1091 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x001ea400 1092 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x001ea580 1093 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET 0x001ea5c0 1094 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET 0x001ea6c0 1095 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_5G_CH0_OFFSET 0x001ea734 1096 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x001ea740 1097 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH0_OFFSET 0x001ea800 1098 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH0_OFFSET 0x001ea840 1099 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH0_OFFSET 0x001ea880 1100 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH0_OFFSET 0x001ea8c0 1101 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH0_OFFSET 0x001ea900 1102 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_5G_CH0_OFFSET 0x001ea99c 1103 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x001ec000 1104 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x001f0000 1105 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x001f0400 1106 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x001f0800 1107 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x001f1000 1108 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x001f1300 1109 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x001f2000 1110 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x001f2400 1111 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x001f2580 1112 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x001f25c0 1113 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x001f26c0 1114 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_2G_CH1_OFFSET 0x001f2734 1115 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x001f2740 1116 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH1_OFFSET 0x001f2800 1117 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH1_OFFSET 0x001f2840 1118 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH1_OFFSET 0x001f2880 1119 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x001f28c0 1120 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x001f2900 1121 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x001f299c 1122 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x001f4000 1123 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x001f8000 1124 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x001f8400 1125 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x001f8800 1126 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x001f9000 1127 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x001f9300 1128 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x001fa000 1129 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x001fa400 1130 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x001fa580 1131 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET 0x001fa5c0 1132 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET 0x001fa6c0 1133 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_5G_CH1_OFFSET 0x001fa734 1134 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x001fa740 1135 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH1_OFFSET 0x001fa800 1136 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH1_OFFSET 0x001fa840 1137 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH1_OFFSET 0x001fa880 1138 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH1_OFFSET 0x001fa8c0 1139 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH1_OFFSET 0x001fa900 1140 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_5G_CH1_OFFSET 0x001fa99c 1141 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x001fc000 1142 1143 1144 /////////////////////////////////////////////////////////////////////////////////////////////// 1145 // Instance Relative Offsets from Block umac_top_reg 1146 /////////////////////////////////////////////////////////////////////////////////////////////// 1147 1148 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000 1149 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000 1150 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000 1151 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000 1152 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000 1153 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000 1154 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000 1155 #define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000 1156 #define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET 0x00034000 1157 #define SEQ_UMAC_TOP_REG_REO_REG_OFFSET 0x00038000 1158 #define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000 1159 #define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000 1160 #define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET 0x00044000 1161 #define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_CE_REG_OFFSET 0x00047000 1162 1163 1164 /////////////////////////////////////////////////////////////////////////////////////////////// 1165 // Instance Relative Offsets from Block cxc_top_reg 1166 /////////////////////////////////////////////////////////////////////////////////////////////// 1167 1168 #define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000 1169 #define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000 1170 #define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000 1171 #define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000 1172 #define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000 1173 #define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000 1174 1175 1176 /////////////////////////////////////////////////////////////////////////////////////////////// 1177 // Instance Relative Offsets from Block wmac_top_reg 1178 /////////////////////////////////////////////////////////////////////////////////////////////// 1179 1180 #define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000 1181 #define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000 1182 #define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000 1183 #define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000 1184 #define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000 1185 #define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000 1186 #define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000 1187 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000 1188 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000 1189 #define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000 1190 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000 1191 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000 1192 #define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000 1193 #define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000 1194 #define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000 1195 #define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000 1196 #define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000 1197 1198 1199 /////////////////////////////////////////////////////////////////////////////////////////////// 1200 // Instance Relative Offsets from Block wcssdbg 1201 /////////////////////////////////////////////////////////////////////////////////////////////// 1202 1203 #define SEQ_WCSSDBG_WCSS_DBG_DAPROM_OFFSET 0x00000000 1204 #define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET 0x00001000 1205 #define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET 0x00002000 1206 #define SEQ_WCSSDBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00004000 1207 #define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000 1208 #define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000 1209 #define SEQ_WCSSDBG_EVENT_MACEVENT_OFFSET 0x00020000 1210 #define SEQ_WCSSDBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00021000 1211 #define SEQ_WCSSDBG_TLV_MACTLV_OFFSET 0x00022000 1212 #define SEQ_WCSSDBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00023000 1213 #define SEQ_WCSSDBG_TBUS_MACTBUS_OFFSET 0x00024000 1214 #define SEQ_WCSSDBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00025000 1215 #define SEQ_WCSSDBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00026000 1216 #define SEQ_WCSSDBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00028000 1217 #define SEQ_WCSSDBG_TPDM_OFFSET 0x00029000 1218 #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00029280 1219 #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00029000 1220 #define SEQ_WCSSDBG_TPDA_OFFSET 0x0002a000 1221 #define SEQ_WCSSDBG_CXATBFUNNEL_128W8SP_OFFSET 0x0002b000 1222 #define SEQ_WCSSDBG_TMC_CXTMC_F128W32K_OFFSET 0x0002c000 1223 #define SEQ_WCSSDBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002e000 1224 #define SEQ_WCSSDBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002f000 1225 #define SEQ_WCSSDBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00030000 1226 #define SEQ_WCSSDBG_TRCCNTRS_OFFSET 0x00031000 1227 #define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_OFFSET 0x00032000 1228 #define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00032280 1229 #define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00032000 1230 #define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_OFFSET 0x00033000 1231 #define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00033280 1232 #define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00033000 1233 #define SEQ_WCSSDBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00034000 1234 #define SEQ_WCSSDBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00035000 1235 #define SEQ_WCSSDBG_PHYADMUX_ATB_DEMUX_OFFSET 0x00036000 1236 #define SEQ_WCSSDBG_PHYBDMUX_ATB_DEMUX_OFFSET 0x00037000 1237 #define SEQ_WCSSDBG_MISCFUN_CXATBFUNNEL_64W8SP_OFFSET 0x00038000 1238 #define SEQ_WCSSDBG_UNOC_UMAC_NOC_OFFSET 0x00040000 1239 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_OFFSET 0x00050000 1240 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00050000 1241 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00054000 1242 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00055000 1243 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00056000 1244 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_ITM_OFFSET 0x00058000 1245 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_DWT_OFFSET 0x00059000 1246 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_FPB_OFFSET 0x0005a000 1247 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_SCS_OFFSET 0x0005b000 1248 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_M3_ETM_OFFSET 0x0005c000 1249 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0005d000 1250 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET 0x0005e000 1251 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_OFFSET 0x00060000 1252 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_PHYB_NOC_OFFSET 0x00060000 1253 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00064000 1254 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00065000 1255 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00066000 1256 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_ITM_OFFSET 0x00068000 1257 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_DWT_OFFSET 0x00069000 1258 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_FPB_OFFSET 0x0006a000 1259 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_SCS_OFFSET 0x0006b000 1260 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_ETM_OFFSET 0x0006c000 1261 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0006d000 1262 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_CPU0_M3_AHB_AP_OFFSET 0x0006e000 1263 #define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET 0x000a1000 1264 1265 1266 /////////////////////////////////////////////////////////////////////////////////////////////// 1267 // Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7 1268 /////////////////////////////////////////////////////////////////////////////////////////////// 1269 1270 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280 1271 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000 1272 1273 1274 /////////////////////////////////////////////////////////////////////////////////////////////// 1275 // Instance Relative Offsets from Block tpdm_atb128_cmb64 1276 /////////////////////////////////////////////////////////////////////////////////////////////// 1277 1278 #define SEQ_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00000280 1279 #define SEQ_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00000000 1280 1281 1282 /////////////////////////////////////////////////////////////////////////////////////////////// 1283 // Instance Relative Offsets from Block phya_dbg 1284 /////////////////////////////////////////////////////////////////////////////////////////////// 1285 1286 #define SEQ_PHYA_DBG_PHYA_NOC_OFFSET 0x00000000 1287 #define SEQ_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00004000 1288 #define SEQ_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00005000 1289 #define SEQ_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00006000 1290 #define SEQ_PHYA_DBG_ITM_OFFSET 0x00008000 1291 #define SEQ_PHYA_DBG_DWT_OFFSET 0x00009000 1292 #define SEQ_PHYA_DBG_FPB_OFFSET 0x0000a000 1293 #define SEQ_PHYA_DBG_SCS_OFFSET 0x0000b000 1294 #define SEQ_PHYA_DBG_M3_ETM_OFFSET 0x0000c000 1295 #define SEQ_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0000d000 1296 #define SEQ_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET 0x0000e000 1297 1298 1299 /////////////////////////////////////////////////////////////////////////////////////////////// 1300 // Instance Relative Offsets from Block phyb_dbg 1301 /////////////////////////////////////////////////////////////////////////////////////////////// 1302 1303 #define SEQ_PHYB_DBG_PHYB_NOC_OFFSET 0x00000000 1304 #define SEQ_PHYB_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00004000 1305 #define SEQ_PHYB_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00005000 1306 #define SEQ_PHYB_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00006000 1307 #define SEQ_PHYB_DBG_ITM_OFFSET 0x00008000 1308 #define SEQ_PHYB_DBG_DWT_OFFSET 0x00009000 1309 #define SEQ_PHYB_DBG_FPB_OFFSET 0x0000a000 1310 #define SEQ_PHYB_DBG_SCS_OFFSET 0x0000b000 1311 #define SEQ_PHYB_DBG_ETM_OFFSET 0x0000c000 1312 #define SEQ_PHYB_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0000d000 1313 #define SEQ_PHYB_DBG_CPU0_M3_AHB_AP_OFFSET 0x0000e000 1314 1315 1316 /////////////////////////////////////////////////////////////////////////////////////////////// 1317 // Instance Relative Offsets from Block qdsp6v67ss_wlan 1318 /////////////////////////////////////////////////////////////////////////////////////////////// 1319 1320 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_OFFSET 0x00000000 1321 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00000000 1322 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000 1323 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00080000 1324 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00080000 1325 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00090000 1326 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x000a0000 1327 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x000a1000 1328 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x000a2000 1329 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x000a3000 1330 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x000b0000 1331 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x000b0000 1332 1333 1334 /////////////////////////////////////////////////////////////////////////////////////////////// 1335 // Instance Relative Offsets from Block qdsp6v67ss 1336 /////////////////////////////////////////////////////////////////////////////////////////////// 1337 1338 #define SEQ_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00000000 1339 #define SEQ_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000 1340 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00080000 1341 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00080000 1342 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00090000 1343 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x000a0000 1344 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x000a1000 1345 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x000a2000 1346 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x000a3000 1347 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x000b0000 1348 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x000b0000 1349 1350 1351 /////////////////////////////////////////////////////////////////////////////////////////////// 1352 // Instance Relative Offsets from Block qdsp6v67ss_public 1353 /////////////////////////////////////////////////////////////////////////////////////////////// 1354 1355 #define SEQ_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000 1356 1357 1358 /////////////////////////////////////////////////////////////////////////////////////////////// 1359 // Instance Relative Offsets from Block qdsp6v67ss_private 1360 /////////////////////////////////////////////////////////////////////////////////////////////// 1361 1362 #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00000000 1363 #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00010000 1364 #define SEQ_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00020000 1365 #define SEQ_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x00021000 1366 #define SEQ_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x00022000 1367 #define SEQ_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x00023000 1368 #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x00030000 1369 #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x00030000 1370 1371 1372 /////////////////////////////////////////////////////////////////////////////////////////////// 1373 // Instance Relative Offsets from Block q6ss_rscc 1374 /////////////////////////////////////////////////////////////////////////////////////////////// 1375 1376 #define SEQ_Q6SS_RSCC_RSCC_RSC_OFFSET 0x00000000 1377 1378 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x1B80000 1379 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x1B81000 1380 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x1B82000 1381 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x1B83000 1382 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x1B84000 1383 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x1B85000 1384 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x1B86000 1385 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x1B87000 1386 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x1B88000 1387 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x1B89000 1388 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x1B8A000 1389 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x1B8B000 1390 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x1B8C000 1391 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x1B8D000 1392 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x1B8E000 1393 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x1B8F000 1394 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x1B90000 1395 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x1B91000 1396 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x1B92000 1397 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x1B93000 1398 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x1B94000 1399 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x1B95000 1400 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x1B96000 1401 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x1B97000 1402 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET 0x1B98000 1403 1404 #endif 1405 1406