1 /* 2 * Copyright (c) 2015-2020 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef __CE_REG_H__ 21 #define __CE_REG_H__ 22 23 #define COPY_ENGINE_ID(COPY_ENGINE_BASE_ADDRESS) ((COPY_ENGINE_BASE_ADDRESS \ 24 - CE0_BASE_ADDRESS)/(CE1_BASE_ADDRESS - CE0_BASE_ADDRESS)) 25 26 #define DST_WR_INDEX_ADDRESS (scn->target_ce_def->d_DST_WR_INDEX_ADDRESS) 27 #define SRC_WATERMARK_ADDRESS (scn->target_ce_def->d_SRC_WATERMARK_ADDRESS) 28 #define SRC_WATERMARK_LOW_MASK (scn->target_ce_def->d_SRC_WATERMARK_LOW_MASK) 29 #define SRC_WATERMARK_HIGH_MASK (scn->target_ce_def->d_SRC_WATERMARK_HIGH_MASK) 30 #define DST_WATERMARK_LOW_MASK (scn->target_ce_def->d_DST_WATERMARK_LOW_MASK) 31 #define DST_WATERMARK_HIGH_MASK (scn->target_ce_def->d_DST_WATERMARK_HIGH_MASK) 32 #define CURRENT_SRRI_ADDRESS (scn->target_ce_def->d_CURRENT_SRRI_ADDRESS) 33 #define CURRENT_DRRI_ADDRESS (scn->target_ce_def->d_CURRENT_DRRI_ADDRESS) 34 35 #define SHADOW_VALUE0 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_0) 36 #define SHADOW_VALUE1 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_1) 37 #define SHADOW_VALUE2 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_2) 38 #define SHADOW_VALUE3 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_3) 39 #define SHADOW_VALUE4 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_4) 40 #define SHADOW_VALUE5 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_5) 41 #define SHADOW_VALUE6 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_6) 42 #define SHADOW_VALUE7 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_7) 43 #define SHADOW_VALUE8 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_8) 44 #define SHADOW_VALUE9 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_9) 45 #define SHADOW_VALUE10 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_10) 46 #define SHADOW_VALUE11 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_11) 47 #define SHADOW_VALUE12 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_12) 48 #define SHADOW_VALUE13 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_13) 49 #define SHADOW_VALUE14 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_14) 50 #define SHADOW_VALUE15 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_15) 51 #define SHADOW_VALUE16 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_16) 52 #define SHADOW_VALUE17 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_17) 53 #define SHADOW_VALUE18 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_18) 54 #define SHADOW_VALUE19 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_19) 55 #define SHADOW_VALUE20 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_20) 56 #define SHADOW_VALUE21 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_21) 57 #define SHADOW_VALUE22 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_22) 58 #define SHADOW_VALUE23 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_23) 59 #define SHADOW_ADDRESS0 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_0) 60 #define SHADOW_ADDRESS1 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_1) 61 #define SHADOW_ADDRESS2 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_2) 62 #define SHADOW_ADDRESS3 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_3) 63 #define SHADOW_ADDRESS4 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_4) 64 #define SHADOW_ADDRESS5 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_5) 65 #define SHADOW_ADDRESS6 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_6) 66 #define SHADOW_ADDRESS7 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_7) 67 #define SHADOW_ADDRESS8 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_8) 68 #define SHADOW_ADDRESS9 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_9) 69 #define SHADOW_ADDRESS10 \ 70 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_10) 71 #define SHADOW_ADDRESS11 \ 72 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_11) 73 #define SHADOW_ADDRESS12 \ 74 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_12) 75 #define SHADOW_ADDRESS13 \ 76 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_13) 77 #define SHADOW_ADDRESS14 \ 78 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_14) 79 #define SHADOW_ADDRESS15 \ 80 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_15) 81 #define SHADOW_ADDRESS16 \ 82 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_16) 83 #define SHADOW_ADDRESS17 \ 84 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_17) 85 #define SHADOW_ADDRESS18 \ 86 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_18) 87 #define SHADOW_ADDRESS19 \ 88 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_19) 89 #define SHADOW_ADDRESS20 \ 90 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_20) 91 #define SHADOW_ADDRESS21 \ 92 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_21) 93 #define SHADOW_ADDRESS22 \ 94 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_22) 95 #define SHADOW_ADDRESS23 \ 96 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_23) 97 98 #define SHADOW_ADDRESS(i) \ 99 (SHADOW_ADDRESS0 + i*(SHADOW_ADDRESS1-SHADOW_ADDRESS0)) 100 101 #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK \ 102 (scn->target_ce_def->d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK) 103 #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK \ 104 (scn->target_ce_def->d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK) 105 #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK \ 106 (scn->target_ce_def->d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK) 107 #define HOST_IS_DST_RING_LOW_WATERMARK_MASK \ 108 (scn->target_ce_def->d_HOST_IS_DST_RING_LOW_WATERMARK_MASK) 109 #define MISC_IS_ADDRESS (scn->target_ce_def->d_MISC_IS_ADDRESS) 110 #define HOST_IS_COPY_COMPLETE_MASK \ 111 (scn->target_ce_def->d_HOST_IS_COPY_COMPLETE_MASK) 112 #define CE_WRAPPER_BASE_ADDRESS (scn->target_ce_def->d_CE_WRAPPER_BASE_ADDRESS) 113 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS \ 114 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS) 115 #define CE_DDR_ADDRESS_FOR_RRI_LOW \ 116 (scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_LOW) 117 #define CE_DDR_ADDRESS_FOR_RRI_HIGH \ 118 (scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_HIGH) 119 #define HOST_IE_COPY_COMPLETE_MASK \ 120 (scn->target_ce_def->d_HOST_IE_COPY_COMPLETE_MASK) 121 #define SR_BA_ADDRESS (scn->target_ce_def->d_SR_BA_ADDRESS) 122 #define SR_BA_ADDRESS_HIGH (scn->target_ce_def->d_SR_BA_ADDRESS_HIGH) 123 #define SR_SIZE_ADDRESS (scn->target_ce_def->d_SR_SIZE_ADDRESS) 124 #define CE_CTRL1_ADDRESS (scn->target_ce_def->d_CE_CTRL1_ADDRESS) 125 #define CE_CTRL1_DMAX_LENGTH_MASK \ 126 (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_MASK) 127 #define DR_BA_ADDRESS (scn->target_ce_def->d_DR_BA_ADDRESS) 128 #define DR_BA_ADDRESS_HIGH (scn->target_ce_def->d_DR_BA_ADDRESS_HIGH) 129 #define DR_SIZE_ADDRESS (scn->target_ce_def->d_DR_SIZE_ADDRESS) 130 #define CE_CMD_REGISTER (scn->target_ce_def->d_CE_CMD_REGISTER) 131 #define CE_MSI_ADDRESS (scn->target_ce_def->d_CE_MSI_ADDRESS) 132 #define CE_MSI_ADDRESS_HIGH (scn->target_ce_def->d_CE_MSI_ADDRESS_HIGH) 133 #define CE_MSI_DATA (scn->target_ce_def->d_CE_MSI_DATA) 134 #define CE_MSI_ENABLE_BIT (scn->target_ce_def->d_CE_MSI_ENABLE_BIT) 135 #define CE_SRC_BATCH_TIMER_INT_SETUP \ 136 (scn->target_ce_def->d_CE_SRC_BATCH_TIMER_INT_SETUP) 137 #define CE_DST_BATCH_TIMER_INT_SETUP \ 138 (scn->target_ce_def->d_CE_DST_BATCH_TIMER_INT_SETUP) 139 #define MISC_IE_ADDRESS (scn->target_ce_def->d_MISC_IE_ADDRESS) 140 #define MISC_IS_AXI_ERR_MASK (scn->target_ce_def->d_MISC_IS_AXI_ERR_MASK) 141 #define MISC_IS_DST_ADDR_ERR_MASK \ 142 (scn->target_ce_def->d_MISC_IS_DST_ADDR_ERR_MASK) 143 #define MISC_IS_SRC_LEN_ERR_MASK \ 144 (scn->target_ce_def->d_MISC_IS_SRC_LEN_ERR_MASK) 145 #define MISC_IS_DST_MAX_LEN_VIO_MASK \ 146 (scn->target_ce_def->d_MISC_IS_DST_MAX_LEN_VIO_MASK) 147 #define MISC_IS_DST_RING_OVERFLOW_MASK \ 148 (scn->target_ce_def->d_MISC_IS_DST_RING_OVERFLOW_MASK) 149 #define MISC_IS_SRC_RING_OVERFLOW_MASK \ 150 (scn->target_ce_def->d_MISC_IS_SRC_RING_OVERFLOW_MASK) 151 #define SRC_WATERMARK_LOW_LSB (scn->target_ce_def->d_SRC_WATERMARK_LOW_LSB) 152 #define SRC_WATERMARK_HIGH_LSB (scn->target_ce_def->d_SRC_WATERMARK_HIGH_LSB) 153 #define DST_WATERMARK_LOW_LSB (scn->target_ce_def->d_DST_WATERMARK_LOW_LSB) 154 #define DST_WATERMARK_HIGH_LSB (scn->target_ce_def->d_DST_WATERMARK_HIGH_LSB) 155 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \ 156 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) 157 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \ 158 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) 159 #define CE_CTRL1_DMAX_LENGTH_LSB \ 160 (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_LSB) 161 #define CE_CTRL1_IDX_UPD_EN (scn->target_ce_def->d_CE_CTRL1_IDX_UPD_EN_MASK) 162 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK \ 163 (scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) 164 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK \ 165 (scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) 166 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB \ 167 (scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) 168 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB \ 169 (scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) 170 #define WLAN_DEBUG_INPUT_SEL_OFFSET \ 171 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_OFFSET) 172 #define WLAN_DEBUG_INPUT_SEL_SRC_MSB \ 173 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MSB) 174 #define WLAN_DEBUG_INPUT_SEL_SRC_LSB \ 175 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_LSB) 176 #define WLAN_DEBUG_INPUT_SEL_SRC_MASK \ 177 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MASK) 178 #define WLAN_DEBUG_CONTROL_OFFSET (scn->targetdef->d_WLAN_DEBUG_CONTROL_OFFSET) 179 #define WLAN_DEBUG_CONTROL_ENABLE_MSB \ 180 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MSB) 181 #define WLAN_DEBUG_CONTROL_ENABLE_LSB \ 182 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_LSB) 183 #define WLAN_DEBUG_CONTROL_ENABLE_MASK \ 184 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MASK) 185 #define WLAN_DEBUG_OUT_OFFSET (scn->targetdef->d_WLAN_DEBUG_OUT_OFFSET) 186 #define WLAN_DEBUG_OUT_DATA_MSB (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MSB) 187 #define WLAN_DEBUG_OUT_DATA_LSB (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_LSB) 188 #define WLAN_DEBUG_OUT_DATA_MASK (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MASK) 189 #define AMBA_DEBUG_BUS_OFFSET (scn->targetdef->d_AMBA_DEBUG_BUS_OFFSET) 190 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB \ 191 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB) 192 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB \ 193 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) 194 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK \ 195 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) 196 #define AMBA_DEBUG_BUS_SEL_MSB (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MSB) 197 #define AMBA_DEBUG_BUS_SEL_LSB (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_LSB) 198 #define AMBA_DEBUG_BUS_SEL_MASK (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MASK) 199 #define CE_WRAPPER_DEBUG_OFFSET \ 200 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_OFFSET) 201 #define CE_WRAPPER_DEBUG_SEL_MSB \ 202 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MSB) 203 #define CE_WRAPPER_DEBUG_SEL_LSB \ 204 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_LSB) 205 #define CE_WRAPPER_DEBUG_SEL_MASK \ 206 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MASK) 207 #define CE_DEBUG_OFFSET (scn->target_ce_def->d_CE_DEBUG_OFFSET) 208 #define CE_DEBUG_SEL_MSB (scn->target_ce_def->d_CE_DEBUG_SEL_MSB) 209 #define CE_DEBUG_SEL_LSB (scn->target_ce_def->d_CE_DEBUG_SEL_LSB) 210 #define CE_DEBUG_SEL_MASK (scn->target_ce_def->d_CE_DEBUG_SEL_MASK) 211 #define HOST_IE_ADDRESS (scn->target_ce_def->d_HOST_IE_ADDRESS) 212 #define HOST_IE_REG1_CE_LSB (scn->target_ce_def->d_HOST_IE_REG1_CE_LSB) 213 #define HOST_IE_ADDRESS_2 (scn->target_ce_def->d_HOST_IE_ADDRESS_2) 214 #define HOST_IE_REG2_CE_LSB (scn->target_ce_def->d_HOST_IE_REG2_CE_LSB) 215 #define HOST_IE_ADDRESS_3 (scn->target_ce_def->d_HOST_IE_ADDRESS_3) 216 #define HOST_IE_REG3_CE_LSB (scn->target_ce_def->d_HOST_IE_REG3_CE_LSB) 217 #define HOST_IS_ADDRESS (scn->target_ce_def->d_HOST_IS_ADDRESS) 218 #define HOST_CE_ADDRESS (scn->target_ce_def->d_HOST_CE_ADDRESS) 219 #define HOST_CMEM_ADDRESS (scn->target_ce_def->d_HOST_CMEM_ADDRESS) 220 #define PMM_SCRATCH_BASE (scn->target_ce_def->d_PMM_SCRATCH_BASE) 221 222 #define SRC_WATERMARK_LOW_SET(x) \ 223 (((x) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK) 224 #define SRC_WATERMARK_HIGH_SET(x) \ 225 (((x) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK) 226 #define DST_WATERMARK_LOW_SET(x) \ 227 (((x) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK) 228 #define DST_WATERMARK_HIGH_SET(x) \ 229 (((x) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK) 230 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \ 231 (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \ 232 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) 233 #define CE_CTRL1_DMAX_LENGTH_SET(x) \ 234 (((x) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK) 235 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \ 236 (((x) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \ 237 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) 238 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \ 239 (((x) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \ 240 CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) 241 #define WLAN_DEBUG_INPUT_SEL_SRC_GET(x) \ 242 (((x) & WLAN_DEBUG_INPUT_SEL_SRC_MASK) >> \ 243 WLAN_DEBUG_INPUT_SEL_SRC_LSB) 244 #define WLAN_DEBUG_INPUT_SEL_SRC_SET(x) \ 245 (((x) << WLAN_DEBUG_INPUT_SEL_SRC_LSB) & \ 246 WLAN_DEBUG_INPUT_SEL_SRC_MASK) 247 #define WLAN_DEBUG_CONTROL_ENABLE_GET(x) \ 248 (((x) & WLAN_DEBUG_CONTROL_ENABLE_MASK) >> \ 249 WLAN_DEBUG_CONTROL_ENABLE_LSB) 250 #define WLAN_DEBUG_CONTROL_ENABLE_SET(x) \ 251 (((x) << WLAN_DEBUG_CONTROL_ENABLE_LSB) & \ 252 WLAN_DEBUG_CONTROL_ENABLE_MASK) 253 #define WLAN_DEBUG_OUT_DATA_GET(x) \ 254 (((x) & WLAN_DEBUG_OUT_DATA_MASK) >> WLAN_DEBUG_OUT_DATA_LSB) 255 #define WLAN_DEBUG_OUT_DATA_SET(x) \ 256 (((x) << WLAN_DEBUG_OUT_DATA_LSB) & WLAN_DEBUG_OUT_DATA_MASK) 257 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_GET(x) \ 258 (((x) & AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) >> \ 259 AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) 260 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_SET(x) \ 261 (((x) << AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) & \ 262 AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) 263 #define AMBA_DEBUG_BUS_SEL_GET(x) \ 264 (((x) & AMBA_DEBUG_BUS_SEL_MASK) >> AMBA_DEBUG_BUS_SEL_LSB) 265 #define AMBA_DEBUG_BUS_SEL_SET(x) \ 266 (((x) << AMBA_DEBUG_BUS_SEL_LSB) & AMBA_DEBUG_BUS_SEL_MASK) 267 #define CE_WRAPPER_DEBUG_SEL_GET(x) \ 268 (((x) & CE_WRAPPER_DEBUG_SEL_MASK) >> CE_WRAPPER_DEBUG_SEL_LSB) 269 #define CE_WRAPPER_DEBUG_SEL_SET(x) \ 270 (((x) << CE_WRAPPER_DEBUG_SEL_LSB) & CE_WRAPPER_DEBUG_SEL_MASK) 271 #define CE_DEBUG_SEL_GET(x) (((x) & CE_DEBUG_SEL_MASK) >> CE_DEBUG_SEL_LSB) 272 #define CE_DEBUG_SEL_SET(x) (((x) << CE_DEBUG_SEL_LSB) & CE_DEBUG_SEL_MASK) 273 #define HOST_IE_REG1_CE_BIT(_ce_id) (1 << (_ce_id + HOST_IE_REG1_CE_LSB)) 274 #define HOST_IE_REG2_CE_BIT(_ce_id) (1 << (_ce_id + HOST_IE_REG2_CE_LSB)) 275 #define HOST_IE_REG3_CE_BIT(_ce_id) (1 << (_ce_id + HOST_IE_REG3_CE_LSB)) 276 277 uint32_t DEBUG_CE_SRC_RING_READ_IDX_GET(struct hif_softc *scn, 278 uint32_t CE_ctrl_addr); 279 uint32_t DEBUG_CE_DEST_RING_READ_IDX_GET(struct hif_softc *scn, 280 uint32_t CE_ctrl_addr); 281 282 #define BITS0_TO_31(val) ((uint32_t)((uint64_t)(val)\ 283 & (uint64_t)(0xFFFFFFFF))) 284 #define BITS32_TO_35(val) ((uint32_t)(((uint64_t)(val)\ 285 & (uint64_t)(0xF00000000))>>32)) 286 287 #ifdef WLAN_40BIT_ADDRESSING_SUPPORT 288 #define RRI_ON_DDR_PADDR_HIGH(val) (uint32_t)(((uint64_t)(val) >> 32) & 0xFF) 289 #else 290 #define RRI_ON_DDR_PADDR_HIGH(val) BITS32_TO_35(val) 291 #endif 292 #define RRI_ON_DDR_PADDR_LOW(val) BITS0_TO_31(val) 293 294 #ifdef WLAN_64BIT_DATA_SUPPORT 295 #define VADDR_FOR_CE(scn, CE_ctrl_addr)\ 296 (((uint64_t *)((scn)->vaddr_rri_on_ddr)) + COPY_ENGINE_ID(CE_ctrl_addr)) 297 #define SRRI_FROM_DDR_ADDR(addr) ((*(addr)) & 0xFFFF) 298 #define DRRI_FROM_DDR_ADDR(addr) (((*(addr)) >> 32) & 0xFFFF) 299 #else 300 #define VADDR_FOR_CE(scn, CE_ctrl_addr)\ 301 (((uint32_t *)((scn)->vaddr_rri_on_ddr)) + COPY_ENGINE_ID(CE_ctrl_addr)) 302 #define SRRI_FROM_DDR_ADDR(addr) ((*(addr)) & 0xFFFF) 303 #define DRRI_FROM_DDR_ADDR(addr) (((*(addr))>>16) & 0xFFFF) 304 #endif 305 306 #define CE_SRC_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \ 307 A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS) 308 #define CE_DEST_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \ 309 A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_DRRI_ADDRESS) 310 311 #ifdef ADRASTEA_RRI_ON_DDR 312 #ifdef SHADOW_REG_DEBUG 313 #define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ 314 DEBUG_CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr) 315 #define CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ 316 DEBUG_CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr) 317 #else 318 #define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ 319 SRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr)) 320 #define CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ 321 DRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr)) 322 #endif 323 324 #ifndef QCA_WIFI_WCN6450 325 unsigned int hif_get_src_ring_read_index(struct hif_softc *scn, 326 uint32_t CE_ctrl_addr); 327 unsigned int hif_get_dst_ring_read_index(struct hif_softc *scn, 328 uint32_t CE_ctrl_addr); 329 330 #define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr)\ 331 hif_get_src_ring_read_index(scn, CE_ctrl_addr) 332 #define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\ 333 hif_get_dst_ring_read_index(scn, CE_ctrl_addr) 334 #else 335 #define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr)\ 336 CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr) 337 #define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\ 338 CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr) 339 #endif 340 #else 341 #define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr) \ 342 CE_SRC_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) 343 #define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\ 344 CE_DEST_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) 345 346 /* 347 * if RRI on DDR is not enabled, get idx from ddr defaults to 348 * using the register value & force wake must be used for 349 * non interrupt processing. 350 */ 351 #define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ 352 A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS) 353 #endif 354 355 #ifdef WLAN_40BIT_ADDRESSING_SUPPORT 356 #define CE_RING_BASE_ADDR_HIGH_MASK 0xFF 357 #else 358 #define CE_RING_BASE_ADDR_HIGH_MASK 0x1F 359 #endif 360 361 #define CE_SRC_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \ 362 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_BA_ADDRESS, (addr)) 363 364 #define CE_SRC_RING_BASE_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \ 365 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_BA_ADDRESS_HIGH, (addr)) 366 367 #define CE_SRC_RING_BASE_ADDR_HIGH_GET(scn, CE_ctrl_addr) \ 368 A_TARGET_READ(scn, (CE_ctrl_addr) + SR_BA_ADDRESS_HIGH) 369 370 #define CE_SRC_RING_SZ_SET(scn, CE_ctrl_addr, n) \ 371 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_SIZE_ADDRESS, (n)) 372 373 #define CE_IDX_UPD_EN_DMAX_LEN_SET(scn, CE_ctrl_addr, n) \ 374 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \ 375 ((A_TARGET_READ(scn, (CE_ctrl_addr) + \ 376 CE_CTRL1_ADDRESS) & ~CE_CTRL1_DMAX_LENGTH_MASK) | \ 377 CE_CTRL1_DMAX_LENGTH_SET(n) | CE_CTRL1_IDX_UPD_EN)) 378 379 #define CE_SRC_RING_DMAX_SET(scn, CE_ctrl_addr, n) \ 380 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \ 381 (A_TARGET_READ(scn, (CE_ctrl_addr) + \ 382 CE_CTRL1_ADDRESS) & ~CE_CTRL1_DMAX_LENGTH_MASK) | \ 383 CE_CTRL1_DMAX_LENGTH_SET(n)) 384 385 #define CE_IDX_UPD_EN_SET(scn, CE_ctrl_addr) \ 386 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \ 387 (A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \ 388 | CE_CTRL1_IDX_UPD_EN)) 389 390 #define CE_CMD_REGISTER_GET(scn, CE_ctrl_addr) \ 391 A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CMD_REGISTER) 392 393 #define CE_CMD_REGISTER_SET(scn, CE_ctrl_addr, n) \ 394 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CMD_REGISTER, n) 395 396 #define CE_MSI_ADDR_LOW_SET(scn, CE_ctrl_addr, addr) \ 397 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS, (addr)) 398 399 #define CE_MSI_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \ 400 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS_HIGH, (addr)) 401 402 #define CE_MSI_ADDR_HIGH_GET(scn, CE_ctrl_addr) \ 403 A_TARGET_READ(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS_HIGH) 404 405 #define CE_MSI_DATA_SET(scn, CE_ctrl_addr, data) \ 406 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_DATA, (data)) 407 408 #define CE_MSI_EN_SET(scn, CE_ctrl_addr) \ 409 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \ 410 (A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \ 411 | CE_MSI_ENABLE_BIT)) 412 413 #define CE_SRC_BATCH_TIMER_THRESHOLD 0 414 #define CE_SRC_BATCH_COUNTER_THRESHOLD 1 415 #define CE_DST_BATCH_TIMER_THRESHOLD 512 416 #define CE_DST_BATCH_COUNTER_THRESHOLD 0 417 418 #define CE_SRC_BATCH_TIMER_THRESH_MASK \ 419 (scn->target_ce_def->d_CE_SRC_BATCH_TIMER_THRESH_MASK) 420 #define CE_SRC_BATCH_TIMER_THRESH_LSB \ 421 (scn->target_ce_def->d_CE_SRC_BATCH_TIMER_THRESH_LSB) 422 #define CE_SRC_BATCH_COUNTER_THRESH_MASK \ 423 (scn->target_ce_def->d_CE_SRC_BATCH_COUNTER_THRESH_MASK) 424 #define CE_SRC_BATCH_COUNTER_THRESH_LSB \ 425 (scn->target_ce_def->d_CE_SRC_BATCH_COUNTER_THRESH_LSB) 426 #define CE_DST_BATCH_TIMER_THRESH_MASK \ 427 (scn->target_ce_def->d_CE_DST_BATCH_TIMER_THRESH_MASK) 428 #define CE_DST_BATCH_TIMER_THRESH_LSB \ 429 (scn->target_ce_def->d_CE_DST_BATCH_TIMER_THRESH_LSB) 430 #define CE_DST_BATCH_COUNTER_THRESH_MASK \ 431 (scn->target_ce_def->d_CE_DST_BATCH_COUNTER_THRESH_MASK) 432 #define CE_DST_BATCH_COUNTER_THRESH_LSB \ 433 (scn->target_ce_def->d_CE_DST_BATCH_COUNTER_THRESH_LSB) 434 435 #define CE_CHANNEL_SRC_BATCH_TIMER_INT_SETUP_GET(scn, CE_ctrl_addr) \ 436 A_TARGET_READ(scn, (CE_ctrl_addr) + CE_SRC_BATCH_TIMER_INT_SETUP) 437 #define CE_CHANNEL_DST_BATCH_TIMER_INT_SETUP_GET(scn, CE_ctrl_addr) \ 438 A_TARGET_READ(scn, (CE_ctrl_addr) + CE_DST_BATCH_TIMER_INT_SETUP) 439 440 #define CE_CHANNEL_SRC_BATCH_TIMER_INT_SETUP(scn, CE_ctrl_addr, data) \ 441 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_SRC_BATCH_TIMER_INT_SETUP, data) 442 #define CE_CHANNEL_DST_BATCH_TIMER_INT_SETUP(scn, CE_ctrl_addr, data) \ 443 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_DST_BATCH_TIMER_INT_SETUP, data) 444 445 #define HOST_IE_SRC_TIMER_BATCH_MASK \ 446 (scn->target_ce_def->d_HOST_IE_SRC_TIMER_BATCH_MASK) 447 #define HOST_IE_DST_TIMER_BATCH_MASK \ 448 (scn->target_ce_def->d_HOST_IE_DST_TIMER_BATCH_MASK) 449 450 #define CE_CHANNEL_SRC_TIMER_BATCH_INT_EN(scn, CE_ctrl_addr) \ 451 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \ 452 A_TARGET_READ(scn, \ 453 (CE_ctrl_addr) + HOST_IE_ADDRESS) | \ 454 HOST_IE_SRC_TIMER_BATCH_MASK) 455 #define CE_CHANNEL_DST_TIMER_BATCH_INT_EN(scn, CE_ctrl_addr) \ 456 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \ 457 A_TARGET_READ(scn, \ 458 (CE_ctrl_addr) + HOST_IE_ADDRESS) | \ 459 HOST_IE_DST_TIMER_BATCH_MASK) 460 461 #define CE_CTRL_REGISTER1_SET(scn, CE_ctrl_addr, val) \ 462 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, val) 463 464 #define CE_CTRL_REGISTER1_GET(scn, CE_ctrl_addr) \ 465 A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS) 466 467 #define CE_SRC_RING_BYTE_SWAP_SET(scn, CE_ctrl_addr, n) \ 468 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \ 469 (A_TARGET_READ(scn, \ 470 (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \ 471 & ~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) | \ 472 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n)) 473 474 #define CE_DEST_RING_BYTE_SWAP_SET(scn, CE_ctrl_addr, n) \ 475 A_TARGET_WRITE(scn, (CE_ctrl_addr)+CE_CTRL1_ADDRESS, \ 476 (A_TARGET_READ(scn, \ 477 (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \ 478 & ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) | \ 479 CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n)) 480 481 482 #define CE_DEST_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \ 483 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_BA_ADDRESS, (addr)) 484 485 #define CE_DEST_RING_BASE_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \ 486 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_BA_ADDRESS_HIGH, (addr)) 487 488 #define CE_DEST_RING_BASE_ADDR_HIGH_GET(scn, CE_ctrl_addr) \ 489 A_TARGET_READ(scn, (CE_ctrl_addr) + DR_BA_ADDRESS_HIGH) 490 491 #define CE_DEST_RING_SZ_SET(scn, CE_ctrl_addr, n) \ 492 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_SIZE_ADDRESS, (n)) 493 494 #define CE_SRC_RING_HIGHMARK_SET(scn, CE_ctrl_addr, n) \ 495 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS, \ 496 (A_TARGET_READ(scn, \ 497 (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS) \ 498 & ~SRC_WATERMARK_HIGH_MASK) | \ 499 SRC_WATERMARK_HIGH_SET(n)) 500 501 #define CE_SRC_RING_LOWMARK_SET(scn, CE_ctrl_addr, n) \ 502 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS, \ 503 (A_TARGET_READ(scn, \ 504 (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS) \ 505 & ~SRC_WATERMARK_LOW_MASK) | \ 506 SRC_WATERMARK_LOW_SET(n)) 507 508 #define CE_DEST_RING_HIGHMARK_SET(scn, CE_ctrl_addr, n) \ 509 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WATERMARK_ADDRESS, \ 510 (A_TARGET_READ(scn, \ 511 (CE_ctrl_addr) + DST_WATERMARK_ADDRESS) \ 512 & ~DST_WATERMARK_HIGH_MASK) | \ 513 DST_WATERMARK_HIGH_SET(n)) 514 515 #define CE_DEST_RING_LOWMARK_SET(scn, CE_ctrl_addr, n) \ 516 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WATERMARK_ADDRESS, \ 517 (A_TARGET_READ(scn, \ 518 (CE_ctrl_addr) + DST_WATERMARK_ADDRESS) \ 519 & ~DST_WATERMARK_LOW_MASK) | \ 520 DST_WATERMARK_LOW_SET(n)) 521 522 #define CE_COPY_COMPLETE_INTR_ENABLE(scn, CE_ctrl_addr) \ 523 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \ 524 A_TARGET_READ(scn, \ 525 (CE_ctrl_addr) + HOST_IE_ADDRESS) | \ 526 HOST_IE_COPY_COMPLETE_MASK) 527 528 #define CE_COPY_COMPLETE_INTR_DISABLE(scn, CE_ctrl_addr) \ 529 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \ 530 A_TARGET_READ(scn, \ 531 (CE_ctrl_addr) + HOST_IE_ADDRESS) \ 532 & ~HOST_IE_COPY_COMPLETE_MASK) 533 534 #define CE_BASE_ADDRESS(CE_id) \ 535 CE0_BASE_ADDRESS + ((CE1_BASE_ADDRESS - \ 536 CE0_BASE_ADDRESS)*(CE_id)) 537 538 #define CE_WATERMARK_INTR_ENABLE(scn, CE_ctrl_addr) \ 539 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \ 540 A_TARGET_READ(scn, \ 541 (CE_ctrl_addr) + HOST_IE_ADDRESS) | \ 542 CE_WATERMARK_MASK) 543 544 #define CE_WATERMARK_INTR_DISABLE(scn, CE_ctrl_addr) \ 545 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \ 546 A_TARGET_READ(scn, \ 547 (CE_ctrl_addr) + HOST_IE_ADDRESS) \ 548 & ~CE_WATERMARK_MASK) 549 550 #define CE_ERROR_INTR_ENABLE(scn, CE_ctrl_addr) \ 551 A_TARGET_WRITE(scn, (CE_ctrl_addr) + MISC_IE_ADDRESS, \ 552 A_TARGET_READ(scn, \ 553 (CE_ctrl_addr) + MISC_IE_ADDRESS) | CE_ERROR_MASK) 554 555 #define CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr) \ 556 A_TARGET_READ(scn, (CE_ctrl_addr) + MISC_IS_ADDRESS) 557 558 #define CE_ENGINE_INT_STATUS_GET(scn, CE_ctrl_addr) \ 559 A_TARGET_READ(scn, (CE_ctrl_addr) + HOST_IS_ADDRESS) 560 561 #define CE_ENGINE_INT_STATUS_CLEAR(scn, CE_ctrl_addr, mask) \ 562 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IS_ADDRESS, (mask)) 563 564 #define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \ 565 HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \ 566 HOST_IS_DST_RING_LOW_WATERMARK_MASK | \ 567 HOST_IS_DST_RING_HIGH_WATERMARK_MASK) 568 569 #define CE_ERROR_MASK (MISC_IS_AXI_ERR_MASK | \ 570 MISC_IS_DST_ADDR_ERR_MASK | \ 571 MISC_IS_SRC_LEN_ERR_MASK | \ 572 MISC_IS_DST_MAX_LEN_VIO_MASK | \ 573 MISC_IS_DST_RING_OVERFLOW_MASK | \ 574 MISC_IS_SRC_RING_OVERFLOW_MASK) 575 576 #define CE_SRC_RING_TO_DESC(baddr, idx) \ 577 (&(((struct CE_src_desc *)baddr)[idx])) 578 #define CE_DEST_RING_TO_DESC(baddr, idx) \ 579 (&(((struct CE_dest_desc *)baddr)[idx])) 580 581 /* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */ 582 #define CE_RING_DELTA(nentries_mask, fromidx, toidx) \ 583 (((int)(toidx)-(int)(fromidx)) & (nentries_mask)) 584 585 #define CE_RING_IDX_INCR(nentries_mask, idx) \ 586 (((idx) + 1) & (nentries_mask)) 587 588 #define CE_RING_IDX_ADD(nentries_mask, idx, num) \ 589 (((idx) + (num)) & (nentries_mask)) 590 591 #define CE_INTERRUPT_SUMMARY(scn) \ 592 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \ 593 A_TARGET_READ(scn, CE_WRAPPER_BASE_ADDRESS + \ 594 CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)) 595 596 #define READ_CE_DDR_ADDRESS_FOR_RRI_LOW(scn) \ 597 (A_TARGET_READ(scn, \ 598 CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_LOW)) 599 600 #define READ_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn) \ 601 (A_TARGET_READ(scn, \ 602 CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_HIGH)) 603 604 #define WRITE_CE_DDR_ADDRESS_FOR_RRI_LOW(scn, val) \ 605 (A_TARGET_WRITE(scn, \ 606 CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_LOW, \ 607 val)) 608 609 #define WRITE_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn, val) \ 610 (A_TARGET_WRITE(scn, \ 611 CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_HIGH, \ 612 val)) 613 614 /*Macro to increment CE packet errors*/ 615 #define OL_ATH_CE_PKT_ERROR_COUNT_INCR(_scn, _ce_ecode) \ 616 do { if (_ce_ecode == CE_RING_DELTA_FAIL) \ 617 (_scn->pkt_stats.ce_ring_delta_fail_count) \ 618 += 1; } while (0) 619 620 /* Given a Copy Engine's ID, determine the interrupt number for that 621 * copy engine's interrupts. 622 */ 623 #define CE_ID_TO_INUM(id) (A_INUM_CE0_COPY_COMP_BASE + (id)) 624 #define CE_INUM_TO_ID(inum) ((inum) - A_INUM_CE0_COPY_COMP_BASE) 625 #define CE0_BASE_ADDRESS (scn->target_ce_def->d_CE0_BASE_ADDRESS) 626 #define CE1_BASE_ADDRESS (scn->target_ce_def->d_CE1_BASE_ADDRESS) 627 628 629 #ifdef ADRASTEA_SHADOW_REGISTERS 630 #define NUM_SHADOW_REGISTERS 24 631 u32 shadow_sr_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr); 632 u32 shadow_dst_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr); 633 634 #define CE_SRC_WR_IDX_OFFSET_GET(scn, CE_ctrl_addr) \ 635 shadow_sr_wr_ind_addr(scn, CE_ctrl_addr) 636 #define CE_DST_WR_IDX_OFFSET_GET(scn, CE_ctrl_addr) \ 637 shadow_dst_wr_ind_addr(scn, CE_ctrl_addr) 638 #else 639 #define CE_SRC_WR_IDX_OFFSET_GET(scn, CE_ctrl_addr) \ 640 CE_ctrl_addr + SR_WR_INDEX_ADDRESS 641 #define CE_DST_WR_IDX_OFFSET_GET(scn, CE_ctrl_addr) \ 642 CE_ctrl_addr + DST_WR_INDEX_ADDRESS 643 #endif 644 645 #if defined(FEATURE_HIF_DELAYED_REG_WRITE) 646 #define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ 647 A_TARGET_DELAYED_REG_WRITE(scn, CE_ctrl_addr, n) 648 #define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ 649 A_TARGET_DELAYED_REG_WRITE(scn, CE_ctrl_addr, n) 650 #elif defined(ADRASTEA_SHADOW_REGISTERS) 651 #define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ 652 A_TARGET_WRITE(scn, shadow_sr_wr_ind_addr(scn, CE_ctrl_addr), n) 653 #define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ 654 A_TARGET_WRITE(scn, shadow_dst_wr_ind_addr(scn, CE_ctrl_addr), n) 655 #else 656 #define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ 657 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_WR_INDEX_ADDRESS, (n)) 658 #define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ 659 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WR_INDEX_ADDRESS, (n)) 660 #endif 661 662 /* The write index read is only needed during initialization because 663 * we keep track of the index that was last written. Thus the register 664 * is the only hardware supported location to read the initial value from. 665 */ 666 #define CE_SRC_RING_WRITE_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \ 667 A_TARGET_READ(scn, (CE_ctrl_addr) + SR_WR_INDEX_ADDRESS) 668 #define CE_DEST_RING_WRITE_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \ 669 A_TARGET_READ(scn, (CE_ctrl_addr) + DST_WR_INDEX_ADDRESS) 670 671 #endif /* __CE_REG_H__ */ 672