xref: /wlan-driver/qca-wifi-host-cmn/wmi/inc/wmi_unified_dbr_param.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2016-2018, 2020 The Linux Foundation. All rights reserved.
3  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for
6  * any purpose with or without fee is hereby granted, provided that the
7  * above copyright notice and this permission notice appear in all
8  * copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17  * PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #ifndef _WMI_UNIFIED_DBR_PARAM_H_
21 #define _WMI_UNIFIED_DBR_PARAM_H_
22 
23 #define WMI_HOST_DBR_RING_ADDR_LO_S 0
24 #define WMI_HOST_DBR_RING_ADDR_LO_M 0xffffffff
25 #define WMI_HOST_DBR_RING_ADDR_LO \
26 	(WMI_HOST_DBR_RING_ADDR_LO_M << WMI_HOST_DBR_RING_ADDR_LO_S)
27 
28 #define WMI_HOST_DBR_RING_ADDR_LO_GET(dword) \
29 			WMI_HOST_F_MS(dword, WMI_HOST_DBR_RING_ADDR_LO)
30 #define WMI_HOST_DBR_RING_ADDR_LO_SET(dword, val) \
31 			WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_RING_ADDR_LO)
32 
33 #define WMI_HOST_DBR_RING_ADDR_HI_S 0
34 #define WMI_HOST_DBR_RING_ADDR_HI_M 0xf
35 #define WMI_HOST_DBR_RING_ADDR_HI \
36 	(WMI_HOST_DBR_RING_ADDR_HI_M << WMI_HOST_DBR_RING_ADDR_HI_S)
37 
38 #define WMI_HOST_DBR_RING_ADDR_HI_GET(dword) \
39 			WMI_HOST_F_MS(dword, WMI_HOST_DBR_RING_ADDR_HI)
40 #define WMI_HOST_DBR_RING_ADDR_HI_SET(dword, val) \
41 			WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_RING_ADDR_HI)
42 
43 #define WMI_HOST_DBR_DATA_ADDR_LO_S 0
44 #define WMI_HOST_DBR_DATA_ADDR_LO_M 0xffffffff
45 #define WMI_HOST_DBR_DATA_ADDR_LO \
46 	(WMI_HOST_DBR_DATA_ADDR_LO_M << WMI_HOST_DBR_DATA_ADDR_LO_S)
47 
48 #define WMI_HOST_DBR_DATA_ADDR_LO_GET(dword) \
49 			WMI_HOST_F_MS(dword, WMI_HOST_DBR_DATA_ADDR_LO)
50 #define WMI_HOST_DBR_DATA_ADDR_LO_SET(dword, val) \
51 			WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_DATA_ADDR_LO)
52 
53 #define WMI_HOST_DBR_DATA_ADDR_HI_S 0
54 #define WMI_HOST_DBR_DATA_ADDR_HI_M 0xf
55 #define WMI_HOST_DBR_DATA_ADDR_HI \
56 	(WMI_HOST_DBR_DATA_ADDR_HI_M << WMI_HOST_DBR_DATA_ADDR_HI_S)
57 
58 #define WMI_HOST_DBR_DATA_ADDR_HI_GET(dword) \
59 			WMI_HOST_F_MS(dword, WMI_HOST_DBR_DATA_ADDR_HI)
60 #define WMI_HOST_DBR_DATA_ADDR_HI_SET(dword, val) \
61 			WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_DATA_ADDR_HI)
62 
63 #define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_S 12
64 #define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_M 0x7ffff
65 #define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA \
66 	(WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_M << \
67 	 WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_S)
68 
69 #define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_GET(dword) \
70 		WMI_HOST_F_MS(dword, WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA)
71 #define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_SET(dword, val) \
72 		WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA)
73 
74 #define WMI_HOST_MAX_NUM_CHAINS 8
75 
76 /**
77  * struct direct_buf_rx_rsp: direct buffer rx response structure
78  *
79  * @pdev_id: Index of the pdev for which response is received
80  * @mod_id: Index of the module for which respone is received
81  * @num_buf_release_entry: Number of buffers released through event
82  * @num_meta_data_entry: Number of meta data released
83  * @num_cv_meta_data_entry: Number of cv meta data released
84  * @num_cqi_meta_data_entry: Number of cqi meta data released
85  * @dbr_entries: Pointer to direct buffer rx entry struct
86  */
87 struct direct_buf_rx_rsp {
88 	uint32_t pdev_id;
89 	uint32_t mod_id;
90 	uint32_t num_buf_release_entry;
91 	uint32_t num_meta_data_entry;
92 	uint32_t num_cv_meta_data_entry;
93 	uint32_t num_cqi_meta_data_entry;
94 	struct direct_buf_rx_entry *dbr_entries;
95 };
96 
97 /**
98  * struct direct_buf_rx_cfg_req: direct buffer rx config request structure
99  *
100  * @pdev_id: Index of the pdev for which response is received
101  * @mod_id: Index of the module for which respone is received
102  * @base_paddr_lo: Lower 32bits of ring base address
103  * @base_paddr_hi: Higher 32bits of ring base address
104  * @head_idx_paddr_lo: Lower 32bits of head idx register address
105  * @head_idx_paddr_hi: Higher 32bits of head idx register address
106  * @tail_idx_paddr_lo: Lower 32bits of tail idx register address
107  * @tail_idx_paddr_hi: Higher 32bits of tail idx register address
108  * @buf_size: Size of the buffer for each pointer in the ring
109  * @num_elems: Number of pointers allocated and part of the source ring
110  * @event_timeout_ms:
111  * @num_resp_per_event:
112  */
113 struct direct_buf_rx_cfg_req {
114 	uint32_t pdev_id;
115 	uint32_t mod_id;
116 	uint32_t base_paddr_lo;
117 	uint32_t base_paddr_hi;
118 	uint32_t head_idx_paddr_lo;
119 	uint32_t head_idx_paddr_hi;
120 	uint32_t tail_idx_paddr_hi;
121 	uint32_t tail_idx_paddr_lo;
122 	uint32_t buf_size;
123 	uint32_t num_elems;
124 	uint32_t event_timeout_ms;
125 	uint32_t num_resp_per_event;
126 };
127 
128 /**
129  * struct direct_buf_rx_metadata: direct buffer metadata
130  *
131  * @noisefloor: noisefloor
132  * @reset_delay: reset delay
133  * @cfreq1: center frequency 1
134  * @cfreq2: center frequency 2
135  * @ch_width: channel width
136  */
137 struct direct_buf_rx_metadata {
138 	int32_t noisefloor[WMI_HOST_MAX_NUM_CHAINS];
139 	uint32_t reset_delay;
140 	uint32_t cfreq1;
141 	uint32_t cfreq2;
142 	uint32_t ch_width;
143 };
144 
145 /**
146  * struct direct_buf_rx_cv_metadata: direct buffer metadata for TxBF CV upload
147  *
148  * @is_valid: Set cv metadata is valid,
149  *            false if sw_peer_id is invalid or FCS error
150  * @fb_type: Feedback type, 0 for SU 1 for MU
151  * @asnr_len: Average SNR length
152  * @asnr_offset: Average SNR offset
153  * @dsnr_len: Delta SNR length
154  * @dsnr_offset: Delta SNR offset
155  * @peer_mac: Peer macaddr
156  * @fb_params: Feedback params, [1:0] Nc [3:2] nss_num
157  */
158 struct direct_buf_rx_cv_metadata {
159 	uint32_t is_valid;
160 	uint32_t fb_type;
161 	uint16_t asnr_len;
162 	uint16_t asnr_offset;
163 	uint16_t dsnr_len;
164 	uint16_t dsnr_offset;
165 	struct qdf_mac_addr peer_mac;
166 	uint32_t fb_params;
167 };
168 
169 /*
170  * In CQI data buffer, each user CQI data will be stored
171  * in a fixed offset of 64 locations from each other,
172  * and each location corresponds to 64-bit length.
173  */
174 #define CQI_USER_DATA_LENGTH      (64 * 8)
175 #define CQI_USER_DATA_OFFSET(idx) ((idx) * CQI_USER_DATA_LENGTH)
176 #define MAX_NUM_CQI_USERS         3
177 /*
178  * struct direct_buf_rx_cqi_per_user_info: Per user CQI data
179  *
180  * @asnr_len: Average SNR length
181  * @asnr_offset: Average SNR offset
182  * @fb_params: Feedback params, [1:0] Nc
183  * @peer_mac: Peer macaddr
184  */
185 struct direct_buf_rx_cqi_per_user_info {
186 	uint16_t asnr_len;
187 	uint16_t asnr_offset;
188 	uint32_t fb_params;
189 	struct qdf_mac_addr peer_mac;
190 };
191 
192 /**
193  * struct direct_buf_rx_cqi_metadata: direct buffer metadata for CQI upload
194  *
195  * @num_users: Number of user info in a metadta buffer
196  * @is_valid: Set cqi metadata is valid,
197  *            false if sw_peer_id is invalid or FCS error
198  * @fb_type: Feedback type, 0 for SU 1 for MU 2 for CQI
199  * @fb_params: Feedback params
200  *	[0] is_valid0
201  *	[1] is_valid1
202  *	[2] is_valid2
203  *	[4:3] Nc0
204  *	[5:4] Nc1
205  *	[6:5] Nc2
206  * @user_info: Per user CQI info
207  */
208 struct direct_buf_rx_cqi_metadata {
209 	uint8_t num_users;
210 	uint32_t is_valid;
211 	uint32_t fb_type;
212 	uint32_t fb_params;
213 	struct direct_buf_rx_cqi_per_user_info user_info[MAX_NUM_CQI_USERS];
214 };
215 
216 /**
217  * struct direct_buf_rx_entry: direct buffer rx release entry structure
218  *
219  * @paddr_lo: LSB 32-bits of the buffer
220  * @paddr_hi: MSB 32-bits of the buffer
221  * @len: Length of the buffer
222  */
223 struct direct_buf_rx_entry {
224 	uint32_t paddr_lo;
225 	uint32_t paddr_hi;
226 	uint32_t len;
227 };
228 
229 #endif /* _WMI_UNIFIED_DBR_PARAM_H_ */
230