Searched refs:hostdef (Results 1 – 13 of 13) sorted by relevance
247 scn->hostdef = &ar6320v2_hostdef; in hif_register_tbl_attach()250 scn->hostdef = &adrastea_hostdef; in hif_register_tbl_attach()254 scn->hostdef = &genoa_hostdef; in hif_register_tbl_attach()259 scn->hostdef = AR6002_HOSTdef; in hif_register_tbl_attach()264 scn->hostdef = AR6003_HOSTdef; in hif_register_tbl_attach()269 scn->hostdef = AR6004_HOSTdef; in hif_register_tbl_attach()274 scn->hostdef = AR9888_HOSTdef; in hif_register_tbl_attach()279 scn->hostdef = AR9888V2_HOSTdef; in hif_register_tbl_attach()284 scn->hostdef = AR900B_HOSTdef; in hif_register_tbl_attach()289 scn->hostdef = QCA9984_HOSTdef; in hif_register_tbl_attach()[all …]
384 struct hostdef_s *hostdef; member
452 #define A_SOC_PCIE_PCIE_BAR0_START (scn->hostdef->d_A_SOC_PCIE_PCIE_BAR0_START)453 #define DESC_DATA_FLAG_MASK (scn->hostdef->d_DESC_DATA_FLAG_MASK)454 #define MUX_ID_MASK (scn->hostdef->d_MUX_ID_MASK)455 #define TRANSACTION_ID_MASK (scn->hostdef->d_TRANSACTION_ID_MASK)456 #define HOST_CE_COUNT (scn->hostdef->d_HOST_CE_COUNT)457 #define ENABLE_MSI (scn->hostdef->d_ENABLE_MSI)459 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB)461 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK)462 #define INT_STATUS_ENABLE_CPU_LSB (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB)463 #define INT_STATUS_ENABLE_CPU_MASK (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK)[all …]
449 #define A_SOC_PCIE_PCIE_BAR0_START (scn->hostdef->d_A_SOC_PCIE_PCIE_BAR0_START)450 #define DESC_DATA_FLAG_MASK (scn->hostdef->d_DESC_DATA_FLAG_MASK)451 #define MUX_ID_MASK (scn->hostdef->d_MUX_ID_MASK)452 #define TRANSACTION_ID_MASK (scn->hostdef->d_TRANSACTION_ID_MASK)453 #define HOST_CE_COUNT (scn->hostdef->d_HOST_CE_COUNT)454 #define ENABLE_MSI (scn->hostdef->d_ENABLE_MSI)456 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB)458 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK)459 #define INT_STATUS_ENABLE_CPU_LSB (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB)460 #define INT_STATUS_ENABLE_CPU_MASK (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK)[all …]
620 #define DESC_DATA_FLAG_MASK (scn->hostdef->d_DESC_DATA_FLAG_MASK)621 #define MUX_ID_MASK (scn->hostdef->d_MUX_ID_MASK)622 #define TRANSACTION_ID_MASK (scn->hostdef->d_TRANSACTION_ID_MASK)623 #define ENABLE_MSI (scn->hostdef->d_ENABLE_MSI)625 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB)627 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK)628 #define INT_STATUS_ENABLE_CPU_LSB (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB)629 #define INT_STATUS_ENABLE_CPU_MASK (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK)631 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_LSB)633 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_MASK)[all …]
58 scn->hostdef = &ar9888_hostdef; in hif_register_tbl_attach()61 scn->hostdef = &ar6320_hostdef; in hif_register_tbl_attach()64 scn->hostdef = &ar6320v2_hostdef; in hif_register_tbl_attach()
53 struct hostdef_s *hostdef; member
978 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB)980 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK)982 (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB)984 (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK)986 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_LSB)988 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_MASK)990 (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_LSB)992 (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_MASK)994 (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)996 (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)[all …]
49 scn->hostdef = &ar9888_hostdef; in hif_register_tbl_attach()52 scn->hostdef = &ar6320_hostdef; in hif_register_tbl_attach()55 scn->hostdef = &ar6320v2_hostdef; in hif_register_tbl_attach()
440 if (!scn->hostdef && !scn->targetdef) { in hif_usb_reg_tbl_attach()
343 scn->hostdef = ol_sc->hostdef; in hif_sdio_probe()
341 if (!scn->hostdef) { in hif_sdio_quirk_mod_strength()
533 if (!scn->hostdef) in hif_pci_device_reset()