xref: /wlan-driver/fw-api/fw/rtc_soc_reg.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
3  *
4  * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
5  *
6  *
7  * Permission to use, copy, modify, and/or distribute this software for
8  * any purpose with or without fee is hereby granted, provided that the
9  * above copyright notice and this permission notice appear in all
10  * copies.
11  *
12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
13  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
14  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
15  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
16  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
17  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
18  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
19  * PERFORMANCE OF THIS SOFTWARE.
20  */
21 
22 /*
23  * This file was originally distributed by Qualcomm Atheros, Inc.
24  * under proprietary terms before Copyright ownership was assigned
25  * to the Linux Foundation.
26  */
27 
28 #ifndef _RTC_SOC_REG_REG_H_
29 #define _RTC_SOC_REG_REG_H_
30 
31 #define SOC_RESET_CONTROL_ADDRESS                0x00000000
32 #define SOC_RESET_CONTROL_OFFSET                 0x00000000
33 #define SOC_RESET_CONTROL_SPI2_RST_MSB           30
34 #define SOC_RESET_CONTROL_SPI2_RST_LSB           30
35 #define SOC_RESET_CONTROL_SPI2_RST_MASK          0x40000000
36 #define SOC_RESET_CONTROL_SPI2_RST_GET(x)        (((x) & SOC_RESET_CONTROL_SPI2_RST_MASK) >> SOC_RESET_CONTROL_SPI2_RST_LSB)
37 #define SOC_RESET_CONTROL_SPI2_RST_SET(x)        (((x) << SOC_RESET_CONTROL_SPI2_RST_LSB) & SOC_RESET_CONTROL_SPI2_RST_MASK)
38 #define SOC_RESET_CONTROL_I2S_1_RST_MSB          29
39 #define SOC_RESET_CONTROL_I2S_1_RST_LSB          29
40 #define SOC_RESET_CONTROL_I2S_1_RST_MASK         0x20000000
41 #define SOC_RESET_CONTROL_I2S_1_RST_GET(x)       (((x) & SOC_RESET_CONTROL_I2S_1_RST_MASK) >> SOC_RESET_CONTROL_I2S_1_RST_LSB)
42 #define SOC_RESET_CONTROL_I2S_1_RST_SET(x)       (((x) << SOC_RESET_CONTROL_I2S_1_RST_LSB) & SOC_RESET_CONTROL_I2S_1_RST_MASK)
43 #define SOC_RESET_CONTROL_I2S_1_MBOX_RST_MSB     28
44 #define SOC_RESET_CONTROL_I2S_1_MBOX_RST_LSB     28
45 #define SOC_RESET_CONTROL_I2S_1_MBOX_RST_MASK    0x10000000
46 #define SOC_RESET_CONTROL_I2S_1_MBOX_RST_GET(x)  (((x) & SOC_RESET_CONTROL_I2S_1_MBOX_RST_MASK) >> SOC_RESET_CONTROL_I2S_1_MBOX_RST_LSB)
47 #define SOC_RESET_CONTROL_I2S_1_MBOX_RST_SET(x)  (((x) << SOC_RESET_CONTROL_I2S_1_MBOX_RST_LSB) & SOC_RESET_CONTROL_I2S_1_MBOX_RST_MASK)
48 #define SOC_RESET_CONTROL_I2C_SLAVE_RST_MSB      27
49 #define SOC_RESET_CONTROL_I2C_SLAVE_RST_LSB      27
50 #define SOC_RESET_CONTROL_I2C_SLAVE_RST_MASK     0x08000000
51 #define SOC_RESET_CONTROL_I2C_SLAVE_RST_GET(x)   (((x) & SOC_RESET_CONTROL_I2C_SLAVE_RST_MASK) >> SOC_RESET_CONTROL_I2C_SLAVE_RST_LSB)
52 #define SOC_RESET_CONTROL_I2C_SLAVE_RST_SET(x)   (((x) << SOC_RESET_CONTROL_I2C_SLAVE_RST_LSB) & SOC_RESET_CONTROL_I2C_SLAVE_RST_MASK)
53 #define SOC_RESET_CONTROL_USB_PHY_ARST_MSB       26
54 #define SOC_RESET_CONTROL_USB_PHY_ARST_LSB       26
55 #define SOC_RESET_CONTROL_USB_PHY_ARST_MASK      0x04000000
56 #define SOC_RESET_CONTROL_USB_PHY_ARST_GET(x)    (((x) & SOC_RESET_CONTROL_USB_PHY_ARST_MASK) >> SOC_RESET_CONTROL_USB_PHY_ARST_LSB)
57 #define SOC_RESET_CONTROL_USB_PHY_ARST_SET(x)    (((x) << SOC_RESET_CONTROL_USB_PHY_ARST_LSB) & SOC_RESET_CONTROL_USB_PHY_ARST_MASK)
58 #define SOC_RESET_CONTROL_USB_PHY_RST_MSB        25
59 #define SOC_RESET_CONTROL_USB_PHY_RST_LSB        25
60 #define SOC_RESET_CONTROL_USB_PHY_RST_MASK       0x02000000
61 #define SOC_RESET_CONTROL_USB_PHY_RST_GET(x)     (((x) & SOC_RESET_CONTROL_USB_PHY_RST_MASK) >> SOC_RESET_CONTROL_USB_PHY_RST_LSB)
62 #define SOC_RESET_CONTROL_USB_PHY_RST_SET(x)     (((x) << SOC_RESET_CONTROL_USB_PHY_RST_LSB) & SOC_RESET_CONTROL_USB_PHY_RST_MASK)
63 #define SOC_RESET_CONTROL_USB_RST_MSB            24
64 #define SOC_RESET_CONTROL_USB_RST_LSB            24
65 #define SOC_RESET_CONTROL_USB_RST_MASK           0x01000000
66 #define SOC_RESET_CONTROL_USB_RST_GET(x)         (((x) & SOC_RESET_CONTROL_USB_RST_MASK) >> SOC_RESET_CONTROL_USB_RST_LSB)
67 #define SOC_RESET_CONTROL_USB_RST_SET(x)         (((x) << SOC_RESET_CONTROL_USB_RST_LSB) & SOC_RESET_CONTROL_USB_RST_MASK)
68 #define SOC_RESET_CONTROL_MMAC_RST_MSB           23
69 #define SOC_RESET_CONTROL_MMAC_RST_LSB           23
70 #define SOC_RESET_CONTROL_MMAC_RST_MASK          0x00800000
71 #define SOC_RESET_CONTROL_MMAC_RST_GET(x)        (((x) & SOC_RESET_CONTROL_MMAC_RST_MASK) >> SOC_RESET_CONTROL_MMAC_RST_LSB)
72 #define SOC_RESET_CONTROL_MMAC_RST_SET(x)        (((x) << SOC_RESET_CONTROL_MMAC_RST_LSB) & SOC_RESET_CONTROL_MMAC_RST_MASK)
73 #define SOC_RESET_CONTROL_MDIO_RST_MSB           22
74 #define SOC_RESET_CONTROL_MDIO_RST_LSB           22
75 #define SOC_RESET_CONTROL_MDIO_RST_MASK          0x00400000
76 #define SOC_RESET_CONTROL_MDIO_RST_GET(x)        (((x) & SOC_RESET_CONTROL_MDIO_RST_MASK) >> SOC_RESET_CONTROL_MDIO_RST_LSB)
77 #define SOC_RESET_CONTROL_MDIO_RST_SET(x)        (((x) << SOC_RESET_CONTROL_MDIO_RST_LSB) & SOC_RESET_CONTROL_MDIO_RST_MASK)
78 #define SOC_RESET_CONTROL_GE0_RST_MSB            21
79 #define SOC_RESET_CONTROL_GE0_RST_LSB            21
80 #define SOC_RESET_CONTROL_GE0_RST_MASK           0x00200000
81 #define SOC_RESET_CONTROL_GE0_RST_GET(x)         (((x) & SOC_RESET_CONTROL_GE0_RST_MASK) >> SOC_RESET_CONTROL_GE0_RST_LSB)
82 #define SOC_RESET_CONTROL_GE0_RST_SET(x)         (((x) << SOC_RESET_CONTROL_GE0_RST_LSB) & SOC_RESET_CONTROL_GE0_RST_MASK)
83 #define SOC_RESET_CONTROL_I2S_RST_MSB            20
84 #define SOC_RESET_CONTROL_I2S_RST_LSB            20
85 #define SOC_RESET_CONTROL_I2S_RST_MASK           0x00100000
86 #define SOC_RESET_CONTROL_I2S_RST_GET(x)         (((x) & SOC_RESET_CONTROL_I2S_RST_MASK) >> SOC_RESET_CONTROL_I2S_RST_LSB)
87 #define SOC_RESET_CONTROL_I2S_RST_SET(x)         (((x) << SOC_RESET_CONTROL_I2S_RST_LSB) & SOC_RESET_CONTROL_I2S_RST_MASK)
88 #define SOC_RESET_CONTROL_I2S_MBOX_RST_MSB       19
89 #define SOC_RESET_CONTROL_I2S_MBOX_RST_LSB       19
90 #define SOC_RESET_CONTROL_I2S_MBOX_RST_MASK      0x00080000
91 #define SOC_RESET_CONTROL_I2S_MBOX_RST_GET(x)    (((x) & SOC_RESET_CONTROL_I2S_MBOX_RST_MASK) >> SOC_RESET_CONTROL_I2S_MBOX_RST_LSB)
92 #define SOC_RESET_CONTROL_I2S_MBOX_RST_SET(x)    (((x) << SOC_RESET_CONTROL_I2S_MBOX_RST_LSB) & SOC_RESET_CONTROL_I2S_MBOX_RST_MASK)
93 /* TODO: */
94 #define SOC_RESET_CONTROL_CHECKSUM_ACC_RST_MSB   18
95 #define SOC_RESET_CONTROL_CHECKSUM_ACC_RST_LSB   18
96 #define SOC_RESET_CONTROL_CHECKSUM_ACC_RST_MASK  0x00040000
97 #define SOC_RESET_CONTROL_CHECKSUM_ACC_RST_GET(x) (((x) & SOC_RESET_CONTROL_CHECKSUM_ACC_RST_MASK) >> SOC_RESET_CONTROL_CHECKSUM_ACC_RST_LSB)
98 #define SOC_RESET_CONTROL_CHECKSUM_ACC_RST_SET(x) (((x) << SOC_RESET_CONTROL_CHECKSUM_ACC_RST_LSB) & SOC_RESET_CONTROL_CHECKSUM_ACC_RST_MASK)
99 #define SOC_RESET_CONTROL_CE_RST_MSB             18
100 #define SOC_RESET_CONTROL_CE_RST_LSB             18
101 #define SOC_RESET_CONTROL_CE_RST_MASK            0x00040000
102 #define SOC_RESET_CONTROL_CE_RST_GET(x)          (((x) & SOC_RESET_CONTROL_CE_RST_MASK) >> SOC_RESET_CONTROL_CE_RST_LSB)
103 #define SOC_RESET_CONTROL_CE_RST_SET(x)          (((x) << SOC_RESET_CONTROL_CE_RST_LSB) & SOC_RESET_CONTROL_CE_RST_MASK)
104 #define SOC_RESET_CONTROL_UART2_RST_MSB          17
105 #define SOC_RESET_CONTROL_UART2_RST_LSB          17
106 #define SOC_RESET_CONTROL_UART2_RST_MASK         0x00020000
107 #define SOC_RESET_CONTROL_UART2_RST_GET(x)       (((x) & SOC_RESET_CONTROL_UART2_RST_MASK) >> SOC_RESET_CONTROL_UART2_RST_LSB)
108 #define SOC_RESET_CONTROL_UART2_RST_SET(x)       (((x) << SOC_RESET_CONTROL_UART2_RST_LSB) & SOC_RESET_CONTROL_UART2_RST_MASK)
109 #define SOC_RESET_CONTROL_DEBUG_UART_RST_MSB     16
110 #define SOC_RESET_CONTROL_DEBUG_UART_RST_LSB     16
111 #define SOC_RESET_CONTROL_DEBUG_UART_RST_MASK    0x00010000
112 #define SOC_RESET_CONTROL_DEBUG_UART_RST_GET(x)  (((x) & SOC_RESET_CONTROL_DEBUG_UART_RST_MASK) >> SOC_RESET_CONTROL_DEBUG_UART_RST_LSB)
113 #define SOC_RESET_CONTROL_DEBUG_UART_RST_SET(x)  (((x) << SOC_RESET_CONTROL_DEBUG_UART_RST_LSB) & SOC_RESET_CONTROL_DEBUG_UART_RST_MASK)
114 #define SOC_RESET_CONTROL_CPU_INIT_RESET_MSB     11
115 #define SOC_RESET_CONTROL_CPU_INIT_RESET_LSB     11
116 #define SOC_RESET_CONTROL_CPU_INIT_RESET_MASK    0x00000800
117 #define SOC_RESET_CONTROL_CPU_INIT_RESET_GET(x)  (((x) & SOC_RESET_CONTROL_CPU_INIT_RESET_MASK) >> SOC_RESET_CONTROL_CPU_INIT_RESET_LSB)
118 #define SOC_RESET_CONTROL_CPU_INIT_RESET_SET(x)  (((x) << SOC_RESET_CONTROL_CPU_INIT_RESET_LSB) & SOC_RESET_CONTROL_CPU_INIT_RESET_MASK)
119 #define SOC_RESET_CONTROL_RST_OUT_MSB            9
120 #define SOC_RESET_CONTROL_RST_OUT_LSB            9
121 #define SOC_RESET_CONTROL_RST_OUT_MASK           0x00000200
122 #define SOC_RESET_CONTROL_RST_OUT_GET(x)         (((x) & SOC_RESET_CONTROL_RST_OUT_MASK) >> SOC_RESET_CONTROL_RST_OUT_LSB)
123 #define SOC_RESET_CONTROL_RST_OUT_SET(x)         (((x) << SOC_RESET_CONTROL_RST_OUT_LSB) & SOC_RESET_CONTROL_RST_OUT_MASK)
124 #define SOC_RESET_CONTROL_COLD_RST_MSB           8
125 #define SOC_RESET_CONTROL_COLD_RST_LSB           8
126 #define SOC_RESET_CONTROL_COLD_RST_MASK          0x00000100
127 #define SOC_RESET_CONTROL_COLD_RST_GET(x)        (((x) & SOC_RESET_CONTROL_COLD_RST_MASK) >> SOC_RESET_CONTROL_COLD_RST_LSB)
128 #define SOC_RESET_CONTROL_COLD_RST_SET(x)        (((x) << SOC_RESET_CONTROL_COLD_RST_LSB) & SOC_RESET_CONTROL_COLD_RST_MASK)
129 #define SOC_RESET_CONTROL_CPU_WARM_RST_MSB       6
130 #define SOC_RESET_CONTROL_CPU_WARM_RST_LSB       6
131 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK      0x00000040
132 #define SOC_RESET_CONTROL_CPU_WARM_RST_GET(x)    (((x) & SOC_RESET_CONTROL_CPU_WARM_RST_MASK) >> SOC_RESET_CONTROL_CPU_WARM_RST_LSB)
133 #define SOC_RESET_CONTROL_CPU_WARM_RST_SET(x)    (((x) << SOC_RESET_CONTROL_CPU_WARM_RST_LSB) & SOC_RESET_CONTROL_CPU_WARM_RST_MASK)
134 /* TODO: */
135 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MSB 2
136 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB 2
137 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000004
138 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_GET(x) (((x) & SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) >> SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB)
139 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_SET(x) (((x) << SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) & SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK)
140 #define SOC_RESET_CONTROL_MBOX_RST_MSB           2
141 #define SOC_RESET_CONTROL_MBOX_RST_LSB           2
142 #define SOC_RESET_CONTROL_MBOX_RST_MASK          0x00000004
143 #define SOC_RESET_CONTROL_MBOX_RST_GET(x)        (((x) & SOC_RESET_CONTROL_MBOX_RST_MASK) >> SOC_RESET_CONTROL_MBOX_RST_LSB)
144 #define SOC_RESET_CONTROL_MBOX_RST_SET(x)        (((x) << SOC_RESET_CONTROL_MBOX_RST_LSB) & SOC_RESET_CONTROL_MBOX_RST_MASK)
145 #define SOC_RESET_CONTROL_UART_RST_MSB           1
146 #define SOC_RESET_CONTROL_UART_RST_LSB           1
147 #define SOC_RESET_CONTROL_UART_RST_MASK          0x00000002
148 #define SOC_RESET_CONTROL_UART_RST_GET(x)        (((x) & SOC_RESET_CONTROL_UART_RST_MASK) >> SOC_RESET_CONTROL_UART_RST_LSB)
149 #define SOC_RESET_CONTROL_UART_RST_SET(x)        (((x) << SOC_RESET_CONTROL_UART_RST_LSB) & SOC_RESET_CONTROL_UART_RST_MASK)
150 #define SOC_RESET_CONTROL_SI0_RST_MSB            0
151 #define SOC_RESET_CONTROL_SI0_RST_LSB            0
152 #define SOC_RESET_CONTROL_SI0_RST_MASK           0x00000001
153 #define SOC_RESET_CONTROL_SI0_RST_GET(x)         (((x) & SOC_RESET_CONTROL_SI0_RST_MASK) >> SOC_RESET_CONTROL_SI0_RST_LSB)
154 #define SOC_RESET_CONTROL_SI0_RST_SET(x)         (((x) << SOC_RESET_CONTROL_SI0_RST_LSB) & SOC_RESET_CONTROL_SI0_RST_MASK)
155 
156 #define SOC_TCXO_DETECT_ADDRESS                  0x00000004
157 #define SOC_TCXO_DETECT_OFFSET                   0x00000004
158 #define SOC_TCXO_DETECT_PRESENT_MSB              0
159 #define SOC_TCXO_DETECT_PRESENT_LSB              0
160 #define SOC_TCXO_DETECT_PRESENT_MASK             0x00000001
161 #define SOC_TCXO_DETECT_PRESENT_GET(x)           (((x) & SOC_TCXO_DETECT_PRESENT_MASK) >> SOC_TCXO_DETECT_PRESENT_LSB)
162 #define SOC_TCXO_DETECT_PRESENT_SET(x)           (((x) << SOC_TCXO_DETECT_PRESENT_LSB) & SOC_TCXO_DETECT_PRESENT_MASK)
163 
164 #define SOC_XTAL_TEST_ADDRESS                    0x00000008
165 #define SOC_XTAL_TEST_OFFSET                     0x00000008
166 #define SOC_XTAL_TEST_NOTCXODET_MSB              0
167 #define SOC_XTAL_TEST_NOTCXODET_LSB              0
168 #define SOC_XTAL_TEST_NOTCXODET_MASK             0x00000001
169 #define SOC_XTAL_TEST_NOTCXODET_GET(x)           (((x) & SOC_XTAL_TEST_NOTCXODET_MASK) >> SOC_XTAL_TEST_NOTCXODET_LSB)
170 #define SOC_XTAL_TEST_NOTCXODET_SET(x)           (((x) << SOC_XTAL_TEST_NOTCXODET_LSB) & SOC_XTAL_TEST_NOTCXODET_MASK)
171 
172 #define SOC_CPU_CLOCK_ADDRESS                    0x00000020
173 #define SOC_CPU_CLOCK_OFFSET                     0x00000020
174 #define SOC_CPU_CLOCK_STANDARD_MSB               1
175 #define SOC_CPU_CLOCK_STANDARD_LSB               0
176 #define SOC_CPU_CLOCK_STANDARD_MASK              0x00000003
177 #define SOC_CPU_CLOCK_STANDARD_GET(x)            (((x) & SOC_CPU_CLOCK_STANDARD_MASK) >> SOC_CPU_CLOCK_STANDARD_LSB)
178 #define SOC_CPU_CLOCK_STANDARD_SET(x)            (((x) << SOC_CPU_CLOCK_STANDARD_LSB) & SOC_CPU_CLOCK_STANDARD_MASK)
179 
180 #define SOC_CLOCK_CONTROL_ADDRESS                0x00000028
181 #define SOC_CLOCK_CONTROL_OFFSET                 0x00000028
182 #define SOC_CLOCK_CONTROL_USB_CLOCK_MSB          3
183 #define SOC_CLOCK_CONTROL_USB_CLOCK_LSB          3
184 #define SOC_CLOCK_CONTROL_USB_CLOCK_MASK         0x00000008
185 #define SOC_CLOCK_CONTROL_USB_CLOCK_GET(x)       (((x) & SOC_CLOCK_CONTROL_USB_CLOCK_MASK) >> SOC_CLOCK_CONTROL_USB_CLOCK_LSB)
186 #define SOC_CLOCK_CONTROL_USB_CLOCK_SET(x)       (((x) << SOC_CLOCK_CONTROL_USB_CLOCK_LSB) & SOC_CLOCK_CONTROL_USB_CLOCK_MASK)
187 #define SOC_CLOCK_CONTROL_LF_CLK32_MSB           2
188 #define SOC_CLOCK_CONTROL_LF_CLK32_LSB           2
189 #define SOC_CLOCK_CONTROL_LF_CLK32_MASK          0x00000004
190 #define SOC_CLOCK_CONTROL_LF_CLK32_GET(x)        (((x) & SOC_CLOCK_CONTROL_LF_CLK32_MASK) >> SOC_CLOCK_CONTROL_LF_CLK32_LSB)
191 #define SOC_CLOCK_CONTROL_LF_CLK32_SET(x)        (((x) << SOC_CLOCK_CONTROL_LF_CLK32_LSB) & SOC_CLOCK_CONTROL_LF_CLK32_MASK)
192 #define SOC_CLOCK_CONTROL_SI0_CLK_MSB            0
193 #define SOC_CLOCK_CONTROL_SI0_CLK_LSB            0
194 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK           0x00000001
195 #define SOC_CLOCK_CONTROL_SI0_CLK_GET(x)         (((x) & SOC_CLOCK_CONTROL_SI0_CLK_MASK) >> SOC_CLOCK_CONTROL_SI0_CLK_LSB)
196 #define SOC_CLOCK_CONTROL_SI0_CLK_SET(x)         (((x) << SOC_CLOCK_CONTROL_SI0_CLK_LSB) & SOC_CLOCK_CONTROL_SI0_CLK_MASK)
197 
198 #define SOC_WDT_CONTROL_ADDRESS                  0x00000030
199 #define SOC_WDT_CONTROL_OFFSET                   0x00000030
200 #define SOC_WDT_CONTROL_ACTION_MSB               2
201 #define SOC_WDT_CONTROL_ACTION_LSB               0
202 #define SOC_WDT_CONTROL_ACTION_MASK              0x00000007
203 #define SOC_WDT_CONTROL_ACTION_GET(x)            (((x) & SOC_WDT_CONTROL_ACTION_MASK) >> SOC_WDT_CONTROL_ACTION_LSB)
204 #define SOC_WDT_CONTROL_ACTION_SET(x)            (((x) << SOC_WDT_CONTROL_ACTION_LSB) & SOC_WDT_CONTROL_ACTION_MASK)
205 
206 #define SOC_WDT_STATUS_ADDRESS                   0x00000034
207 #define SOC_WDT_STATUS_OFFSET                    0x00000034
208 #define SOC_WDT_STATUS_INTERRUPT_MSB             0
209 #define SOC_WDT_STATUS_INTERRUPT_LSB             0
210 #define SOC_WDT_STATUS_INTERRUPT_MASK            0x00000001
211 #define SOC_WDT_STATUS_INTERRUPT_GET(x)          (((x) & SOC_WDT_STATUS_INTERRUPT_MASK) >> SOC_WDT_STATUS_INTERRUPT_LSB)
212 #define SOC_WDT_STATUS_INTERRUPT_SET(x)          (((x) << SOC_WDT_STATUS_INTERRUPT_LSB) & SOC_WDT_STATUS_INTERRUPT_MASK)
213 
214 #define SOC_WDT_ADDRESS                          0x00000038
215 #define SOC_WDT_OFFSET                           0x00000038
216 #define SOC_WDT_TARGET_MSB                       21
217 #define SOC_WDT_TARGET_LSB                       0
218 #define SOC_WDT_TARGET_MASK                      0x003fffff
219 #define SOC_WDT_TARGET_GET(x)                    (((x) & SOC_WDT_TARGET_MASK) >> SOC_WDT_TARGET_LSB)
220 #define SOC_WDT_TARGET_SET(x)                    (((x) << SOC_WDT_TARGET_LSB) & SOC_WDT_TARGET_MASK)
221 
222 #define SOC_WDT_COUNT_ADDRESS                    0x0000003c
223 #define SOC_WDT_COUNT_OFFSET                     0x0000003c
224 #define SOC_WDT_COUNT_VALUE_MSB                  21
225 #define SOC_WDT_COUNT_VALUE_LSB                  0
226 #define SOC_WDT_COUNT_VALUE_MASK                 0x003fffff
227 #define SOC_WDT_COUNT_VALUE_GET(x)               (((x) & SOC_WDT_COUNT_VALUE_MASK) >> SOC_WDT_COUNT_VALUE_LSB)
228 #define SOC_WDT_COUNT_VALUE_SET(x)               (((x) << SOC_WDT_COUNT_VALUE_LSB) & SOC_WDT_COUNT_VALUE_MASK)
229 
230 #define SOC_WDT_RESET_ADDRESS                    0x00000040
231 #define SOC_WDT_RESET_OFFSET                     0x00000040
232 #define SOC_WDT_RESET_VALUE_MSB                  0
233 #define SOC_WDT_RESET_VALUE_LSB                  0
234 #define SOC_WDT_RESET_VALUE_MASK                 0x00000001
235 #define SOC_WDT_RESET_VALUE_GET(x)               (((x) & SOC_WDT_RESET_VALUE_MASK) >> SOC_WDT_RESET_VALUE_LSB)
236 #define SOC_WDT_RESET_VALUE_SET(x)               (((x) << SOC_WDT_RESET_VALUE_LSB) & SOC_WDT_RESET_VALUE_MASK)
237 
238 #define SOC_INT_STATUS_ADDRESS                   0x00000044
239 #define SOC_INT_STATUS_OFFSET                    0x00000044
240 #define SOC_INT_STATUS_MAC_4_MSB                 23
241 #define SOC_INT_STATUS_MAC_4_LSB                 23
242 #define SOC_INT_STATUS_MAC_4_MASK                0x00800000
243 #define SOC_INT_STATUS_MAC_4_GET(x)              (((x) & SOC_INT_STATUS_MAC_4_MASK) >> SOC_INT_STATUS_MAC_4_LSB)
244 #define SOC_INT_STATUS_MAC_4_SET(x)              (((x) << SOC_INT_STATUS_MAC_4_LSB) & SOC_INT_STATUS_MAC_4_MASK)
245 #define SOC_INT_STATUS_MAC_3_MSB                 22
246 #define SOC_INT_STATUS_MAC_3_LSB                 22
247 #define SOC_INT_STATUS_MAC_3_MASK                0x00400000
248 #define SOC_INT_STATUS_MAC_3_GET(x)              (((x) & SOC_INT_STATUS_MAC_3_MASK) >> SOC_INT_STATUS_MAC_3_LSB)
249 #define SOC_INT_STATUS_MAC_3_SET(x)              (((x) << SOC_INT_STATUS_MAC_3_LSB) & SOC_INT_STATUS_MAC_3_MASK)
250 #define SOC_INT_STATUS_MAC_2_MSB                 21
251 #define SOC_INT_STATUS_MAC_2_LSB                 21
252 #define SOC_INT_STATUS_MAC_2_MASK                0x00200000
253 #define SOC_INT_STATUS_MAC_2_GET(x)              (((x) & SOC_INT_STATUS_MAC_2_MASK) >> SOC_INT_STATUS_MAC_2_LSB)
254 #define SOC_INT_STATUS_MAC_2_SET(x)              (((x) << SOC_INT_STATUS_MAC_2_LSB) & SOC_INT_STATUS_MAC_2_MASK)
255 #define SOC_INT_STATUS_MAC_1_MSB                 20
256 #define SOC_INT_STATUS_MAC_1_LSB                 20
257 #define SOC_INT_STATUS_MAC_1_MASK                0x00100000
258 #define SOC_INT_STATUS_MAC_1_GET(x)              (((x) & SOC_INT_STATUS_MAC_1_MASK) >> SOC_INT_STATUS_MAC_1_LSB)
259 #define SOC_INT_STATUS_MAC_1_SET(x)              (((x) << SOC_INT_STATUS_MAC_1_LSB) & SOC_INT_STATUS_MAC_1_MASK)
260 #define SOC_INT_STATUS_USBDMA_MSB                19
261 #define SOC_INT_STATUS_USBDMA_LSB                19
262 #define SOC_INT_STATUS_USBDMA_MASK               0x00080000
263 #define SOC_INT_STATUS_USBDMA_GET(x)             (((x) & SOC_INT_STATUS_USBDMA_MASK) >> SOC_INT_STATUS_USBDMA_LSB)
264 #define SOC_INT_STATUS_USBDMA_SET(x)             (((x) << SOC_INT_STATUS_USBDMA_LSB) & SOC_INT_STATUS_USBDMA_MASK)
265 #define SOC_INT_STATUS_USBIP_MSB                 18
266 #define SOC_INT_STATUS_USBIP_LSB                 18
267 #define SOC_INT_STATUS_USBIP_MASK                0x00040000
268 #define SOC_INT_STATUS_USBIP_GET(x)              (((x) & SOC_INT_STATUS_USBIP_MASK) >> SOC_INT_STATUS_USBIP_LSB)
269 #define SOC_INT_STATUS_USBIP_SET(x)              (((x) << SOC_INT_STATUS_USBIP_LSB) & SOC_INT_STATUS_USBIP_MASK)
270 #define SOC_INT_STATUS_THERM_MSB                 17
271 #define SOC_INT_STATUS_THERM_LSB                 17
272 #define SOC_INT_STATUS_THERM_MASK                0x00020000
273 #define SOC_INT_STATUS_THERM_GET(x)              (((x) & SOC_INT_STATUS_THERM_MASK) >> SOC_INT_STATUS_THERM_LSB)
274 #define SOC_INT_STATUS_THERM_SET(x)              (((x) << SOC_INT_STATUS_THERM_LSB) & SOC_INT_STATUS_THERM_MASK)
275 #define SOC_INT_STATUS_EFUSE_OVERWRITE_MSB       16
276 #define SOC_INT_STATUS_EFUSE_OVERWRITE_LSB       16
277 #define SOC_INT_STATUS_EFUSE_OVERWRITE_MASK      0x00010000
278 #define SOC_INT_STATUS_EFUSE_OVERWRITE_GET(x)    (((x) & SOC_INT_STATUS_EFUSE_OVERWRITE_MASK) >> SOC_INT_STATUS_EFUSE_OVERWRITE_LSB)
279 #define SOC_INT_STATUS_EFUSE_OVERWRITE_SET(x)    (((x) << SOC_INT_STATUS_EFUSE_OVERWRITE_LSB) & SOC_INT_STATUS_EFUSE_OVERWRITE_MASK)
280 #define SOC_INT_STATUS_RDMA_MSB                  15
281 #define SOC_INT_STATUS_RDMA_LSB                  15
282 #define SOC_INT_STATUS_RDMA_MASK                 0x00008000
283 #define SOC_INT_STATUS_RDMA_GET(x)               (((x) & SOC_INT_STATUS_RDMA_MASK) >> SOC_INT_STATUS_RDMA_LSB)
284 #define SOC_INT_STATUS_RDMA_SET(x)               (((x) << SOC_INT_STATUS_RDMA_LSB) & SOC_INT_STATUS_RDMA_MASK)
285 #define SOC_INT_STATUS_BTCOEX_MSB                14
286 #define SOC_INT_STATUS_BTCOEX_LSB                14
287 #define SOC_INT_STATUS_BTCOEX_MASK               0x00004000
288 #define SOC_INT_STATUS_BTCOEX_GET(x)             (((x) & SOC_INT_STATUS_BTCOEX_MASK) >> SOC_INT_STATUS_BTCOEX_LSB)
289 #define SOC_INT_STATUS_BTCOEX_SET(x)             (((x) << SOC_INT_STATUS_BTCOEX_LSB) & SOC_INT_STATUS_BTCOEX_MASK)
290 #define SOC_INT_STATUS_RTC_POWER_MSB             13
291 #define SOC_INT_STATUS_RTC_POWER_LSB             13
292 #define SOC_INT_STATUS_RTC_POWER_MASK            0x00002000
293 #define SOC_INT_STATUS_RTC_POWER_GET(x)          (((x) & SOC_INT_STATUS_RTC_POWER_MASK) >> SOC_INT_STATUS_RTC_POWER_LSB)
294 #define SOC_INT_STATUS_RTC_POWER_SET(x)          (((x) << SOC_INT_STATUS_RTC_POWER_LSB) & SOC_INT_STATUS_RTC_POWER_MASK)
295 #define SOC_INT_STATUS_MAC_MSB                   12
296 #define SOC_INT_STATUS_MAC_LSB                   12
297 #define SOC_INT_STATUS_MAC_MASK                  0x00001000
298 #define SOC_INT_STATUS_MAC_GET(x)                (((x) & SOC_INT_STATUS_MAC_MASK) >> SOC_INT_STATUS_MAC_LSB)
299 #define SOC_INT_STATUS_MAC_SET(x)                (((x) << SOC_INT_STATUS_MAC_LSB) & SOC_INT_STATUS_MAC_MASK)
300 #define SOC_INT_STATUS_MAILBOX_MSB               11
301 #define SOC_INT_STATUS_MAILBOX_LSB               11
302 #define SOC_INT_STATUS_MAILBOX_MASK              0x00000800
303 #define SOC_INT_STATUS_MAILBOX_GET(x)            (((x) & SOC_INT_STATUS_MAILBOX_MASK) >> SOC_INT_STATUS_MAILBOX_LSB)
304 #define SOC_INT_STATUS_MAILBOX_SET(x)            (((x) << SOC_INT_STATUS_MAILBOX_LSB) & SOC_INT_STATUS_MAILBOX_MASK)
305 #define SOC_INT_STATUS_RTC_ALARM_MSB             10
306 #define SOC_INT_STATUS_RTC_ALARM_LSB             10
307 #define SOC_INT_STATUS_RTC_ALARM_MASK            0x00000400
308 #define SOC_INT_STATUS_RTC_ALARM_GET(x)          (((x) & SOC_INT_STATUS_RTC_ALARM_MASK) >> SOC_INT_STATUS_RTC_ALARM_LSB)
309 #define SOC_INT_STATUS_RTC_ALARM_SET(x)          (((x) << SOC_INT_STATUS_RTC_ALARM_LSB) & SOC_INT_STATUS_RTC_ALARM_MASK)
310 #define SOC_INT_STATUS_HF_TIMER_MSB              9
311 #define SOC_INT_STATUS_HF_TIMER_LSB              9
312 #define SOC_INT_STATUS_HF_TIMER_MASK             0x00000200
313 #define SOC_INT_STATUS_HF_TIMER_GET(x)           (((x) & SOC_INT_STATUS_HF_TIMER_MASK) >> SOC_INT_STATUS_HF_TIMER_LSB)
314 #define SOC_INT_STATUS_HF_TIMER_SET(x)           (((x) << SOC_INT_STATUS_HF_TIMER_LSB) & SOC_INT_STATUS_HF_TIMER_MASK)
315 #define SOC_INT_STATUS_LF_TIMER3_MSB             8
316 #define SOC_INT_STATUS_LF_TIMER3_LSB             8
317 #define SOC_INT_STATUS_LF_TIMER3_MASK            0x00000100
318 #define SOC_INT_STATUS_LF_TIMER3_GET(x)          (((x) & SOC_INT_STATUS_LF_TIMER3_MASK) >> SOC_INT_STATUS_LF_TIMER3_LSB)
319 #define SOC_INT_STATUS_LF_TIMER3_SET(x)          (((x) << SOC_INT_STATUS_LF_TIMER3_LSB) & SOC_INT_STATUS_LF_TIMER3_MASK)
320 #define SOC_INT_STATUS_LF_TIMER2_MSB             7
321 #define SOC_INT_STATUS_LF_TIMER2_LSB             7
322 #define SOC_INT_STATUS_LF_TIMER2_MASK            0x00000080
323 #define SOC_INT_STATUS_LF_TIMER2_GET(x)          (((x) & SOC_INT_STATUS_LF_TIMER2_MASK) >> SOC_INT_STATUS_LF_TIMER2_LSB)
324 #define SOC_INT_STATUS_LF_TIMER2_SET(x)          (((x) << SOC_INT_STATUS_LF_TIMER2_LSB) & SOC_INT_STATUS_LF_TIMER2_MASK)
325 #define SOC_INT_STATUS_LF_TIMER1_MSB             6
326 #define SOC_INT_STATUS_LF_TIMER1_LSB             6
327 #define SOC_INT_STATUS_LF_TIMER1_MASK            0x00000040
328 #define SOC_INT_STATUS_LF_TIMER1_GET(x)          (((x) & SOC_INT_STATUS_LF_TIMER1_MASK) >> SOC_INT_STATUS_LF_TIMER1_LSB)
329 #define SOC_INT_STATUS_LF_TIMER1_SET(x)          (((x) << SOC_INT_STATUS_LF_TIMER1_LSB) & SOC_INT_STATUS_LF_TIMER1_MASK)
330 #define SOC_INT_STATUS_LF_TIMER0_MSB             5
331 #define SOC_INT_STATUS_LF_TIMER0_LSB             5
332 #define SOC_INT_STATUS_LF_TIMER0_MASK            0x00000020
333 #define SOC_INT_STATUS_LF_TIMER0_GET(x)          (((x) & SOC_INT_STATUS_LF_TIMER0_MASK) >> SOC_INT_STATUS_LF_TIMER0_LSB)
334 #define SOC_INT_STATUS_LF_TIMER0_SET(x)          (((x) << SOC_INT_STATUS_LF_TIMER0_LSB) & SOC_INT_STATUS_LF_TIMER0_MASK)
335 #define SOC_INT_STATUS_SI_MSB                    4
336 #define SOC_INT_STATUS_SI_LSB                    4
337 #define SOC_INT_STATUS_SI_MASK                   0x00000010
338 #define SOC_INT_STATUS_SI_GET(x)                 (((x) & SOC_INT_STATUS_SI_MASK) >> SOC_INT_STATUS_SI_LSB)
339 #define SOC_INT_STATUS_SI_SET(x)                 (((x) << SOC_INT_STATUS_SI_LSB) & SOC_INT_STATUS_SI_MASK)
340 #define SOC_INT_STATUS_GPIO_MSB                  3
341 #define SOC_INT_STATUS_GPIO_LSB                  3
342 #define SOC_INT_STATUS_GPIO_MASK                 0x00000008
343 #define SOC_INT_STATUS_GPIO_GET(x)               (((x) & SOC_INT_STATUS_GPIO_MASK) >> SOC_INT_STATUS_GPIO_LSB)
344 #define SOC_INT_STATUS_GPIO_SET(x)               (((x) << SOC_INT_STATUS_GPIO_LSB) & SOC_INT_STATUS_GPIO_MASK)
345 #define SOC_INT_STATUS_DEBUG_UART_MSB            2
346 #define SOC_INT_STATUS_DEBUG_UART_LSB            2
347 #define SOC_INT_STATUS_DEBUG_UART_MASK           0x00000004
348 #define SOC_INT_STATUS_DEBUG_UART_GET(x)         (((x) & SOC_INT_STATUS_DEBUG_UART_MASK) >> SOC_INT_STATUS_DEBUG_UART_LSB)
349 #define SOC_INT_STATUS_DEBUG_UART_SET(x)         (((x) << SOC_INT_STATUS_DEBUG_UART_LSB) & SOC_INT_STATUS_DEBUG_UART_MASK)
350 #define SOC_INT_STATUS_ERROR_MSB                 1
351 #define SOC_INT_STATUS_ERROR_LSB                 1
352 #define SOC_INT_STATUS_ERROR_MASK                0x00000002
353 #define SOC_INT_STATUS_ERROR_GET(x)              (((x) & SOC_INT_STATUS_ERROR_MASK) >> SOC_INT_STATUS_ERROR_LSB)
354 #define SOC_INT_STATUS_ERROR_SET(x)              (((x) << SOC_INT_STATUS_ERROR_LSB) & SOC_INT_STATUS_ERROR_MASK)
355 #define SOC_INT_STATUS_WDT_INT_MSB               0
356 #define SOC_INT_STATUS_WDT_INT_LSB               0
357 #define SOC_INT_STATUS_WDT_INT_MASK              0x00000001
358 #define SOC_INT_STATUS_WDT_INT_GET(x)            (((x) & SOC_INT_STATUS_WDT_INT_MASK) >> SOC_INT_STATUS_WDT_INT_LSB)
359 #define SOC_INT_STATUS_WDT_INT_SET(x)            (((x) << SOC_INT_STATUS_WDT_INT_LSB) & SOC_INT_STATUS_WDT_INT_MASK)
360 
361 #define SOC_LF_TIMER0_ADDRESS                    0x00000048
362 #define SOC_LF_TIMER0_OFFSET                     0x00000048
363 #define SOC_LF_TIMER0_TARGET_MSB                 31
364 #define SOC_LF_TIMER0_TARGET_LSB                 0
365 #define SOC_LF_TIMER0_TARGET_MASK                0xffffffff
366 #define SOC_LF_TIMER0_TARGET_GET(x)              (((x) & SOC_LF_TIMER0_TARGET_MASK) >> SOC_LF_TIMER0_TARGET_LSB)
367 #define SOC_LF_TIMER0_TARGET_SET(x)              (((x) << SOC_LF_TIMER0_TARGET_LSB) & SOC_LF_TIMER0_TARGET_MASK)
368 
369 #define SOC_LF_TIMER_COUNT0_ADDRESS              0x0000004c
370 #define SOC_LF_TIMER_COUNT0_OFFSET               0x0000004c
371 #define SOC_LF_TIMER_COUNT0_VALUE_MSB            31
372 #define SOC_LF_TIMER_COUNT0_VALUE_LSB            0
373 #define SOC_LF_TIMER_COUNT0_VALUE_MASK           0xffffffff
374 #define SOC_LF_TIMER_COUNT0_VALUE_GET(x)         (((x) & SOC_LF_TIMER_COUNT0_VALUE_MASK) >> SOC_LF_TIMER_COUNT0_VALUE_LSB)
375 #define SOC_LF_TIMER_COUNT0_VALUE_SET(x)         (((x) << SOC_LF_TIMER_COUNT0_VALUE_LSB) & SOC_LF_TIMER_COUNT0_VALUE_MASK)
376 
377 #define SOC_LF_TIMER_CONTROL0_ADDRESS            0x00000050
378 #define SOC_LF_TIMER_CONTROL0_OFFSET             0x00000050
379 #define SOC_LF_TIMER_CONTROL0_ENABLE_MSB         2
380 #define SOC_LF_TIMER_CONTROL0_ENABLE_LSB         2
381 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK        0x00000004
382 #define SOC_LF_TIMER_CONTROL0_ENABLE_GET(x)      (((x) & SOC_LF_TIMER_CONTROL0_ENABLE_MASK) >> SOC_LF_TIMER_CONTROL0_ENABLE_LSB)
383 #define SOC_LF_TIMER_CONTROL0_ENABLE_SET(x)      (((x) << SOC_LF_TIMER_CONTROL0_ENABLE_LSB) & SOC_LF_TIMER_CONTROL0_ENABLE_MASK)
384 #define SOC_LF_TIMER_CONTROL0_AUTO_RESTART_MSB   1
385 #define SOC_LF_TIMER_CONTROL0_AUTO_RESTART_LSB   1
386 #define SOC_LF_TIMER_CONTROL0_AUTO_RESTART_MASK  0x00000002
387 #define SOC_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & SOC_LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> SOC_LF_TIMER_CONTROL0_AUTO_RESTART_LSB)
388 #define SOC_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << SOC_LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & SOC_LF_TIMER_CONTROL0_AUTO_RESTART_MASK)
389 #define SOC_LF_TIMER_CONTROL0_RESET_MSB          0
390 #define SOC_LF_TIMER_CONTROL0_RESET_LSB          0
391 #define SOC_LF_TIMER_CONTROL0_RESET_MASK         0x00000001
392 #define SOC_LF_TIMER_CONTROL0_RESET_GET(x)       (((x) & SOC_LF_TIMER_CONTROL0_RESET_MASK) >> SOC_LF_TIMER_CONTROL0_RESET_LSB)
393 #define SOC_LF_TIMER_CONTROL0_RESET_SET(x)       (((x) << SOC_LF_TIMER_CONTROL0_RESET_LSB) & SOC_LF_TIMER_CONTROL0_RESET_MASK)
394 
395 #define SOC_LF_TIMER_STATUS0_ADDRESS             0x00000054
396 #define SOC_LF_TIMER_STATUS0_OFFSET              0x00000054
397 #define SOC_LF_TIMER_STATUS0_INTERRUPT_MSB       0
398 #define SOC_LF_TIMER_STATUS0_INTERRUPT_LSB       0
399 #define SOC_LF_TIMER_STATUS0_INTERRUPT_MASK      0x00000001
400 #define SOC_LF_TIMER_STATUS0_INTERRUPT_GET(x)    (((x) & SOC_LF_TIMER_STATUS0_INTERRUPT_MASK) >> SOC_LF_TIMER_STATUS0_INTERRUPT_LSB)
401 #define SOC_LF_TIMER_STATUS0_INTERRUPT_SET(x)    (((x) << SOC_LF_TIMER_STATUS0_INTERRUPT_LSB) & SOC_LF_TIMER_STATUS0_INTERRUPT_MASK)
402 
403 #define SOC_LF_TIMER1_ADDRESS                    0x00000058
404 #define SOC_LF_TIMER1_OFFSET                     0x00000058
405 #define SOC_LF_TIMER1_TARGET_MSB                 31
406 #define SOC_LF_TIMER1_TARGET_LSB                 0
407 #define SOC_LF_TIMER1_TARGET_MASK                0xffffffff
408 #define SOC_LF_TIMER1_TARGET_GET(x)              (((x) & SOC_LF_TIMER1_TARGET_MASK) >> SOC_LF_TIMER1_TARGET_LSB)
409 #define SOC_LF_TIMER1_TARGET_SET(x)              (((x) << SOC_LF_TIMER1_TARGET_LSB) & SOC_LF_TIMER1_TARGET_MASK)
410 
411 #define SOC_LF_TIMER_COUNT1_ADDRESS              0x0000005c
412 #define SOC_LF_TIMER_COUNT1_OFFSET               0x0000005c
413 #define SOC_LF_TIMER_COUNT1_VALUE_MSB            31
414 #define SOC_LF_TIMER_COUNT1_VALUE_LSB            0
415 #define SOC_LF_TIMER_COUNT1_VALUE_MASK           0xffffffff
416 #define SOC_LF_TIMER_COUNT1_VALUE_GET(x)         (((x) & SOC_LF_TIMER_COUNT1_VALUE_MASK) >> SOC_LF_TIMER_COUNT1_VALUE_LSB)
417 #define SOC_LF_TIMER_COUNT1_VALUE_SET(x)         (((x) << SOC_LF_TIMER_COUNT1_VALUE_LSB) & SOC_LF_TIMER_COUNT1_VALUE_MASK)
418 
419 #define SOC_LF_TIMER_CONTROL1_ADDRESS            0x00000060
420 #define SOC_LF_TIMER_CONTROL1_OFFSET             0x00000060
421 #define SOC_LF_TIMER_CONTROL1_ENABLE_MSB         2
422 #define SOC_LF_TIMER_CONTROL1_ENABLE_LSB         2
423 #define SOC_LF_TIMER_CONTROL1_ENABLE_MASK        0x00000004
424 #define SOC_LF_TIMER_CONTROL1_ENABLE_GET(x)      (((x) & SOC_LF_TIMER_CONTROL1_ENABLE_MASK) >> SOC_LF_TIMER_CONTROL1_ENABLE_LSB)
425 #define SOC_LF_TIMER_CONTROL1_ENABLE_SET(x)      (((x) << SOC_LF_TIMER_CONTROL1_ENABLE_LSB) & SOC_LF_TIMER_CONTROL1_ENABLE_MASK)
426 #define SOC_LF_TIMER_CONTROL1_AUTO_RESTART_MSB   1
427 #define SOC_LF_TIMER_CONTROL1_AUTO_RESTART_LSB   1
428 #define SOC_LF_TIMER_CONTROL1_AUTO_RESTART_MASK  0x00000002
429 #define SOC_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & SOC_LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> SOC_LF_TIMER_CONTROL1_AUTO_RESTART_LSB)
430 #define SOC_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << SOC_LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & SOC_LF_TIMER_CONTROL1_AUTO_RESTART_MASK)
431 #define SOC_LF_TIMER_CONTROL1_RESET_MSB          0
432 #define SOC_LF_TIMER_CONTROL1_RESET_LSB          0
433 #define SOC_LF_TIMER_CONTROL1_RESET_MASK         0x00000001
434 #define SOC_LF_TIMER_CONTROL1_RESET_GET(x)       (((x) & SOC_LF_TIMER_CONTROL1_RESET_MASK) >> SOC_LF_TIMER_CONTROL1_RESET_LSB)
435 #define SOC_LF_TIMER_CONTROL1_RESET_SET(x)       (((x) << SOC_LF_TIMER_CONTROL1_RESET_LSB) & SOC_LF_TIMER_CONTROL1_RESET_MASK)
436 
437 #define SOC_LF_TIMER_STATUS1_ADDRESS             0x00000064
438 #define SOC_LF_TIMER_STATUS1_OFFSET              0x00000064
439 #define SOC_LF_TIMER_STATUS1_INTERRUPT_MSB       0
440 #define SOC_LF_TIMER_STATUS1_INTERRUPT_LSB       0
441 #define SOC_LF_TIMER_STATUS1_INTERRUPT_MASK      0x00000001
442 #define SOC_LF_TIMER_STATUS1_INTERRUPT_GET(x)    (((x) & SOC_LF_TIMER_STATUS1_INTERRUPT_MASK) >> SOC_LF_TIMER_STATUS1_INTERRUPT_LSB)
443 #define SOC_LF_TIMER_STATUS1_INTERRUPT_SET(x)    (((x) << SOC_LF_TIMER_STATUS1_INTERRUPT_LSB) & SOC_LF_TIMER_STATUS1_INTERRUPT_MASK)
444 
445 #define SOC_LF_TIMER2_ADDRESS                    0x00000068
446 #define SOC_LF_TIMER2_OFFSET                     0x00000068
447 #define SOC_LF_TIMER2_TARGET_MSB                 31
448 #define SOC_LF_TIMER2_TARGET_LSB                 0
449 #define SOC_LF_TIMER2_TARGET_MASK                0xffffffff
450 #define SOC_LF_TIMER2_TARGET_GET(x)              (((x) & SOC_LF_TIMER2_TARGET_MASK) >> SOC_LF_TIMER2_TARGET_LSB)
451 #define SOC_LF_TIMER2_TARGET_SET(x)              (((x) << SOC_LF_TIMER2_TARGET_LSB) & SOC_LF_TIMER2_TARGET_MASK)
452 
453 #define SOC_LF_TIMER_COUNT2_ADDRESS              0x0000006c
454 #define SOC_LF_TIMER_COUNT2_OFFSET               0x0000006c
455 #define SOC_LF_TIMER_COUNT2_VALUE_MSB            31
456 #define SOC_LF_TIMER_COUNT2_VALUE_LSB            0
457 #define SOC_LF_TIMER_COUNT2_VALUE_MASK           0xffffffff
458 #define SOC_LF_TIMER_COUNT2_VALUE_GET(x)         (((x) & SOC_LF_TIMER_COUNT2_VALUE_MASK) >> SOC_LF_TIMER_COUNT2_VALUE_LSB)
459 #define SOC_LF_TIMER_COUNT2_VALUE_SET(x)         (((x) << SOC_LF_TIMER_COUNT2_VALUE_LSB) & SOC_LF_TIMER_COUNT2_VALUE_MASK)
460 
461 #define SOC_LF_TIMER_CONTROL2_ADDRESS            0x00000070
462 #define SOC_LF_TIMER_CONTROL2_OFFSET             0x00000070
463 #define SOC_LF_TIMER_CONTROL2_ENABLE_MSB         2
464 #define SOC_LF_TIMER_CONTROL2_ENABLE_LSB         2
465 #define SOC_LF_TIMER_CONTROL2_ENABLE_MASK        0x00000004
466 #define SOC_LF_TIMER_CONTROL2_ENABLE_GET(x)      (((x) & SOC_LF_TIMER_CONTROL2_ENABLE_MASK) >> SOC_LF_TIMER_CONTROL2_ENABLE_LSB)
467 #define SOC_LF_TIMER_CONTROL2_ENABLE_SET(x)      (((x) << SOC_LF_TIMER_CONTROL2_ENABLE_LSB) & SOC_LF_TIMER_CONTROL2_ENABLE_MASK)
468 #define SOC_LF_TIMER_CONTROL2_AUTO_RESTART_MSB   1
469 #define SOC_LF_TIMER_CONTROL2_AUTO_RESTART_LSB   1
470 #define SOC_LF_TIMER_CONTROL2_AUTO_RESTART_MASK  0x00000002
471 #define SOC_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & SOC_LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> SOC_LF_TIMER_CONTROL2_AUTO_RESTART_LSB)
472 #define SOC_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << SOC_LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & SOC_LF_TIMER_CONTROL2_AUTO_RESTART_MASK)
473 #define SOC_LF_TIMER_CONTROL2_RESET_MSB          0
474 #define SOC_LF_TIMER_CONTROL2_RESET_LSB          0
475 #define SOC_LF_TIMER_CONTROL2_RESET_MASK         0x00000001
476 #define SOC_LF_TIMER_CONTROL2_RESET_GET(x)       (((x) & SOC_LF_TIMER_CONTROL2_RESET_MASK) >> SOC_LF_TIMER_CONTROL2_RESET_LSB)
477 #define SOC_LF_TIMER_CONTROL2_RESET_SET(x)       (((x) << SOC_LF_TIMER_CONTROL2_RESET_LSB) & SOC_LF_TIMER_CONTROL2_RESET_MASK)
478 
479 #define SOC_LF_TIMER_STATUS2_ADDRESS             0x00000074
480 #define SOC_LF_TIMER_STATUS2_OFFSET              0x00000074
481 #define SOC_LF_TIMER_STATUS2_INTERRUPT_MSB       0
482 #define SOC_LF_TIMER_STATUS2_INTERRUPT_LSB       0
483 #define SOC_LF_TIMER_STATUS2_INTERRUPT_MASK      0x00000001
484 #define SOC_LF_TIMER_STATUS2_INTERRUPT_GET(x)    (((x) & SOC_LF_TIMER_STATUS2_INTERRUPT_MASK) >> SOC_LF_TIMER_STATUS2_INTERRUPT_LSB)
485 #define SOC_LF_TIMER_STATUS2_INTERRUPT_SET(x)    (((x) << SOC_LF_TIMER_STATUS2_INTERRUPT_LSB) & SOC_LF_TIMER_STATUS2_INTERRUPT_MASK)
486 
487 #define SOC_LF_TIMER3_ADDRESS                    0x00000078
488 #define SOC_LF_TIMER3_OFFSET                     0x00000078
489 #define SOC_LF_TIMER3_TARGET_MSB                 31
490 #define SOC_LF_TIMER3_TARGET_LSB                 0
491 #define SOC_LF_TIMER3_TARGET_MASK                0xffffffff
492 #define SOC_LF_TIMER3_TARGET_GET(x)              (((x) & SOC_LF_TIMER3_TARGET_MASK) >> SOC_LF_TIMER3_TARGET_LSB)
493 #define SOC_LF_TIMER3_TARGET_SET(x)              (((x) << SOC_LF_TIMER3_TARGET_LSB) & SOC_LF_TIMER3_TARGET_MASK)
494 
495 #define SOC_LF_TIMER_COUNT3_ADDRESS              0x0000007c
496 #define SOC_LF_TIMER_COUNT3_OFFSET               0x0000007c
497 #define SOC_LF_TIMER_COUNT3_VALUE_MSB            31
498 #define SOC_LF_TIMER_COUNT3_VALUE_LSB            0
499 #define SOC_LF_TIMER_COUNT3_VALUE_MASK           0xffffffff
500 #define SOC_LF_TIMER_COUNT3_VALUE_GET(x)         (((x) & SOC_LF_TIMER_COUNT3_VALUE_MASK) >> SOC_LF_TIMER_COUNT3_VALUE_LSB)
501 #define SOC_LF_TIMER_COUNT3_VALUE_SET(x)         (((x) << SOC_LF_TIMER_COUNT3_VALUE_LSB) & SOC_LF_TIMER_COUNT3_VALUE_MASK)
502 
503 #define SOC_LF_TIMER_CONTROL3_ADDRESS            0x00000080
504 #define SOC_LF_TIMER_CONTROL3_OFFSET             0x00000080
505 #define SOC_LF_TIMER_CONTROL3_ENABLE_MSB         2
506 #define SOC_LF_TIMER_CONTROL3_ENABLE_LSB         2
507 #define SOC_LF_TIMER_CONTROL3_ENABLE_MASK        0x00000004
508 #define SOC_LF_TIMER_CONTROL3_ENABLE_GET(x)      (((x) & SOC_LF_TIMER_CONTROL3_ENABLE_MASK) >> SOC_LF_TIMER_CONTROL3_ENABLE_LSB)
509 #define SOC_LF_TIMER_CONTROL3_ENABLE_SET(x)      (((x) << SOC_LF_TIMER_CONTROL3_ENABLE_LSB) & SOC_LF_TIMER_CONTROL3_ENABLE_MASK)
510 #define SOC_LF_TIMER_CONTROL3_AUTO_RESTART_MSB   1
511 #define SOC_LF_TIMER_CONTROL3_AUTO_RESTART_LSB   1
512 #define SOC_LF_TIMER_CONTROL3_AUTO_RESTART_MASK  0x00000002
513 #define SOC_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & SOC_LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> SOC_LF_TIMER_CONTROL3_AUTO_RESTART_LSB)
514 #define SOC_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << SOC_LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & SOC_LF_TIMER_CONTROL3_AUTO_RESTART_MASK)
515 #define SOC_LF_TIMER_CONTROL3_RESET_MSB          0
516 #define SOC_LF_TIMER_CONTROL3_RESET_LSB          0
517 #define SOC_LF_TIMER_CONTROL3_RESET_MASK         0x00000001
518 #define SOC_LF_TIMER_CONTROL3_RESET_GET(x)       (((x) & SOC_LF_TIMER_CONTROL3_RESET_MASK) >> SOC_LF_TIMER_CONTROL3_RESET_LSB)
519 #define SOC_LF_TIMER_CONTROL3_RESET_SET(x)       (((x) << SOC_LF_TIMER_CONTROL3_RESET_LSB) & SOC_LF_TIMER_CONTROL3_RESET_MASK)
520 
521 #define SOC_LF_TIMER_STATUS3_ADDRESS             0x00000084
522 #define SOC_LF_TIMER_STATUS3_OFFSET              0x00000084
523 #define SOC_LF_TIMER_STATUS3_INTERRUPT_MSB       0
524 #define SOC_LF_TIMER_STATUS3_INTERRUPT_LSB       0
525 #define SOC_LF_TIMER_STATUS3_INTERRUPT_MASK      0x00000001
526 #define SOC_LF_TIMER_STATUS3_INTERRUPT_GET(x)    (((x) & SOC_LF_TIMER_STATUS3_INTERRUPT_MASK) >> SOC_LF_TIMER_STATUS3_INTERRUPT_LSB)
527 #define SOC_LF_TIMER_STATUS3_INTERRUPT_SET(x)    (((x) << SOC_LF_TIMER_STATUS3_INTERRUPT_LSB) & SOC_LF_TIMER_STATUS3_INTERRUPT_MASK)
528 
529 #define SOC_HF_TIMER_ADDRESS                     0x00000088
530 #define SOC_HF_TIMER_OFFSET                      0x00000088
531 #define SOC_HF_TIMER_TARGET_MSB                  31
532 #define SOC_HF_TIMER_TARGET_LSB                  12
533 #define SOC_HF_TIMER_TARGET_MASK                 0xfffff000
534 #define SOC_HF_TIMER_TARGET_GET(x)               (((x) & SOC_HF_TIMER_TARGET_MASK) >> SOC_HF_TIMER_TARGET_LSB)
535 #define SOC_HF_TIMER_TARGET_SET(x)               (((x) << SOC_HF_TIMER_TARGET_LSB) & SOC_HF_TIMER_TARGET_MASK)
536 
537 #define SOC_HF_TIMER_COUNT_ADDRESS               0x0000008c
538 #define SOC_HF_TIMER_COUNT_OFFSET                0x0000008c
539 #define SOC_HF_TIMER_COUNT_VALUE_MSB             31
540 #define SOC_HF_TIMER_COUNT_VALUE_LSB             12
541 #define SOC_HF_TIMER_COUNT_VALUE_MASK            0xfffff000
542 #define SOC_HF_TIMER_COUNT_VALUE_GET(x)          (((x) & SOC_HF_TIMER_COUNT_VALUE_MASK) >> SOC_HF_TIMER_COUNT_VALUE_LSB)
543 #define SOC_HF_TIMER_COUNT_VALUE_SET(x)          (((x) << SOC_HF_TIMER_COUNT_VALUE_LSB) & SOC_HF_TIMER_COUNT_VALUE_MASK)
544 
545 #define SOC_HF_LF_COUNT_ADDRESS                  0x00000090
546 #define SOC_HF_LF_COUNT_OFFSET                   0x00000090
547 #define SOC_HF_LF_COUNT_VALUE_MSB                31
548 #define SOC_HF_LF_COUNT_VALUE_LSB                0
549 #define SOC_HF_LF_COUNT_VALUE_MASK               0xffffffff
550 #define SOC_HF_LF_COUNT_VALUE_GET(x)             (((x) & SOC_HF_LF_COUNT_VALUE_MASK) >> SOC_HF_LF_COUNT_VALUE_LSB)
551 #define SOC_HF_LF_COUNT_VALUE_SET(x)             (((x) << SOC_HF_LF_COUNT_VALUE_LSB) & SOC_HF_LF_COUNT_VALUE_MASK)
552 
553 #define SOC_HF_TIMER_CONTROL_ADDRESS             0x00000094
554 #define SOC_HF_TIMER_CONTROL_OFFSET              0x00000094
555 #define SOC_HF_TIMER_CONTROL_ENABLE_MSB          3
556 #define SOC_HF_TIMER_CONTROL_ENABLE_LSB          3
557 #define SOC_HF_TIMER_CONTROL_ENABLE_MASK         0x00000008
558 #define SOC_HF_TIMER_CONTROL_ENABLE_GET(x)       (((x) & SOC_HF_TIMER_CONTROL_ENABLE_MASK) >> SOC_HF_TIMER_CONTROL_ENABLE_LSB)
559 #define SOC_HF_TIMER_CONTROL_ENABLE_SET(x)       (((x) << SOC_HF_TIMER_CONTROL_ENABLE_LSB) & SOC_HF_TIMER_CONTROL_ENABLE_MASK)
560 #define SOC_HF_TIMER_CONTROL_ON_MSB              2
561 #define SOC_HF_TIMER_CONTROL_ON_LSB              2
562 #define SOC_HF_TIMER_CONTROL_ON_MASK             0x00000004
563 #define SOC_HF_TIMER_CONTROL_ON_GET(x)           (((x) & SOC_HF_TIMER_CONTROL_ON_MASK) >> SOC_HF_TIMER_CONTROL_ON_LSB)
564 #define SOC_HF_TIMER_CONTROL_ON_SET(x)           (((x) << SOC_HF_TIMER_CONTROL_ON_LSB) & SOC_HF_TIMER_CONTROL_ON_MASK)
565 #define SOC_HF_TIMER_CONTROL_AUTO_RESTART_MSB    1
566 #define SOC_HF_TIMER_CONTROL_AUTO_RESTART_LSB    1
567 #define SOC_HF_TIMER_CONTROL_AUTO_RESTART_MASK   0x00000002
568 #define SOC_HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & SOC_HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> SOC_HF_TIMER_CONTROL_AUTO_RESTART_LSB)
569 #define SOC_HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << SOC_HF_TIMER_CONTROL_AUTO_RESTART_LSB) & SOC_HF_TIMER_CONTROL_AUTO_RESTART_MASK)
570 #define SOC_HF_TIMER_CONTROL_RESET_MSB           0
571 #define SOC_HF_TIMER_CONTROL_RESET_LSB           0
572 #define SOC_HF_TIMER_CONTROL_RESET_MASK          0x00000001
573 #define SOC_HF_TIMER_CONTROL_RESET_GET(x)        (((x) & SOC_HF_TIMER_CONTROL_RESET_MASK) >> SOC_HF_TIMER_CONTROL_RESET_LSB)
574 #define SOC_HF_TIMER_CONTROL_RESET_SET(x)        (((x) << SOC_HF_TIMER_CONTROL_RESET_LSB) & SOC_HF_TIMER_CONTROL_RESET_MASK)
575 
576 #define SOC_HF_TIMER_STATUS_ADDRESS              0x00000098
577 #define SOC_HF_TIMER_STATUS_OFFSET               0x00000098
578 #define SOC_HF_TIMER_STATUS_INTERRUPT_MSB        0
579 #define SOC_HF_TIMER_STATUS_INTERRUPT_LSB        0
580 #define SOC_HF_TIMER_STATUS_INTERRUPT_MASK       0x00000001
581 #define SOC_HF_TIMER_STATUS_INTERRUPT_GET(x)     (((x) & SOC_HF_TIMER_STATUS_INTERRUPT_MASK) >> SOC_HF_TIMER_STATUS_INTERRUPT_LSB)
582 #define SOC_HF_TIMER_STATUS_INTERRUPT_SET(x)     (((x) << SOC_HF_TIMER_STATUS_INTERRUPT_LSB) & SOC_HF_TIMER_STATUS_INTERRUPT_MASK)
583 
584 #define SOC_RTC_CONTROL_ADDRESS                  0x0000009c
585 #define SOC_RTC_CONTROL_OFFSET                   0x0000009c
586 #define SOC_RTC_CONTROL_ENABLE_MSB               2
587 #define SOC_RTC_CONTROL_ENABLE_LSB               2
588 #define SOC_RTC_CONTROL_ENABLE_MASK              0x00000004
589 #define SOC_RTC_CONTROL_ENABLE_GET(x)            (((x) & SOC_RTC_CONTROL_ENABLE_MASK) >> SOC_RTC_CONTROL_ENABLE_LSB)
590 #define SOC_RTC_CONTROL_ENABLE_SET(x)            (((x) << SOC_RTC_CONTROL_ENABLE_LSB) & SOC_RTC_CONTROL_ENABLE_MASK)
591 #define SOC_RTC_CONTROL_LOAD_RTC_MSB             1
592 #define SOC_RTC_CONTROL_LOAD_RTC_LSB             1
593 #define SOC_RTC_CONTROL_LOAD_RTC_MASK            0x00000002
594 #define SOC_RTC_CONTROL_LOAD_RTC_GET(x)          (((x) & SOC_RTC_CONTROL_LOAD_RTC_MASK) >> SOC_RTC_CONTROL_LOAD_RTC_LSB)
595 #define SOC_RTC_CONTROL_LOAD_RTC_SET(x)          (((x) << SOC_RTC_CONTROL_LOAD_RTC_LSB) & SOC_RTC_CONTROL_LOAD_RTC_MASK)
596 #define SOC_RTC_CONTROL_LOAD_ALARM_MSB           0
597 #define SOC_RTC_CONTROL_LOAD_ALARM_LSB           0
598 #define SOC_RTC_CONTROL_LOAD_ALARM_MASK          0x00000001
599 #define SOC_RTC_CONTROL_LOAD_ALARM_GET(x)        (((x) & SOC_RTC_CONTROL_LOAD_ALARM_MASK) >> SOC_RTC_CONTROL_LOAD_ALARM_LSB)
600 #define SOC_RTC_CONTROL_LOAD_ALARM_SET(x)        (((x) << SOC_RTC_CONTROL_LOAD_ALARM_LSB) & SOC_RTC_CONTROL_LOAD_ALARM_MASK)
601 
602 #define SOC_RTC_TIME_ADDRESS                     0x000000a0
603 #define SOC_RTC_TIME_OFFSET                      0x000000a0
604 #define SOC_RTC_TIME_WEEK_DAY_MSB                26
605 #define SOC_RTC_TIME_WEEK_DAY_LSB                24
606 #define SOC_RTC_TIME_WEEK_DAY_MASK               0x07000000
607 #define SOC_RTC_TIME_WEEK_DAY_GET(x)             (((x) & SOC_RTC_TIME_WEEK_DAY_MASK) >> SOC_RTC_TIME_WEEK_DAY_LSB)
608 #define SOC_RTC_TIME_WEEK_DAY_SET(x)             (((x) << SOC_RTC_TIME_WEEK_DAY_LSB) & SOC_RTC_TIME_WEEK_DAY_MASK)
609 #define SOC_RTC_TIME_HOUR_MSB                    21
610 #define SOC_RTC_TIME_HOUR_LSB                    16
611 #define SOC_RTC_TIME_HOUR_MASK                   0x003f0000
612 #define SOC_RTC_TIME_HOUR_GET(x)                 (((x) & SOC_RTC_TIME_HOUR_MASK) >> SOC_RTC_TIME_HOUR_LSB)
613 #define SOC_RTC_TIME_HOUR_SET(x)                 (((x) << SOC_RTC_TIME_HOUR_LSB) & SOC_RTC_TIME_HOUR_MASK)
614 #define SOC_RTC_TIME_MINUTE_MSB                  14
615 #define SOC_RTC_TIME_MINUTE_LSB                  8
616 #define SOC_RTC_TIME_MINUTE_MASK                 0x00007f00
617 #define SOC_RTC_TIME_MINUTE_GET(x)               (((x) & SOC_RTC_TIME_MINUTE_MASK) >> SOC_RTC_TIME_MINUTE_LSB)
618 #define SOC_RTC_TIME_MINUTE_SET(x)               (((x) << SOC_RTC_TIME_MINUTE_LSB) & SOC_RTC_TIME_MINUTE_MASK)
619 #define SOC_RTC_TIME_SECOND_MSB                  6
620 #define SOC_RTC_TIME_SECOND_LSB                  0
621 #define SOC_RTC_TIME_SECOND_MASK                 0x0000007f
622 #define SOC_RTC_TIME_SECOND_GET(x)               (((x) & SOC_RTC_TIME_SECOND_MASK) >> SOC_RTC_TIME_SECOND_LSB)
623 #define SOC_RTC_TIME_SECOND_SET(x)               (((x) << SOC_RTC_TIME_SECOND_LSB) & SOC_RTC_TIME_SECOND_MASK)
624 
625 #define SOC_RTC_DATE_ADDRESS                     0x000000a4
626 #define SOC_RTC_DATE_OFFSET                      0x000000a4
627 #define SOC_RTC_DATE_YEAR_MSB                    23
628 #define SOC_RTC_DATE_YEAR_LSB                    16
629 #define SOC_RTC_DATE_YEAR_MASK                   0x00ff0000
630 #define SOC_RTC_DATE_YEAR_GET(x)                 (((x) & SOC_RTC_DATE_YEAR_MASK) >> SOC_RTC_DATE_YEAR_LSB)
631 #define SOC_RTC_DATE_YEAR_SET(x)                 (((x) << SOC_RTC_DATE_YEAR_LSB) & SOC_RTC_DATE_YEAR_MASK)
632 #define SOC_RTC_DATE_MONTH_MSB                   12
633 #define SOC_RTC_DATE_MONTH_LSB                   8
634 #define SOC_RTC_DATE_MONTH_MASK                  0x00001f00
635 #define SOC_RTC_DATE_MONTH_GET(x)                (((x) & SOC_RTC_DATE_MONTH_MASK) >> SOC_RTC_DATE_MONTH_LSB)
636 #define SOC_RTC_DATE_MONTH_SET(x)                (((x) << SOC_RTC_DATE_MONTH_LSB) & SOC_RTC_DATE_MONTH_MASK)
637 #define SOC_RTC_DATE_MONTH_DAY_MSB               5
638 #define SOC_RTC_DATE_MONTH_DAY_LSB               0
639 #define SOC_RTC_DATE_MONTH_DAY_MASK              0x0000003f
640 #define SOC_RTC_DATE_MONTH_DAY_GET(x)            (((x) & SOC_RTC_DATE_MONTH_DAY_MASK) >> SOC_RTC_DATE_MONTH_DAY_LSB)
641 #define SOC_RTC_DATE_MONTH_DAY_SET(x)            (((x) << SOC_RTC_DATE_MONTH_DAY_LSB) & SOC_RTC_DATE_MONTH_DAY_MASK)
642 
643 #define SOC_RTC_SET_TIME_ADDRESS                 0x000000a8
644 #define SOC_RTC_SET_TIME_OFFSET                  0x000000a8
645 #define SOC_RTC_SET_TIME_WEEK_DAY_MSB            26
646 #define SOC_RTC_SET_TIME_WEEK_DAY_LSB            24
647 #define SOC_RTC_SET_TIME_WEEK_DAY_MASK           0x07000000
648 #define SOC_RTC_SET_TIME_WEEK_DAY_GET(x)         (((x) & SOC_RTC_SET_TIME_WEEK_DAY_MASK) >> SOC_RTC_SET_TIME_WEEK_DAY_LSB)
649 #define SOC_RTC_SET_TIME_WEEK_DAY_SET(x)         (((x) << SOC_RTC_SET_TIME_WEEK_DAY_LSB) & SOC_RTC_SET_TIME_WEEK_DAY_MASK)
650 #define SOC_RTC_SET_TIME_HOUR_MSB                21
651 #define SOC_RTC_SET_TIME_HOUR_LSB                16
652 #define SOC_RTC_SET_TIME_HOUR_MASK               0x003f0000
653 #define SOC_RTC_SET_TIME_HOUR_GET(x)             (((x) & SOC_RTC_SET_TIME_HOUR_MASK) >> SOC_RTC_SET_TIME_HOUR_LSB)
654 #define SOC_RTC_SET_TIME_HOUR_SET(x)             (((x) << SOC_RTC_SET_TIME_HOUR_LSB) & SOC_RTC_SET_TIME_HOUR_MASK)
655 #define SOC_RTC_SET_TIME_MINUTE_MSB              14
656 #define SOC_RTC_SET_TIME_MINUTE_LSB              8
657 #define SOC_RTC_SET_TIME_MINUTE_MASK             0x00007f00
658 #define SOC_RTC_SET_TIME_MINUTE_GET(x)           (((x) & SOC_RTC_SET_TIME_MINUTE_MASK) >> SOC_RTC_SET_TIME_MINUTE_LSB)
659 #define SOC_RTC_SET_TIME_MINUTE_SET(x)           (((x) << SOC_RTC_SET_TIME_MINUTE_LSB) & SOC_RTC_SET_TIME_MINUTE_MASK)
660 #define SOC_RTC_SET_TIME_SECOND_MSB              6
661 #define SOC_RTC_SET_TIME_SECOND_LSB              0
662 #define SOC_RTC_SET_TIME_SECOND_MASK             0x0000007f
663 #define SOC_RTC_SET_TIME_SECOND_GET(x)           (((x) & SOC_RTC_SET_TIME_SECOND_MASK) >> SOC_RTC_SET_TIME_SECOND_LSB)
664 #define SOC_RTC_SET_TIME_SECOND_SET(x)           (((x) << SOC_RTC_SET_TIME_SECOND_LSB) & SOC_RTC_SET_TIME_SECOND_MASK)
665 
666 #define SOC_RTC_SET_DATE_ADDRESS                 0x000000ac
667 #define SOC_RTC_SET_DATE_OFFSET                  0x000000ac
668 #define SOC_RTC_SET_DATE_YEAR_MSB                23
669 #define SOC_RTC_SET_DATE_YEAR_LSB                16
670 #define SOC_RTC_SET_DATE_YEAR_MASK               0x00ff0000
671 #define SOC_RTC_SET_DATE_YEAR_GET(x)             (((x) & SOC_RTC_SET_DATE_YEAR_MASK) >> SOC_RTC_SET_DATE_YEAR_LSB)
672 #define SOC_RTC_SET_DATE_YEAR_SET(x)             (((x) << SOC_RTC_SET_DATE_YEAR_LSB) & SOC_RTC_SET_DATE_YEAR_MASK)
673 #define SOC_RTC_SET_DATE_MONTH_MSB               12
674 #define SOC_RTC_SET_DATE_MONTH_LSB               8
675 #define SOC_RTC_SET_DATE_MONTH_MASK              0x00001f00
676 #define SOC_RTC_SET_DATE_MONTH_GET(x)            (((x) & SOC_RTC_SET_DATE_MONTH_MASK) >> SOC_RTC_SET_DATE_MONTH_LSB)
677 #define SOC_RTC_SET_DATE_MONTH_SET(x)            (((x) << SOC_RTC_SET_DATE_MONTH_LSB) & SOC_RTC_SET_DATE_MONTH_MASK)
678 #define SOC_RTC_SET_DATE_MONTH_DAY_MSB           5
679 #define SOC_RTC_SET_DATE_MONTH_DAY_LSB           0
680 #define SOC_RTC_SET_DATE_MONTH_DAY_MASK          0x0000003f
681 #define SOC_RTC_SET_DATE_MONTH_DAY_GET(x)        (((x) & SOC_RTC_SET_DATE_MONTH_DAY_MASK) >> SOC_RTC_SET_DATE_MONTH_DAY_LSB)
682 #define SOC_RTC_SET_DATE_MONTH_DAY_SET(x)        (((x) << SOC_RTC_SET_DATE_MONTH_DAY_LSB) & SOC_RTC_SET_DATE_MONTH_DAY_MASK)
683 
684 #define SOC_RTC_SET_ALARM_ADDRESS                0x000000b0
685 #define SOC_RTC_SET_ALARM_OFFSET                 0x000000b0
686 #define SOC_RTC_SET_ALARM_HOUR_MSB               21
687 #define SOC_RTC_SET_ALARM_HOUR_LSB               16
688 #define SOC_RTC_SET_ALARM_HOUR_MASK              0x003f0000
689 #define SOC_RTC_SET_ALARM_HOUR_GET(x)            (((x) & SOC_RTC_SET_ALARM_HOUR_MASK) >> SOC_RTC_SET_ALARM_HOUR_LSB)
690 #define SOC_RTC_SET_ALARM_HOUR_SET(x)            (((x) << SOC_RTC_SET_ALARM_HOUR_LSB) & SOC_RTC_SET_ALARM_HOUR_MASK)
691 #define SOC_RTC_SET_ALARM_MINUTE_MSB             14
692 #define SOC_RTC_SET_ALARM_MINUTE_LSB             8
693 #define SOC_RTC_SET_ALARM_MINUTE_MASK            0x00007f00
694 #define SOC_RTC_SET_ALARM_MINUTE_GET(x)          (((x) & SOC_RTC_SET_ALARM_MINUTE_MASK) >> SOC_RTC_SET_ALARM_MINUTE_LSB)
695 #define SOC_RTC_SET_ALARM_MINUTE_SET(x)          (((x) << SOC_RTC_SET_ALARM_MINUTE_LSB) & SOC_RTC_SET_ALARM_MINUTE_MASK)
696 #define SOC_RTC_SET_ALARM_SECOND_MSB             6
697 #define SOC_RTC_SET_ALARM_SECOND_LSB             0
698 #define SOC_RTC_SET_ALARM_SECOND_MASK            0x0000007f
699 #define SOC_RTC_SET_ALARM_SECOND_GET(x)          (((x) & SOC_RTC_SET_ALARM_SECOND_MASK) >> SOC_RTC_SET_ALARM_SECOND_LSB)
700 #define SOC_RTC_SET_ALARM_SECOND_SET(x)          (((x) << SOC_RTC_SET_ALARM_SECOND_LSB) & SOC_RTC_SET_ALARM_SECOND_MASK)
701 
702 #define SOC_RTC_CONFIG_ADDRESS                   0x000000b4
703 #define SOC_RTC_CONFIG_OFFSET                    0x000000b4
704 #define SOC_RTC_CONFIG_BCD_MSB                   2
705 #define SOC_RTC_CONFIG_BCD_LSB                   2
706 #define SOC_RTC_CONFIG_BCD_MASK                  0x00000004
707 #define SOC_RTC_CONFIG_BCD_GET(x)                (((x) & SOC_RTC_CONFIG_BCD_MASK) >> SOC_RTC_CONFIG_BCD_LSB)
708 #define SOC_RTC_CONFIG_BCD_SET(x)                (((x) << SOC_RTC_CONFIG_BCD_LSB) & SOC_RTC_CONFIG_BCD_MASK)
709 #define SOC_RTC_CONFIG_TWELVE_HOUR_MSB           1
710 #define SOC_RTC_CONFIG_TWELVE_HOUR_LSB           1
711 #define SOC_RTC_CONFIG_TWELVE_HOUR_MASK          0x00000002
712 #define SOC_RTC_CONFIG_TWELVE_HOUR_GET(x)        (((x) & SOC_RTC_CONFIG_TWELVE_HOUR_MASK) >> SOC_RTC_CONFIG_TWELVE_HOUR_LSB)
713 #define SOC_RTC_CONFIG_TWELVE_HOUR_SET(x)        (((x) << SOC_RTC_CONFIG_TWELVE_HOUR_LSB) & SOC_RTC_CONFIG_TWELVE_HOUR_MASK)
714 #define SOC_RTC_CONFIG_DSE_MSB                   0
715 #define SOC_RTC_CONFIG_DSE_LSB                   0
716 #define SOC_RTC_CONFIG_DSE_MASK                  0x00000001
717 #define SOC_RTC_CONFIG_DSE_GET(x)                (((x) & SOC_RTC_CONFIG_DSE_MASK) >> SOC_RTC_CONFIG_DSE_LSB)
718 #define SOC_RTC_CONFIG_DSE_SET(x)                (((x) << SOC_RTC_CONFIG_DSE_LSB) & SOC_RTC_CONFIG_DSE_MASK)
719 
720 #define SOC_RTC_ALARM_STATUS_ADDRESS             0x000000b8
721 #define SOC_RTC_ALARM_STATUS_OFFSET              0x000000b8
722 #define SOC_RTC_ALARM_STATUS_ENABLE_MSB          1
723 #define SOC_RTC_ALARM_STATUS_ENABLE_LSB          1
724 #define SOC_RTC_ALARM_STATUS_ENABLE_MASK         0x00000002
725 #define SOC_RTC_ALARM_STATUS_ENABLE_GET(x)       (((x) & SOC_RTC_ALARM_STATUS_ENABLE_MASK) >> SOC_RTC_ALARM_STATUS_ENABLE_LSB)
726 #define SOC_RTC_ALARM_STATUS_ENABLE_SET(x)       (((x) << SOC_RTC_ALARM_STATUS_ENABLE_LSB) & SOC_RTC_ALARM_STATUS_ENABLE_MASK)
727 #define SOC_RTC_ALARM_STATUS_INTERRUPT_MSB       0
728 #define SOC_RTC_ALARM_STATUS_INTERRUPT_LSB       0
729 #define SOC_RTC_ALARM_STATUS_INTERRUPT_MASK      0x00000001
730 #define SOC_RTC_ALARM_STATUS_INTERRUPT_GET(x)    (((x) & SOC_RTC_ALARM_STATUS_INTERRUPT_MASK) >> SOC_RTC_ALARM_STATUS_INTERRUPT_LSB)
731 #define SOC_RTC_ALARM_STATUS_INTERRUPT_SET(x)    (((x) << SOC_RTC_ALARM_STATUS_INTERRUPT_LSB) & SOC_RTC_ALARM_STATUS_INTERRUPT_MASK)
732 
733 #define SOC_UART_WAKEUP_ADDRESS                  0x000000bc
734 #define SOC_UART_WAKEUP_OFFSET                   0x000000bc
735 #define SOC_UART_WAKEUP_ENABLE_MSB               0
736 #define SOC_UART_WAKEUP_ENABLE_LSB               0
737 #define SOC_UART_WAKEUP_ENABLE_MASK              0x00000001
738 #define SOC_UART_WAKEUP_ENABLE_GET(x)            (((x) & SOC_UART_WAKEUP_ENABLE_MASK) >> SOC_UART_WAKEUP_ENABLE_LSB)
739 #define SOC_UART_WAKEUP_ENABLE_SET(x)            (((x) << SOC_UART_WAKEUP_ENABLE_LSB) & SOC_UART_WAKEUP_ENABLE_MASK)
740 
741 #define SOC_RESET_CAUSE_ADDRESS                  0x000000c0
742 #define SOC_RESET_CAUSE_OFFSET                   0x000000c0
743 #define SOC_RESET_CAUSE_LAST_MSB                 2
744 #define SOC_RESET_CAUSE_LAST_LSB                 0
745 #define SOC_RESET_CAUSE_LAST_MASK                0x00000007
746 #define SOC_RESET_CAUSE_LAST_GET(x)              (((x) & SOC_RESET_CAUSE_LAST_MASK) >> SOC_RESET_CAUSE_LAST_LSB)
747 #define SOC_RESET_CAUSE_LAST_SET(x)              (((x) << SOC_RESET_CAUSE_LAST_LSB) & SOC_RESET_CAUSE_LAST_MASK)
748 
749 #define SOC_SYSTEM_SLEEP_ADDRESS                 0x000000c4
750 #define SOC_SYSTEM_SLEEP_OFFSET                  0x000000c4
751 #define SOC_SYSTEM_SLEEP_MCI_MSB                 5
752 #define SOC_SYSTEM_SLEEP_MCI_LSB                 5
753 #define SOC_SYSTEM_SLEEP_MCI_MASK                0x00000020
754 #define SOC_SYSTEM_SLEEP_MCI_GET(x)              (((x) & SOC_SYSTEM_SLEEP_MCI_MASK) >> SOC_SYSTEM_SLEEP_MCI_LSB)
755 #define SOC_SYSTEM_SLEEP_MCI_SET(x)              (((x) << SOC_SYSTEM_SLEEP_MCI_LSB) & SOC_SYSTEM_SLEEP_MCI_MASK)
756 #define SOC_SYSTEM_SLEEP_HOST_IF_MSB             4
757 #define SOC_SYSTEM_SLEEP_HOST_IF_LSB             4
758 #define SOC_SYSTEM_SLEEP_HOST_IF_MASK            0x00000010
759 #define SOC_SYSTEM_SLEEP_HOST_IF_GET(x)          (((x) & SOC_SYSTEM_SLEEP_HOST_IF_MASK) >> SOC_SYSTEM_SLEEP_HOST_IF_LSB)
760 #define SOC_SYSTEM_SLEEP_HOST_IF_SET(x)          (((x) << SOC_SYSTEM_SLEEP_HOST_IF_LSB) & SOC_SYSTEM_SLEEP_HOST_IF_MASK)
761 #define SOC_SYSTEM_SLEEP_MBOX_MSB                3
762 #define SOC_SYSTEM_SLEEP_MBOX_LSB                3
763 #define SOC_SYSTEM_SLEEP_MBOX_MASK               0x00000008
764 #define SOC_SYSTEM_SLEEP_MBOX_GET(x)             (((x) & SOC_SYSTEM_SLEEP_MBOX_MASK) >> SOC_SYSTEM_SLEEP_MBOX_LSB)
765 #define SOC_SYSTEM_SLEEP_MBOX_SET(x)             (((x) << SOC_SYSTEM_SLEEP_MBOX_LSB) & SOC_SYSTEM_SLEEP_MBOX_MASK)
766 #define SOC_SYSTEM_SLEEP_MAC_IF_MSB              2
767 #define SOC_SYSTEM_SLEEP_MAC_IF_LSB              2
768 #define SOC_SYSTEM_SLEEP_MAC_IF_MASK             0x00000004
769 #define SOC_SYSTEM_SLEEP_MAC_IF_GET(x)           (((x) & SOC_SYSTEM_SLEEP_MAC_IF_MASK) >> SOC_SYSTEM_SLEEP_MAC_IF_LSB)
770 #define SOC_SYSTEM_SLEEP_MAC_IF_SET(x)           (((x) << SOC_SYSTEM_SLEEP_MAC_IF_LSB) & SOC_SYSTEM_SLEEP_MAC_IF_MASK)
771 #define SOC_SYSTEM_SLEEP_LIGHT_MSB               1
772 #define SOC_SYSTEM_SLEEP_LIGHT_LSB               1
773 #define SOC_SYSTEM_SLEEP_LIGHT_MASK              0x00000002
774 #define SOC_SYSTEM_SLEEP_LIGHT_GET(x)            (((x) & SOC_SYSTEM_SLEEP_LIGHT_MASK) >> SOC_SYSTEM_SLEEP_LIGHT_LSB)
775 #define SOC_SYSTEM_SLEEP_LIGHT_SET(x)            (((x) << SOC_SYSTEM_SLEEP_LIGHT_LSB) & SOC_SYSTEM_SLEEP_LIGHT_MASK)
776 #define SOC_SYSTEM_SLEEP_DISABLE_MSB             0
777 #define SOC_SYSTEM_SLEEP_DISABLE_LSB             0
778 #define SOC_SYSTEM_SLEEP_DISABLE_MASK            0x00000001
779 #define SOC_SYSTEM_SLEEP_DISABLE_GET(x)          (((x) & SOC_SYSTEM_SLEEP_DISABLE_MASK) >> SOC_SYSTEM_SLEEP_DISABLE_LSB)
780 #define SOC_SYSTEM_SLEEP_DISABLE_SET(x)          (((x) << SOC_SYSTEM_SLEEP_DISABLE_LSB) & SOC_SYSTEM_SLEEP_DISABLE_MASK)
781 
782 #define SOC_SDIO_WRAPPER_ADDRESS                 0x000000c8
783 #define SOC_SDIO_WRAPPER_OFFSET                  0x000000c8
784 #define SOC_SDIO_WRAPPER_SLEEP_MSB               3
785 #define SOC_SDIO_WRAPPER_SLEEP_LSB               3
786 #define SOC_SDIO_WRAPPER_SLEEP_MASK              0x00000008
787 #define SOC_SDIO_WRAPPER_SLEEP_GET(x)            (((x) & SOC_SDIO_WRAPPER_SLEEP_MASK) >> SOC_SDIO_WRAPPER_SLEEP_LSB)
788 #define SOC_SDIO_WRAPPER_SLEEP_SET(x)            (((x) << SOC_SDIO_WRAPPER_SLEEP_LSB) & SOC_SDIO_WRAPPER_SLEEP_MASK)
789 #define SOC_SDIO_WRAPPER_WAKEUP_MSB              2
790 #define SOC_SDIO_WRAPPER_WAKEUP_LSB              2
791 #define SOC_SDIO_WRAPPER_WAKEUP_MASK             0x00000004
792 #define SOC_SDIO_WRAPPER_WAKEUP_GET(x)           (((x) & SOC_SDIO_WRAPPER_WAKEUP_MASK) >> SOC_SDIO_WRAPPER_WAKEUP_LSB)
793 #define SOC_SDIO_WRAPPER_WAKEUP_SET(x)           (((x) << SOC_SDIO_WRAPPER_WAKEUP_LSB) & SOC_SDIO_WRAPPER_WAKEUP_MASK)
794 #define SOC_SDIO_WRAPPER_SOC_ON_MSB              1
795 #define SOC_SDIO_WRAPPER_SOC_ON_LSB              1
796 #define SOC_SDIO_WRAPPER_SOC_ON_MASK             0x00000002
797 #define SOC_SDIO_WRAPPER_SOC_ON_GET(x)           (((x) & SOC_SDIO_WRAPPER_SOC_ON_MASK) >> SOC_SDIO_WRAPPER_SOC_ON_LSB)
798 #define SOC_SDIO_WRAPPER_SOC_ON_SET(x)           (((x) << SOC_SDIO_WRAPPER_SOC_ON_LSB) & SOC_SDIO_WRAPPER_SOC_ON_MASK)
799 #define SOC_SDIO_WRAPPER_ON_MSB                  0
800 #define SOC_SDIO_WRAPPER_ON_LSB                  0
801 #define SOC_SDIO_WRAPPER_ON_MASK                 0x00000001
802 #define SOC_SDIO_WRAPPER_ON_GET(x)               (((x) & SOC_SDIO_WRAPPER_ON_MASK) >> SOC_SDIO_WRAPPER_ON_LSB)
803 #define SOC_SDIO_WRAPPER_ON_SET(x)               (((x) << SOC_SDIO_WRAPPER_ON_LSB) & SOC_SDIO_WRAPPER_ON_MASK)
804 
805 #define SOC_INT_SLEEP_MASK_ADDRESS               0x000000cc
806 #define SOC_INT_SLEEP_MASK_OFFSET                0x000000cc
807 #define SOC_INT_SLEEP_MASK_BITMAP_MSB            31
808 #define SOC_INT_SLEEP_MASK_BITMAP_LSB            0
809 #define SOC_INT_SLEEP_MASK_BITMAP_MASK           0xffffffff
810 #define SOC_INT_SLEEP_MASK_BITMAP_GET(x)         (((x) & SOC_INT_SLEEP_MASK_BITMAP_MASK) >> SOC_INT_SLEEP_MASK_BITMAP_LSB)
811 #define SOC_INT_SLEEP_MASK_BITMAP_SET(x)         (((x) << SOC_INT_SLEEP_MASK_BITMAP_LSB) & SOC_INT_SLEEP_MASK_BITMAP_MASK)
812 
813 #define SOC_LPO_CAL_TIME_ADDRESS                 0x000000d4
814 #define SOC_LPO_CAL_TIME_OFFSET                  0x000000d4
815 #define SOC_LPO_CAL_TIME_LENGTH_MSB              13
816 #define SOC_LPO_CAL_TIME_LENGTH_LSB              0
817 #define SOC_LPO_CAL_TIME_LENGTH_MASK             0x00003fff
818 #define SOC_LPO_CAL_TIME_LENGTH_GET(x)           (((x) & SOC_LPO_CAL_TIME_LENGTH_MASK) >> SOC_LPO_CAL_TIME_LENGTH_LSB)
819 #define SOC_LPO_CAL_TIME_LENGTH_SET(x)           (((x) << SOC_LPO_CAL_TIME_LENGTH_LSB) & SOC_LPO_CAL_TIME_LENGTH_MASK)
820 
821 #define SOC_LPO_INIT_DIVIDEND_INT_ADDRESS        0x000000d8
822 #define SOC_LPO_INIT_DIVIDEND_INT_OFFSET         0x000000d8
823 #define SOC_LPO_INIT_DIVIDEND_INT_VALUE_MSB      23
824 #define SOC_LPO_INIT_DIVIDEND_INT_VALUE_LSB      0
825 #define SOC_LPO_INIT_DIVIDEND_INT_VALUE_MASK     0x00ffffff
826 #define SOC_LPO_INIT_DIVIDEND_INT_VALUE_GET(x)   (((x) & SOC_LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> SOC_LPO_INIT_DIVIDEND_INT_VALUE_LSB)
827 #define SOC_LPO_INIT_DIVIDEND_INT_VALUE_SET(x)   (((x) << SOC_LPO_INIT_DIVIDEND_INT_VALUE_LSB) & SOC_LPO_INIT_DIVIDEND_INT_VALUE_MASK)
828 
829 #define SOC_LPO_INIT_DIVIDEND_FRACTION_ADDRESS   0x000000dc
830 #define SOC_LPO_INIT_DIVIDEND_FRACTION_OFFSET    0x000000dc
831 #define SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10
832 #define SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0
833 #define SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff
834 #define SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) (((x) & SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB)
835 #define SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) (((x) << SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK)
836 
837 #define SOC_LPO_CAL_ADDRESS                      0x000000e0
838 #define SOC_LPO_CAL_OFFSET                       0x000000e0
839 #define SOC_LPO_CAL_ENABLE_MSB                   20
840 #define SOC_LPO_CAL_ENABLE_LSB                   20
841 #define SOC_LPO_CAL_ENABLE_MASK                  0x00100000
842 #define SOC_LPO_CAL_ENABLE_GET(x)                (((x) & SOC_LPO_CAL_ENABLE_MASK) >> SOC_LPO_CAL_ENABLE_LSB)
843 #define SOC_LPO_CAL_ENABLE_SET(x)                (((x) << SOC_LPO_CAL_ENABLE_LSB) & SOC_LPO_CAL_ENABLE_MASK)
844 #define SOC_LPO_CAL_COUNT_MSB                    19
845 #define SOC_LPO_CAL_COUNT_LSB                    0
846 #define SOC_LPO_CAL_COUNT_MASK                   0x000fffff
847 #define SOC_LPO_CAL_COUNT_GET(x)                 (((x) & SOC_LPO_CAL_COUNT_MASK) >> SOC_LPO_CAL_COUNT_LSB)
848 #define SOC_LPO_CAL_COUNT_SET(x)                 (((x) << SOC_LPO_CAL_COUNT_LSB) & SOC_LPO_CAL_COUNT_MASK)
849 
850 #define SOC_LPO_CAL_TEST_CONTROL_ADDRESS         0x000000e4
851 #define SOC_LPO_CAL_TEST_CONTROL_OFFSET          0x000000e4
852 #define SOC_LPO_CAL_TEST_CONTROL_ENABLE_MSB      16
853 #define SOC_LPO_CAL_TEST_CONTROL_ENABLE_LSB      16
854 #define SOC_LPO_CAL_TEST_CONTROL_ENABLE_MASK     0x00010000
855 #define SOC_LPO_CAL_TEST_CONTROL_ENABLE_GET(x)   (((x) & SOC_LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> SOC_LPO_CAL_TEST_CONTROL_ENABLE_LSB)
856 #define SOC_LPO_CAL_TEST_CONTROL_ENABLE_SET(x)   (((x) << SOC_LPO_CAL_TEST_CONTROL_ENABLE_LSB) & SOC_LPO_CAL_TEST_CONTROL_ENABLE_MASK)
857 #define SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB  15
858 #define SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB  0
859 #define SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000ffff
860 #define SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) (((x) & SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB)
861 #define SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) (((x) << SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK)
862 
863 #define SOC_LPO_CAL_TEST_STATUS_ADDRESS          0x000000e8
864 #define SOC_LPO_CAL_TEST_STATUS_OFFSET           0x000000e8
865 #define SOC_LPO_CAL_TEST_STATUS_READY_MSB        16
866 #define SOC_LPO_CAL_TEST_STATUS_READY_LSB        16
867 #define SOC_LPO_CAL_TEST_STATUS_READY_MASK       0x00010000
868 #define SOC_LPO_CAL_TEST_STATUS_READY_GET(x)     (((x) & SOC_LPO_CAL_TEST_STATUS_READY_MASK) >> SOC_LPO_CAL_TEST_STATUS_READY_LSB)
869 #define SOC_LPO_CAL_TEST_STATUS_READY_SET(x)     (((x) << SOC_LPO_CAL_TEST_STATUS_READY_LSB) & SOC_LPO_CAL_TEST_STATUS_READY_MASK)
870 #define SOC_LPO_CAL_TEST_STATUS_COUNT_MSB        15
871 #define SOC_LPO_CAL_TEST_STATUS_COUNT_LSB        0
872 #define SOC_LPO_CAL_TEST_STATUS_COUNT_MASK       0x0000ffff
873 #define SOC_LPO_CAL_TEST_STATUS_COUNT_GET(x)     (((x) & SOC_LPO_CAL_TEST_STATUS_COUNT_MASK) >> SOC_LPO_CAL_TEST_STATUS_COUNT_LSB)
874 #define SOC_LPO_CAL_TEST_STATUS_COUNT_SET(x)     (((x) << SOC_LPO_CAL_TEST_STATUS_COUNT_LSB) & SOC_LPO_CAL_TEST_STATUS_COUNT_MASK)
875 
876 #define LEGACY_SOC_CHIP_ID_ADDRESS               0x000000ec
877 #define LEGACY_SOC_CHIP_ID_OFFSET                0x000000ec
878 #define LEGACY_SOC_CHIP_ID_DEVICE_ID_MSB         31
879 #define LEGACY_SOC_CHIP_ID_DEVICE_ID_LSB         16
880 #define LEGACY_SOC_CHIP_ID_DEVICE_ID_MASK        0xffff0000
881 #define LEGACY_SOC_CHIP_ID_DEVICE_ID_GET(x)      (((x) & LEGACY_SOC_CHIP_ID_DEVICE_ID_MASK) >> LEGACY_SOC_CHIP_ID_DEVICE_ID_LSB)
882 #define LEGACY_SOC_CHIP_ID_DEVICE_ID_SET(x)      (((x) << LEGACY_SOC_CHIP_ID_DEVICE_ID_LSB) & LEGACY_SOC_CHIP_ID_DEVICE_ID_MASK)
883 #define LEGACY_SOC_CHIP_ID_CONFIG_ID_MSB         15
884 #define LEGACY_SOC_CHIP_ID_CONFIG_ID_LSB         4
885 #define LEGACY_SOC_CHIP_ID_CONFIG_ID_MASK        0x0000fff0
886 #define LEGACY_SOC_CHIP_ID_CONFIG_ID_GET(x)      (((x) & LEGACY_SOC_CHIP_ID_CONFIG_ID_MASK) >> LEGACY_SOC_CHIP_ID_CONFIG_ID_LSB)
887 #define LEGACY_SOC_CHIP_ID_CONFIG_ID_SET(x)      (((x) << LEGACY_SOC_CHIP_ID_CONFIG_ID_LSB) & LEGACY_SOC_CHIP_ID_CONFIG_ID_MASK)
888 #define LEGACY_SOC_CHIP_ID_VERSION_ID_MSB        3
889 #define LEGACY_SOC_CHIP_ID_VERSION_ID_LSB        0
890 #define LEGACY_SOC_CHIP_ID_VERSION_ID_MASK       0x0000000f
891 #define LEGACY_SOC_CHIP_ID_VERSION_ID_GET(x)     (((x) & LEGACY_SOC_CHIP_ID_VERSION_ID_MASK) >> LEGACY_SOC_CHIP_ID_VERSION_ID_LSB)
892 #define LEGACY_SOC_CHIP_ID_VERSION_ID_SET(x)     (((x) << LEGACY_SOC_CHIP_ID_VERSION_ID_LSB) & LEGACY_SOC_CHIP_ID_VERSION_ID_MASK)
893 
894 #define SOC_CHIP_ID_ADDRESS                      0x000000f0
895 #define SOC_CHIP_ID_OFFSET                       0x000000f0
896 #define SOC_CHIP_ID_DEVICE_ID_MSB                31
897 #define SOC_CHIP_ID_DEVICE_ID_LSB                16
898 #define SOC_CHIP_ID_DEVICE_ID_MASK               0xffff0000
899 #define SOC_CHIP_ID_DEVICE_ID_GET(x)             (((x) & SOC_CHIP_ID_DEVICE_ID_MASK) >> SOC_CHIP_ID_DEVICE_ID_LSB)
900 #define SOC_CHIP_ID_DEVICE_ID_SET(x)             (((x) << SOC_CHIP_ID_DEVICE_ID_LSB) & SOC_CHIP_ID_DEVICE_ID_MASK)
901 #define SOC_CHIP_ID_CONFIG_ID_MSB                15
902 #define SOC_CHIP_ID_CONFIG_ID_LSB                4
903 #define SOC_CHIP_ID_CONFIG_ID_MASK               0x0000fff0
904 #define SOC_CHIP_ID_CONFIG_ID_GET(x)             (((x) & SOC_CHIP_ID_CONFIG_ID_MASK) >> SOC_CHIP_ID_CONFIG_ID_LSB)
905 #define SOC_CHIP_ID_CONFIG_ID_SET(x)             (((x) << SOC_CHIP_ID_CONFIG_ID_LSB) & SOC_CHIP_ID_CONFIG_ID_MASK)
906 #define SOC_CHIP_ID_VERSION_ID_MSB               3
907 #define SOC_CHIP_ID_VERSION_ID_LSB               0
908 #define SOC_CHIP_ID_VERSION_ID_MASK              0x0000000f
909 #define SOC_CHIP_ID_VERSION_ID_GET(x)            (((x) & SOC_CHIP_ID_VERSION_ID_MASK) >> SOC_CHIP_ID_VERSION_ID_LSB)
910 #define SOC_CHIP_ID_VERSION_ID_SET(x)            (((x) << SOC_CHIP_ID_VERSION_ID_LSB) & SOC_CHIP_ID_VERSION_ID_MASK)
911 
912 #define SOC_POWER_REG_ADDRESS                    0x0000010c
913 #define SOC_POWER_REG_OFFSET                     0x0000010c
914 #define SOC_POWER_REG_DISCON_MODE_EN_MSB         16
915 #define SOC_POWER_REG_DISCON_MODE_EN_LSB         16
916 #define SOC_POWER_REG_DISCON_MODE_EN_MASK        0x00010000
917 #define SOC_POWER_REG_DISCON_MODE_EN_GET(x)      (((x) & SOC_POWER_REG_DISCON_MODE_EN_MASK) >> SOC_POWER_REG_DISCON_MODE_EN_LSB)
918 #define SOC_POWER_REG_DISCON_MODE_EN_SET(x)      (((x) << SOC_POWER_REG_DISCON_MODE_EN_LSB) & SOC_POWER_REG_DISCON_MODE_EN_MASK)
919 #define SOC_POWER_REG_DEEP_SLEEP_EN_MSB          15
920 #define SOC_POWER_REG_DEEP_SLEEP_EN_LSB          15
921 #define SOC_POWER_REG_DEEP_SLEEP_EN_MASK         0x00008000
922 #define SOC_POWER_REG_DEEP_SLEEP_EN_GET(x)       (((x) & SOC_POWER_REG_DEEP_SLEEP_EN_MASK) >> SOC_POWER_REG_DEEP_SLEEP_EN_LSB)
923 #define SOC_POWER_REG_DEEP_SLEEP_EN_SET(x)       (((x) << SOC_POWER_REG_DEEP_SLEEP_EN_LSB) & SOC_POWER_REG_DEEP_SLEEP_EN_MASK)
924 #define SOC_POWER_REG_DEBUG_EN_MSB               14
925 #define SOC_POWER_REG_DEBUG_EN_LSB               14
926 #define SOC_POWER_REG_DEBUG_EN_MASK              0x00004000
927 #define SOC_POWER_REG_DEBUG_EN_GET(x)            (((x) & SOC_POWER_REG_DEBUG_EN_MASK) >> SOC_POWER_REG_DEBUG_EN_LSB)
928 #define SOC_POWER_REG_DEBUG_EN_SET(x)            (((x) << SOC_POWER_REG_DEBUG_EN_LSB) & SOC_POWER_REG_DEBUG_EN_MASK)
929 #define SOC_POWER_REG_WLAN_BB_PWD_EN_MSB         13
930 #define SOC_POWER_REG_WLAN_BB_PWD_EN_LSB         13
931 #define SOC_POWER_REG_WLAN_BB_PWD_EN_MASK        0x00002000
932 #define SOC_POWER_REG_WLAN_BB_PWD_EN_GET(x)      (((x) & SOC_POWER_REG_WLAN_BB_PWD_EN_MASK) >> SOC_POWER_REG_WLAN_BB_PWD_EN_LSB)
933 #define SOC_POWER_REG_WLAN_BB_PWD_EN_SET(x)      (((x) << SOC_POWER_REG_WLAN_BB_PWD_EN_LSB) & SOC_POWER_REG_WLAN_BB_PWD_EN_MASK)
934 #define SOC_POWER_REG_WLAN_MAC_PWD_EN_MSB        12
935 #define SOC_POWER_REG_WLAN_MAC_PWD_EN_LSB        12
936 #define SOC_POWER_REG_WLAN_MAC_PWD_EN_MASK       0x00001000
937 #define SOC_POWER_REG_WLAN_MAC_PWD_EN_GET(x)     (((x) & SOC_POWER_REG_WLAN_MAC_PWD_EN_MASK) >> SOC_POWER_REG_WLAN_MAC_PWD_EN_LSB)
938 #define SOC_POWER_REG_WLAN_MAC_PWD_EN_SET(x)     (((x) << SOC_POWER_REG_WLAN_MAC_PWD_EN_LSB) & SOC_POWER_REG_WLAN_MAC_PWD_EN_MASK)
939 #define SOC_POWER_REG_CPU_INT_ENABLE_MSB         7
940 #define SOC_POWER_REG_CPU_INT_ENABLE_LSB         7
941 #define SOC_POWER_REG_CPU_INT_ENABLE_MASK        0x00000080
942 #define SOC_POWER_REG_CPU_INT_ENABLE_GET(x)      (((x) & SOC_POWER_REG_CPU_INT_ENABLE_MASK) >> SOC_POWER_REG_CPU_INT_ENABLE_LSB)
943 #define SOC_POWER_REG_CPU_INT_ENABLE_SET(x)      (((x) << SOC_POWER_REG_CPU_INT_ENABLE_LSB) & SOC_POWER_REG_CPU_INT_ENABLE_MASK)
944 #define SOC_POWER_REG_WLAN_ISO_DIS_MSB           6
945 #define SOC_POWER_REG_WLAN_ISO_DIS_LSB           6
946 #define SOC_POWER_REG_WLAN_ISO_DIS_MASK          0x00000040
947 #define SOC_POWER_REG_WLAN_ISO_DIS_GET(x)        (((x) & SOC_POWER_REG_WLAN_ISO_DIS_MASK) >> SOC_POWER_REG_WLAN_ISO_DIS_LSB)
948 #define SOC_POWER_REG_WLAN_ISO_DIS_SET(x)        (((x) << SOC_POWER_REG_WLAN_ISO_DIS_LSB) & SOC_POWER_REG_WLAN_ISO_DIS_MASK)
949 #define SOC_POWER_REG_WLAN_ISO_CNTL_MSB          5
950 #define SOC_POWER_REG_WLAN_ISO_CNTL_LSB          5
951 #define SOC_POWER_REG_WLAN_ISO_CNTL_MASK         0x00000020
952 #define SOC_POWER_REG_WLAN_ISO_CNTL_GET(x)       (((x) & SOC_POWER_REG_WLAN_ISO_CNTL_MASK) >> SOC_POWER_REG_WLAN_ISO_CNTL_LSB)
953 #define SOC_POWER_REG_WLAN_ISO_CNTL_SET(x)       (((x) << SOC_POWER_REG_WLAN_ISO_CNTL_LSB) & SOC_POWER_REG_WLAN_ISO_CNTL_MASK)
954 #define SOC_POWER_REG_RADIO_PWD_EN_MSB           4
955 #define SOC_POWER_REG_RADIO_PWD_EN_LSB           4
956 #define SOC_POWER_REG_RADIO_PWD_EN_MASK          0x00000010
957 #define SOC_POWER_REG_RADIO_PWD_EN_GET(x)        (((x) & SOC_POWER_REG_RADIO_PWD_EN_MASK) >> SOC_POWER_REG_RADIO_PWD_EN_LSB)
958 #define SOC_POWER_REG_RADIO_PWD_EN_SET(x)        (((x) << SOC_POWER_REG_RADIO_PWD_EN_LSB) & SOC_POWER_REG_RADIO_PWD_EN_MASK)
959 #define SOC_POWER_REG_SOC_ISO_EN_MSB             3
960 #define SOC_POWER_REG_SOC_ISO_EN_LSB             3
961 #define SOC_POWER_REG_SOC_ISO_EN_MASK            0x00000008
962 #define SOC_POWER_REG_SOC_ISO_EN_GET(x)          (((x) & SOC_POWER_REG_SOC_ISO_EN_MASK) >> SOC_POWER_REG_SOC_ISO_EN_LSB)
963 #define SOC_POWER_REG_SOC_ISO_EN_SET(x)          (((x) << SOC_POWER_REG_SOC_ISO_EN_LSB) & SOC_POWER_REG_SOC_ISO_EN_MASK)
964 #define SOC_POWER_REG_WLAN_ISO_EN_MSB            2
965 #define SOC_POWER_REG_WLAN_ISO_EN_LSB            2
966 #define SOC_POWER_REG_WLAN_ISO_EN_MASK           0x00000004
967 #define SOC_POWER_REG_WLAN_ISO_EN_GET(x)         (((x) & SOC_POWER_REG_WLAN_ISO_EN_MASK) >> SOC_POWER_REG_WLAN_ISO_EN_LSB)
968 #define SOC_POWER_REG_WLAN_ISO_EN_SET(x)         (((x) << SOC_POWER_REG_WLAN_ISO_EN_LSB) & SOC_POWER_REG_WLAN_ISO_EN_MASK)
969 #define SOC_POWER_REG_WLAN_PWD_EN_MSB            1
970 #define SOC_POWER_REG_WLAN_PWD_EN_LSB            1
971 #define SOC_POWER_REG_WLAN_PWD_EN_MASK           0x00000002
972 #define SOC_POWER_REG_WLAN_PWD_EN_GET(x)         (((x) & SOC_POWER_REG_WLAN_PWD_EN_MASK) >> SOC_POWER_REG_WLAN_PWD_EN_LSB)
973 #define SOC_POWER_REG_WLAN_PWD_EN_SET(x)         (((x) << SOC_POWER_REG_WLAN_PWD_EN_LSB) & SOC_POWER_REG_WLAN_PWD_EN_MASK)
974 #define SOC_POWER_REG_POWER_EN_MSB               0
975 #define SOC_POWER_REG_POWER_EN_LSB               0
976 #define SOC_POWER_REG_POWER_EN_MASK              0x00000001
977 #define SOC_POWER_REG_POWER_EN_GET(x)            (((x) & SOC_POWER_REG_POWER_EN_MASK) >> SOC_POWER_REG_POWER_EN_LSB)
978 #define SOC_POWER_REG_POWER_EN_SET(x)            (((x) << SOC_POWER_REG_POWER_EN_LSB) & SOC_POWER_REG_POWER_EN_MASK)
979 
980 #define SOC_CORE_CLK_CTRL_ADDRESS                0x00000110
981 #define SOC_CORE_CLK_CTRL_OFFSET                 0x00000110
982 #define SOC_CORE_CLK_CTRL_DIV_MSB                2
983 #define SOC_CORE_CLK_CTRL_DIV_LSB                0
984 #define SOC_CORE_CLK_CTRL_DIV_MASK               0x00000007
985 #define SOC_CORE_CLK_CTRL_DIV_GET(x)             (((x) & SOC_CORE_CLK_CTRL_DIV_MASK) >> SOC_CORE_CLK_CTRL_DIV_LSB)
986 #define SOC_CORE_CLK_CTRL_DIV_SET(x)             (((x) << SOC_CORE_CLK_CTRL_DIV_LSB) & SOC_CORE_CLK_CTRL_DIV_MASK)
987 
988 #define SOC_GPIO_WAKEUP_CONTROL_ADDRESS          0x00000114
989 #define SOC_GPIO_WAKEUP_CONTROL_OFFSET           0x00000114
990 #define SOC_GPIO_WAKEUP_CONTROL_ENABLE_MSB       0
991 #define SOC_GPIO_WAKEUP_CONTROL_ENABLE_LSB       0
992 #define SOC_GPIO_WAKEUP_CONTROL_ENABLE_MASK      0x00000001
993 #define SOC_GPIO_WAKEUP_CONTROL_ENABLE_GET(x)    (((x) & SOC_GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> SOC_GPIO_WAKEUP_CONTROL_ENABLE_LSB)
994 #define SOC_GPIO_WAKEUP_CONTROL_ENABLE_SET(x)    (((x) << SOC_GPIO_WAKEUP_CONTROL_ENABLE_LSB) & SOC_GPIO_WAKEUP_CONTROL_ENABLE_MASK)
995 
996 #define SLEEP_RETENTION_ADDRESS                  0x00000214
997 #define SLEEP_RETENTION_OFFSET                   0x00000214
998 #define SLEEP_RETENTION_GREEN_SAVE_MSB           10
999 #define SLEEP_RETENTION_GREEN_SAVE_LSB           10
1000 #define SLEEP_RETENTION_GREEN_SAVE_MASK          0x00000400
1001 #define SLEEP_RETENTION_GREEN_SAVE_GET(x)        (((x) & SLEEP_RETENTION_GREEN_SAVE_MASK) >> SLEEP_RETENTION_GREEN_SAVE_LSB)
1002 #define SLEEP_RETENTION_GREEN_SAVE_SET(x)        (((x) << SLEEP_RETENTION_GREEN_SAVE_LSB) & SLEEP_RETENTION_GREEN_SAVE_MASK)
1003 #define SLEEP_RETENTION_TIME_MSB                 9
1004 #define SLEEP_RETENTION_TIME_LSB                 2
1005 #define SLEEP_RETENTION_TIME_MASK                0x000003fc
1006 #define SLEEP_RETENTION_TIME_GET(x)              (((x) & SLEEP_RETENTION_TIME_MASK) >> SLEEP_RETENTION_TIME_LSB)
1007 #define SLEEP_RETENTION_TIME_SET(x)              (((x) << SLEEP_RETENTION_TIME_LSB) & SLEEP_RETENTION_TIME_MASK)
1008 #define SLEEP_RETENTION_MODE_MSB                 1
1009 #define SLEEP_RETENTION_MODE_LSB                 1
1010 #define SLEEP_RETENTION_MODE_MASK                0x00000002
1011 #define SLEEP_RETENTION_MODE_GET(x)              (((x) & SLEEP_RETENTION_MODE_MASK) >> SLEEP_RETENTION_MODE_LSB)
1012 #define SLEEP_RETENTION_MODE_SET(x)              (((x) << SLEEP_RETENTION_MODE_LSB) & SLEEP_RETENTION_MODE_MASK)
1013 #define SLEEP_RETENTION_ENABLE_MSB               0
1014 #define SLEEP_RETENTION_ENABLE_LSB               0
1015 #define SLEEP_RETENTION_ENABLE_MASK              0x00000001
1016 #define SLEEP_RETENTION_ENABLE_GET(x)            (((x) & SLEEP_RETENTION_ENABLE_MASK) >> SLEEP_RETENTION_ENABLE_LSB)
1017 #define SLEEP_RETENTION_ENABLE_SET(x)            (((x) << SLEEP_RETENTION_ENABLE_LSB) & SLEEP_RETENTION_ENABLE_MASK)
1018 
1019 #define LP_PERF_COUNTER_ADDRESS                  0x00000284
1020 #define LP_PERF_COUNTER_OFFSET                   0x00000284
1021 #define LP_PERF_COUNTER_EN_MSB                   0
1022 #define LP_PERF_COUNTER_EN_LSB                   0
1023 #define LP_PERF_COUNTER_EN_MASK                  0x00000001
1024 #define LP_PERF_COUNTER_EN_GET(x)                (((x) & LP_PERF_COUNTER_EN_MASK) >> LP_PERF_COUNTER_EN_LSB)
1025 #define LP_PERF_COUNTER_EN_SET(x)                (((x) << LP_PERF_COUNTER_EN_LSB) & LP_PERF_COUNTER_EN_MASK)
1026 
1027 #define LP_PERF_LIGHT_SLEEP_ADDRESS              0x00000288
1028 #define LP_PERF_LIGHT_SLEEP_OFFSET               0x00000288
1029 #define LP_PERF_LIGHT_SLEEP_CNT_MSB              31
1030 #define LP_PERF_LIGHT_SLEEP_CNT_LSB              0
1031 #define LP_PERF_LIGHT_SLEEP_CNT_MASK             0xffffffff
1032 #define LP_PERF_LIGHT_SLEEP_CNT_GET(x)           (((x) & LP_PERF_LIGHT_SLEEP_CNT_MASK) >> LP_PERF_LIGHT_SLEEP_CNT_LSB)
1033 #define LP_PERF_LIGHT_SLEEP_CNT_SET(x)           (((x) << LP_PERF_LIGHT_SLEEP_CNT_LSB) & LP_PERF_LIGHT_SLEEP_CNT_MASK)
1034 
1035 #define LP_PERF_DEEP_SLEEP_ADDRESS               0x0000028c
1036 #define LP_PERF_DEEP_SLEEP_OFFSET                0x0000028c
1037 #define LP_PERF_DEEP_SLEEP_CNT_MSB               31
1038 #define LP_PERF_DEEP_SLEEP_CNT_LSB               0
1039 #define LP_PERF_DEEP_SLEEP_CNT_MASK              0xffffffff
1040 #define LP_PERF_DEEP_SLEEP_CNT_GET(x)            (((x) & LP_PERF_DEEP_SLEEP_CNT_MASK) >> LP_PERF_DEEP_SLEEP_CNT_LSB)
1041 #define LP_PERF_DEEP_SLEEP_CNT_SET(x)            (((x) << LP_PERF_DEEP_SLEEP_CNT_LSB) & LP_PERF_DEEP_SLEEP_CNT_MASK)
1042 
1043 #define LP_PERF_ON_ADDRESS                       0x00000290
1044 #define LP_PERF_ON_OFFSET                        0x00000290
1045 #define LP_PERF_ON_CNT_MSB                       31
1046 #define LP_PERF_ON_CNT_LSB                       0
1047 #define LP_PERF_ON_CNT_MASK                      0xffffffff
1048 #define LP_PERF_ON_CNT_GET(x)                    (((x) & LP_PERF_ON_CNT_MASK) >> LP_PERF_ON_CNT_LSB)
1049 #define LP_PERF_ON_CNT_SET(x)                    (((x) << LP_PERF_ON_CNT_LSB) & LP_PERF_ON_CNT_MASK)
1050 
1051 #define CHIP_MODE_ADDRESS                        0x000002a8
1052 #define CHIP_MODE_OFFSET                         0x000002a8
1053 #define CHIP_MODE_BIT_MSB                        1
1054 #define CHIP_MODE_BIT_LSB                        0
1055 #define CHIP_MODE_BIT_MASK                       0x00000003
1056 #define CHIP_MODE_BIT_GET(x)                     (((x) & CHIP_MODE_BIT_MASK) >> CHIP_MODE_BIT_LSB)
1057 #define CHIP_MODE_BIT_SET(x)                     (((x) << CHIP_MODE_BIT_LSB) & CHIP_MODE_BIT_MASK)
1058 
1059 #define CLK_REQ_FALL_EDGE_ADDRESS                0x000002ac
1060 #define CLK_REQ_FALL_EDGE_OFFSET                 0x000002ac
1061 #define CLK_REQ_FALL_EDGE_EN_MSB                 31
1062 #define CLK_REQ_FALL_EDGE_EN_LSB                 31
1063 #define CLK_REQ_FALL_EDGE_EN_MASK                0x80000000
1064 #define CLK_REQ_FALL_EDGE_EN_GET(x)              (((x) & CLK_REQ_FALL_EDGE_EN_MASK) >> CLK_REQ_FALL_EDGE_EN_LSB)
1065 #define CLK_REQ_FALL_EDGE_EN_SET(x)              (((x) << CLK_REQ_FALL_EDGE_EN_LSB) & CLK_REQ_FALL_EDGE_EN_MASK)
1066 #define CLK_REQ_FALL_EDGE_DELAY_MSB              7
1067 #define CLK_REQ_FALL_EDGE_DELAY_LSB              0
1068 #define CLK_REQ_FALL_EDGE_DELAY_MASK             0x000000ff
1069 #define CLK_REQ_FALL_EDGE_DELAY_GET(x)           (((x) & CLK_REQ_FALL_EDGE_DELAY_MASK) >> CLK_REQ_FALL_EDGE_DELAY_LSB)
1070 #define CLK_REQ_FALL_EDGE_DELAY_SET(x)           (((x) << CLK_REQ_FALL_EDGE_DELAY_LSB) & CLK_REQ_FALL_EDGE_DELAY_MASK)
1071 
1072 #define OTP_ADDRESS                              0x000002b0
1073 #define OTP_OFFSET                               0x000002b0
1074 #define OTP_LDO25_EN_MSB                         1
1075 #define OTP_LDO25_EN_LSB                         1
1076 #define OTP_LDO25_EN_MASK                        0x00000002
1077 #define OTP_LDO25_EN_GET(x)                      (((x) & OTP_LDO25_EN_MASK) >> OTP_LDO25_EN_LSB)
1078 #define OTP_LDO25_EN_SET(x)                      (((x) << OTP_LDO25_EN_LSB) & OTP_LDO25_EN_MASK)
1079 #define OTP_VDD12_EN_MSB                         0
1080 #define OTP_VDD12_EN_LSB                         0
1081 #define OTP_VDD12_EN_MASK                        0x00000001
1082 #define OTP_VDD12_EN_GET(x)                      (((x) & OTP_VDD12_EN_MASK) >> OTP_VDD12_EN_LSB)
1083 #define OTP_VDD12_EN_SET(x)                      (((x) << OTP_VDD12_EN_LSB) & OTP_VDD12_EN_MASK)
1084 
1085 #define OTP_STATUS_ADDRESS                       0x000002b4
1086 #define OTP_STATUS_OFFSET                        0x000002b4
1087 #define OTP_STATUS_LDO25_EN_READY_MSB            1
1088 #define OTP_STATUS_LDO25_EN_READY_LSB            1
1089 #define OTP_STATUS_LDO25_EN_READY_MASK           0x00000002
1090 #define OTP_STATUS_LDO25_EN_READY_GET(x)         (((x) & OTP_STATUS_LDO25_EN_READY_MASK) >> OTP_STATUS_LDO25_EN_READY_LSB)
1091 #define OTP_STATUS_LDO25_EN_READY_SET(x)         (((x) << OTP_STATUS_LDO25_EN_READY_LSB) & OTP_STATUS_LDO25_EN_READY_MASK)
1092 #define OTP_STATUS_VDD12_EN_READY_MSB            0
1093 #define OTP_STATUS_VDD12_EN_READY_LSB            0
1094 #define OTP_STATUS_VDD12_EN_READY_MASK           0x00000001
1095 #define OTP_STATUS_VDD12_EN_READY_GET(x)         (((x) & OTP_STATUS_VDD12_EN_READY_MASK) >> OTP_STATUS_VDD12_EN_READY_LSB)
1096 #define OTP_STATUS_VDD12_EN_READY_SET(x)         (((x) << OTP_STATUS_VDD12_EN_READY_LSB) & OTP_STATUS_VDD12_EN_READY_MASK)
1097 
1098 #define PMU_ADDRESS                              0x000002b8
1099 #define PMU_OFFSET                               0x000002b8
1100 #define PMU_REG_WAKEUP_TIME_SEL_MSB              1
1101 #define PMU_REG_WAKEUP_TIME_SEL_LSB              0
1102 #define PMU_REG_WAKEUP_TIME_SEL_MASK             0x00000003
1103 #define PMU_REG_WAKEUP_TIME_SEL_GET(x)           (((x) & PMU_REG_WAKEUP_TIME_SEL_MASK) >> PMU_REG_WAKEUP_TIME_SEL_LSB)
1104 #define PMU_REG_WAKEUP_TIME_SEL_SET(x)           (((x) << PMU_REG_WAKEUP_TIME_SEL_LSB) & PMU_REG_WAKEUP_TIME_SEL_MASK)
1105 
1106 #define PMU_CONFIG_ADDRESS                       0x000002bc
1107 #define PMU_CONFIG_OFFSET                        0x000002bc
1108 #define PMU_CONFIG_VALUE_MSB                     4
1109 #define PMU_CONFIG_VALUE_LSB                     0
1110 #define PMU_CONFIG_VALUE_MASK                    0x0000001f
1111 #define PMU_CONFIG_VALUE_GET(x)                  (((x) & PMU_CONFIG_VALUE_MASK) >> PMU_CONFIG_VALUE_LSB)
1112 #define PMU_CONFIG_VALUE_SET(x)                  (((x) << PMU_CONFIG_VALUE_LSB) & PMU_CONFIG_VALUE_MASK)
1113 
1114 #define PMU_PAREG_ADDRESS                        0x000002c0
1115 #define PMU_PAREG_OFFSET                         0x000002c0
1116 #define PMU_PAREG_LVL_CTR_MSB                    2
1117 #define PMU_PAREG_LVL_CTR_LSB                    0
1118 #define PMU_PAREG_LVL_CTR_MASK                   0x00000007
1119 #define PMU_PAREG_LVL_CTR_GET(x)                 (((x) & PMU_PAREG_LVL_CTR_MASK) >> PMU_PAREG_LVL_CTR_LSB)
1120 #define PMU_PAREG_LVL_CTR_SET(x)                 (((x) << PMU_PAREG_LVL_CTR_LSB) & PMU_PAREG_LVL_CTR_MASK)
1121 
1122 #define PMU_BYPASS_ADDRESS                       0x000002c4
1123 #define PMU_BYPASS_OFFSET                        0x000002c4
1124 #define PMU_BYPASS_SWREG_MSB                     2
1125 #define PMU_BYPASS_SWREG_LSB                     2
1126 #define PMU_BYPASS_SWREG_MASK                    0x00000004
1127 #define PMU_BYPASS_SWREG_GET(x)                  (((x) & PMU_BYPASS_SWREG_MASK) >> PMU_BYPASS_SWREG_LSB)
1128 #define PMU_BYPASS_SWREG_SET(x)                  (((x) << PMU_BYPASS_SWREG_LSB) & PMU_BYPASS_SWREG_MASK)
1129 #define PMU_BYPASS_DREG_MSB                      1
1130 #define PMU_BYPASS_DREG_LSB                      1
1131 #define PMU_BYPASS_DREG_MASK                     0x00000002
1132 #define PMU_BYPASS_DREG_GET(x)                   (((x) & PMU_BYPASS_DREG_MASK) >> PMU_BYPASS_DREG_LSB)
1133 #define PMU_BYPASS_DREG_SET(x)                   (((x) << PMU_BYPASS_DREG_LSB) & PMU_BYPASS_DREG_MASK)
1134 #define PMU_BYPASS_PAREG_MSB                     0
1135 #define PMU_BYPASS_PAREG_LSB                     0
1136 #define PMU_BYPASS_PAREG_MASK                    0x00000001
1137 #define PMU_BYPASS_PAREG_GET(x)                  (((x) & PMU_BYPASS_PAREG_MASK) >> PMU_BYPASS_PAREG_LSB)
1138 #define PMU_BYPASS_PAREG_SET(x)                  (((x) << PMU_BYPASS_PAREG_LSB) & PMU_BYPASS_PAREG_MASK)
1139 
1140 #define THERM_CTRL1_ADDRESS                      0x000002dc
1141 #define THERM_CTRL1_OFFSET                       0x000002dc
1142 #define THERM_CTRL1_BYPASS_MSB                   16
1143 #define THERM_CTRL1_BYPASS_LSB                   16
1144 #define THERM_CTRL1_BYPASS_MASK                  0x00010000
1145 #define THERM_CTRL1_BYPASS_GET(x)                (((x) & THERM_CTRL1_BYPASS_MASK) >> THERM_CTRL1_BYPASS_LSB)
1146 #define THERM_CTRL1_BYPASS_SET(x)                (((x) << THERM_CTRL1_BYPASS_LSB) & THERM_CTRL1_BYPASS_MASK)
1147 #define THERM_CTRL1_WIDTH_ARBITOR_MSB            15
1148 #define THERM_CTRL1_WIDTH_ARBITOR_LSB            12
1149 #define THERM_CTRL1_WIDTH_ARBITOR_MASK           0x0000f000
1150 #define THERM_CTRL1_WIDTH_ARBITOR_GET(x)         (((x) & THERM_CTRL1_WIDTH_ARBITOR_MASK) >> THERM_CTRL1_WIDTH_ARBITOR_LSB)
1151 #define THERM_CTRL1_WIDTH_ARBITOR_SET(x)         (((x) << THERM_CTRL1_WIDTH_ARBITOR_LSB) & THERM_CTRL1_WIDTH_ARBITOR_MASK)
1152 #define THERM_CTRL1_WIDTH_MSB                    11
1153 #define THERM_CTRL1_WIDTH_LSB                    5
1154 #define THERM_CTRL1_WIDTH_MASK                   0x00000fe0
1155 #define THERM_CTRL1_WIDTH_GET(x)                 (((x) & THERM_CTRL1_WIDTH_MASK) >> THERM_CTRL1_WIDTH_LSB)
1156 #define THERM_CTRL1_WIDTH_SET(x)                 (((x) << THERM_CTRL1_WIDTH_LSB) & THERM_CTRL1_WIDTH_MASK)
1157 #define THERM_CTRL1_TYPE_MSB                     4
1158 #define THERM_CTRL1_TYPE_LSB                     3
1159 #define THERM_CTRL1_TYPE_MASK                    0x00000018
1160 #define THERM_CTRL1_TYPE_GET(x)                  (((x) & THERM_CTRL1_TYPE_MASK) >> THERM_CTRL1_TYPE_LSB)
1161 #define THERM_CTRL1_TYPE_SET(x)                  (((x) << THERM_CTRL1_TYPE_LSB) & THERM_CTRL1_TYPE_MASK)
1162 #define THERM_CTRL1_MEASURE_MSB                  2
1163 #define THERM_CTRL1_MEASURE_LSB                  2
1164 #define THERM_CTRL1_MEASURE_MASK                 0x00000004
1165 #define THERM_CTRL1_MEASURE_GET(x)               (((x) & THERM_CTRL1_MEASURE_MASK) >> THERM_CTRL1_MEASURE_LSB)
1166 #define THERM_CTRL1_MEASURE_SET(x)               (((x) << THERM_CTRL1_MEASURE_LSB) & THERM_CTRL1_MEASURE_MASK)
1167 #define THERM_CTRL1_INT_EN_MSB                   1
1168 #define THERM_CTRL1_INT_EN_LSB                   1
1169 #define THERM_CTRL1_INT_EN_MASK                  0x00000002
1170 #define THERM_CTRL1_INT_EN_GET(x)                (((x) & THERM_CTRL1_INT_EN_MASK) >> THERM_CTRL1_INT_EN_LSB)
1171 #define THERM_CTRL1_INT_EN_SET(x)                (((x) << THERM_CTRL1_INT_EN_LSB) & THERM_CTRL1_INT_EN_MASK)
1172 #define THERM_CTRL1_INT_STATUS_MSB               0
1173 #define THERM_CTRL1_INT_STATUS_LSB               0
1174 #define THERM_CTRL1_INT_STATUS_MASK              0x00000001
1175 #define THERM_CTRL1_INT_STATUS_GET(x)            (((x) & THERM_CTRL1_INT_STATUS_MASK) >> THERM_CTRL1_INT_STATUS_LSB)
1176 #define THERM_CTRL1_INT_STATUS_SET(x)            (((x) << THERM_CTRL1_INT_STATUS_LSB) & THERM_CTRL1_INT_STATUS_MASK)
1177 
1178 #define THERM_CTRL2_ADDRESS                      0x000002e0
1179 #define THERM_CTRL2_OFFSET                       0x000002e0
1180 #define THERM_CTRL2_ADC_OFF_MSB                  25
1181 #define THERM_CTRL2_ADC_OFF_LSB                  25
1182 #define THERM_CTRL2_ADC_OFF_MASK                 0x02000000
1183 #define THERM_CTRL2_ADC_OFF_GET(x)               (((x) & THERM_CTRL2_ADC_OFF_MASK) >> THERM_CTRL2_ADC_OFF_LSB)
1184 #define THERM_CTRL2_ADC_OFF_SET(x)               (((x) << THERM_CTRL2_ADC_OFF_LSB) & THERM_CTRL2_ADC_OFF_MASK)
1185 #define THERM_CTRL2_ADC_ON_MSB                   24
1186 #define THERM_CTRL2_ADC_ON_LSB                   24
1187 #define THERM_CTRL2_ADC_ON_MASK                  0x01000000
1188 #define THERM_CTRL2_ADC_ON_GET(x)                (((x) & THERM_CTRL2_ADC_ON_MASK) >> THERM_CTRL2_ADC_ON_LSB)
1189 #define THERM_CTRL2_ADC_ON_SET(x)                (((x) << THERM_CTRL2_ADC_ON_LSB) & THERM_CTRL2_ADC_ON_MASK)
1190 #define THERM_CTRL2_SAMPLE_MSB                   23
1191 #define THERM_CTRL2_SAMPLE_LSB                   16
1192 #define THERM_CTRL2_SAMPLE_MASK                  0x00ff0000
1193 #define THERM_CTRL2_SAMPLE_GET(x)                (((x) & THERM_CTRL2_SAMPLE_MASK) >> THERM_CTRL2_SAMPLE_LSB)
1194 #define THERM_CTRL2_SAMPLE_SET(x)                (((x) << THERM_CTRL2_SAMPLE_LSB) & THERM_CTRL2_SAMPLE_MASK)
1195 #define THERM_CTRL2_HIGH_MSB                     15
1196 #define THERM_CTRL2_HIGH_LSB                     8
1197 #define THERM_CTRL2_HIGH_MASK                    0x0000ff00
1198 #define THERM_CTRL2_HIGH_GET(x)                  (((x) & THERM_CTRL2_HIGH_MASK) >> THERM_CTRL2_HIGH_LSB)
1199 #define THERM_CTRL2_HIGH_SET(x)                  (((x) << THERM_CTRL2_HIGH_LSB) & THERM_CTRL2_HIGH_MASK)
1200 #define THERM_CTRL2_LOW_MSB                      7
1201 #define THERM_CTRL2_LOW_LSB                      0
1202 #define THERM_CTRL2_LOW_MASK                     0x000000ff
1203 #define THERM_CTRL2_LOW_GET(x)                   (((x) & THERM_CTRL2_LOW_MASK) >> THERM_CTRL2_LOW_LSB)
1204 #define THERM_CTRL2_LOW_SET(x)                   (((x) << THERM_CTRL2_LOW_LSB) & THERM_CTRL2_LOW_MASK)
1205 
1206 #define THERM_CTRL3_ADDRESS                      0x000002e4
1207 #define THERM_CTRL3_OFFSET                       0x000002e4
1208 #define THERM_CTRL3_ADC_GAIN_MSB                 16
1209 #define THERM_CTRL3_ADC_GAIN_LSB                 8
1210 #define THERM_CTRL3_ADC_GAIN_MASK                0x0001ff00
1211 #define THERM_CTRL3_ADC_GAIN_GET(x)              (((x) & THERM_CTRL3_ADC_GAIN_MASK) >> THERM_CTRL3_ADC_GAIN_LSB)
1212 #define THERM_CTRL3_ADC_GAIN_SET(x)              (((x) << THERM_CTRL3_ADC_GAIN_LSB) & THERM_CTRL3_ADC_GAIN_MASK)
1213 #define THERM_CTRL3_ADC_OFFSET_MSB               7
1214 #define THERM_CTRL3_ADC_OFFSET_LSB               0
1215 #define THERM_CTRL3_ADC_OFFSET_MASK              0x000000ff
1216 #define THERM_CTRL3_ADC_OFFSET_GET(x)            (((x) & THERM_CTRL3_ADC_OFFSET_MASK) >> THERM_CTRL3_ADC_OFFSET_LSB)
1217 #define THERM_CTRL3_ADC_OFFSET_SET(x)            (((x) << THERM_CTRL3_ADC_OFFSET_LSB) & THERM_CTRL3_ADC_OFFSET_MASK)
1218 
1219 #define LISTEN_MODE1_ADDRESS                     0x000002e8
1220 #define LISTEN_MODE1_OFFSET                      0x000002e8
1221 #define LISTEN_MODE1_TIMER_CLEAR_MSB             19
1222 #define LISTEN_MODE1_TIMER_CLEAR_LSB             19
1223 #define LISTEN_MODE1_TIMER_CLEAR_MASK            0x00080000
1224 #define LISTEN_MODE1_TIMER_CLEAR_GET(x)          (((x) & LISTEN_MODE1_TIMER_CLEAR_MASK) >> LISTEN_MODE1_TIMER_CLEAR_LSB)
1225 #define LISTEN_MODE1_TIMER_CLEAR_SET(x)          (((x) << LISTEN_MODE1_TIMER_CLEAR_LSB) & LISTEN_MODE1_TIMER_CLEAR_MASK)
1226 #define LISTEN_MODE1_TIMER_THRESH_WAKE_MSB       18
1227 #define LISTEN_MODE1_TIMER_THRESH_WAKE_LSB       3
1228 #define LISTEN_MODE1_TIMER_THRESH_WAKE_MASK      0x0007fff8
1229 #define LISTEN_MODE1_TIMER_THRESH_WAKE_GET(x)    (((x) & LISTEN_MODE1_TIMER_THRESH_WAKE_MASK) >> LISTEN_MODE1_TIMER_THRESH_WAKE_LSB)
1230 #define LISTEN_MODE1_TIMER_THRESH_WAKE_SET(x)    (((x) << LISTEN_MODE1_TIMER_THRESH_WAKE_LSB) & LISTEN_MODE1_TIMER_THRESH_WAKE_MASK)
1231 #define LISTEN_MODE1_TIMER_OVERFLOW_WAKE_MSB     2
1232 #define LISTEN_MODE1_TIMER_OVERFLOW_WAKE_LSB     2
1233 #define LISTEN_MODE1_TIMER_OVERFLOW_WAKE_MASK    0x00000004
1234 #define LISTEN_MODE1_TIMER_OVERFLOW_WAKE_GET(x)  (((x) & LISTEN_MODE1_TIMER_OVERFLOW_WAKE_MASK) >> LISTEN_MODE1_TIMER_OVERFLOW_WAKE_LSB)
1235 #define LISTEN_MODE1_TIMER_OVERFLOW_WAKE_SET(x)  (((x) << LISTEN_MODE1_TIMER_OVERFLOW_WAKE_LSB) & LISTEN_MODE1_TIMER_OVERFLOW_WAKE_MASK)
1236 #define LISTEN_MODE1_CLOCK_GATE_MSB              1
1237 #define LISTEN_MODE1_CLOCK_GATE_LSB              1
1238 #define LISTEN_MODE1_CLOCK_GATE_MASK             0x00000002
1239 #define LISTEN_MODE1_CLOCK_GATE_GET(x)           (((x) & LISTEN_MODE1_CLOCK_GATE_MASK) >> LISTEN_MODE1_CLOCK_GATE_LSB)
1240 #define LISTEN_MODE1_CLOCK_GATE_SET(x)           (((x) << LISTEN_MODE1_CLOCK_GATE_LSB) & LISTEN_MODE1_CLOCK_GATE_MASK)
1241 #define LISTEN_MODE1_ENABLE_MSB                  0
1242 #define LISTEN_MODE1_ENABLE_LSB                  0
1243 #define LISTEN_MODE1_ENABLE_MASK                 0x00000001
1244 #define LISTEN_MODE1_ENABLE_GET(x)               (((x) & LISTEN_MODE1_ENABLE_MASK) >> LISTEN_MODE1_ENABLE_LSB)
1245 #define LISTEN_MODE1_ENABLE_SET(x)               (((x) << LISTEN_MODE1_ENABLE_LSB) & LISTEN_MODE1_ENABLE_MASK)
1246 
1247 #define LISTEN_MODE2_ADDRESS                     0x000002ec
1248 #define LISTEN_MODE2_OFFSET                      0x000002ec
1249 #define LISTEN_MODE2_TIMER_TRIGGER_WAKE_MSB      15
1250 #define LISTEN_MODE2_TIMER_TRIGGER_WAKE_LSB      0
1251 #define LISTEN_MODE2_TIMER_TRIGGER_WAKE_MASK     0x0000ffff
1252 #define LISTEN_MODE2_TIMER_TRIGGER_WAKE_GET(x)   (((x) & LISTEN_MODE2_TIMER_TRIGGER_WAKE_MASK) >> LISTEN_MODE2_TIMER_TRIGGER_WAKE_LSB)
1253 #define LISTEN_MODE2_TIMER_TRIGGER_WAKE_SET(x)   (((x) << LISTEN_MODE2_TIMER_TRIGGER_WAKE_LSB) & LISTEN_MODE2_TIMER_TRIGGER_WAKE_MASK)
1254 
1255 #define AUDIO_PLL_CONFIG_ADDRESS                 0x000002f0
1256 #define AUDIO_PLL_CONFIG_OFFSET                  0x000002f0
1257 #define AUDIO_PLL_CONFIG_UPDATING_MSB            31
1258 #define AUDIO_PLL_CONFIG_UPDATING_LSB            31
1259 #define AUDIO_PLL_CONFIG_UPDATING_MASK           0x80000000
1260 #define AUDIO_PLL_CONFIG_UPDATING_GET(x)         (((x) & AUDIO_PLL_CONFIG_UPDATING_MASK) >> AUDIO_PLL_CONFIG_UPDATING_LSB)
1261 #define AUDIO_PLL_CONFIG_UPDATING_SET(x)         (((x) << AUDIO_PLL_CONFIG_UPDATING_LSB) & AUDIO_PLL_CONFIG_UPDATING_MASK)
1262 #define AUDIO_PLL_CONFIG_EXT_DIV_MSB             14
1263 #define AUDIO_PLL_CONFIG_EXT_DIV_LSB             12
1264 #define AUDIO_PLL_CONFIG_EXT_DIV_MASK            0x00007000
1265 #define AUDIO_PLL_CONFIG_EXT_DIV_GET(x)          (((x) & AUDIO_PLL_CONFIG_EXT_DIV_MASK) >> AUDIO_PLL_CONFIG_EXT_DIV_LSB)
1266 #define AUDIO_PLL_CONFIG_EXT_DIV_SET(x)          (((x) << AUDIO_PLL_CONFIG_EXT_DIV_LSB) & AUDIO_PLL_CONFIG_EXT_DIV_MASK)
1267 #define AUDIO_PLL_CONFIG_POSTPLLDIV_MSB          9
1268 #define AUDIO_PLL_CONFIG_POSTPLLDIV_LSB          7
1269 #define AUDIO_PLL_CONFIG_POSTPLLDIV_MASK         0x00000380
1270 #define AUDIO_PLL_CONFIG_POSTPLLDIV_GET(x)       (((x) & AUDIO_PLL_CONFIG_POSTPLLDIV_MASK) >> AUDIO_PLL_CONFIG_POSTPLLDIV_LSB)
1271 #define AUDIO_PLL_CONFIG_POSTPLLDIV_SET(x)       (((x) << AUDIO_PLL_CONFIG_POSTPLLDIV_LSB) & AUDIO_PLL_CONFIG_POSTPLLDIV_MASK)
1272 #define AUDIO_PLL_CONFIG_PLLPWD_MSB              5
1273 #define AUDIO_PLL_CONFIG_PLLPWD_LSB              5
1274 #define AUDIO_PLL_CONFIG_PLLPWD_MASK             0x00000020
1275 #define AUDIO_PLL_CONFIG_PLLPWD_GET(x)           (((x) & AUDIO_PLL_CONFIG_PLLPWD_MASK) >> AUDIO_PLL_CONFIG_PLLPWD_LSB)
1276 #define AUDIO_PLL_CONFIG_PLLPWD_SET(x)           (((x) << AUDIO_PLL_CONFIG_PLLPWD_LSB) & AUDIO_PLL_CONFIG_PLLPWD_MASK)
1277 #define AUDIO_PLL_CONFIG_BYPASS_MSB              4
1278 #define AUDIO_PLL_CONFIG_BYPASS_LSB              4
1279 #define AUDIO_PLL_CONFIG_BYPASS_MASK             0x00000010
1280 #define AUDIO_PLL_CONFIG_BYPASS_GET(x)           (((x) & AUDIO_PLL_CONFIG_BYPASS_MASK) >> AUDIO_PLL_CONFIG_BYPASS_LSB)
1281 #define AUDIO_PLL_CONFIG_BYPASS_SET(x)           (((x) << AUDIO_PLL_CONFIG_BYPASS_LSB) & AUDIO_PLL_CONFIG_BYPASS_MASK)
1282 #define AUDIO_PLL_CONFIG_REFDIV_MSB              3
1283 #define AUDIO_PLL_CONFIG_REFDIV_LSB              0
1284 #define AUDIO_PLL_CONFIG_REFDIV_MASK             0x0000000f
1285 #define AUDIO_PLL_CONFIG_REFDIV_GET(x)           (((x) & AUDIO_PLL_CONFIG_REFDIV_MASK) >> AUDIO_PLL_CONFIG_REFDIV_LSB)
1286 #define AUDIO_PLL_CONFIG_REFDIV_SET(x)           (((x) << AUDIO_PLL_CONFIG_REFDIV_LSB) & AUDIO_PLL_CONFIG_REFDIV_MASK)
1287 
1288 #define AUDIO_PLL_MODULATION_ADDRESS             0x000002f4
1289 #define AUDIO_PLL_MODULATION_OFFSET              0x000002f4
1290 #define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MSB    28
1291 #define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_LSB    11
1292 #define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MASK   0x1ffff800
1293 #define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_GET(x) (((x) & AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MASK) >> AUDIO_PLL_MODULATION_TGT_DIV_FRAC_LSB)
1294 #define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_SET(x) (((x) << AUDIO_PLL_MODULATION_TGT_DIV_FRAC_LSB) & AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MASK)
1295 #define AUDIO_PLL_MODULATION_TGT_DIV_INT_MSB     6
1296 #define AUDIO_PLL_MODULATION_TGT_DIV_INT_LSB     1
1297 #define AUDIO_PLL_MODULATION_TGT_DIV_INT_MASK    0x0000007e
1298 #define AUDIO_PLL_MODULATION_TGT_DIV_INT_GET(x)  (((x) & AUDIO_PLL_MODULATION_TGT_DIV_INT_MASK) >> AUDIO_PLL_MODULATION_TGT_DIV_INT_LSB)
1299 #define AUDIO_PLL_MODULATION_TGT_DIV_INT_SET(x)  (((x) << AUDIO_PLL_MODULATION_TGT_DIV_INT_LSB) & AUDIO_PLL_MODULATION_TGT_DIV_INT_MASK)
1300 #define AUDIO_PLL_MODULATION_START_MSB           0
1301 #define AUDIO_PLL_MODULATION_START_LSB           0
1302 #define AUDIO_PLL_MODULATION_START_MASK          0x00000001
1303 #define AUDIO_PLL_MODULATION_START_GET(x)        (((x) & AUDIO_PLL_MODULATION_START_MASK) >> AUDIO_PLL_MODULATION_START_LSB)
1304 #define AUDIO_PLL_MODULATION_START_SET(x)        (((x) << AUDIO_PLL_MODULATION_START_LSB) & AUDIO_PLL_MODULATION_START_MASK)
1305 
1306 #define AUDIO_PLL_MOD_STEP_ADDRESS               0x000002f8
1307 #define AUDIO_PLL_MOD_STEP_OFFSET                0x000002f8
1308 #define AUDIO_PLL_MOD_STEP_FRAC_MSB              31
1309 #define AUDIO_PLL_MOD_STEP_FRAC_LSB              14
1310 #define AUDIO_PLL_MOD_STEP_FRAC_MASK             0xffffc000
1311 #define AUDIO_PLL_MOD_STEP_FRAC_GET(x)           (((x) & AUDIO_PLL_MOD_STEP_FRAC_MASK) >> AUDIO_PLL_MOD_STEP_FRAC_LSB)
1312 #define AUDIO_PLL_MOD_STEP_FRAC_SET(x)           (((x) << AUDIO_PLL_MOD_STEP_FRAC_LSB) & AUDIO_PLL_MOD_STEP_FRAC_MASK)
1313 #define AUDIO_PLL_MOD_STEP_INT_MSB               13
1314 #define AUDIO_PLL_MOD_STEP_INT_LSB               4
1315 #define AUDIO_PLL_MOD_STEP_INT_MASK              0x00003ff0
1316 #define AUDIO_PLL_MOD_STEP_INT_GET(x)            (((x) & AUDIO_PLL_MOD_STEP_INT_MASK) >> AUDIO_PLL_MOD_STEP_INT_LSB)
1317 #define AUDIO_PLL_MOD_STEP_INT_SET(x)            (((x) << AUDIO_PLL_MOD_STEP_INT_LSB) & AUDIO_PLL_MOD_STEP_INT_MASK)
1318 #define AUDIO_PLL_MOD_STEP_UPDATE_CNT_MSB        3
1319 #define AUDIO_PLL_MOD_STEP_UPDATE_CNT_LSB        0
1320 #define AUDIO_PLL_MOD_STEP_UPDATE_CNT_MASK       0x0000000f
1321 #define AUDIO_PLL_MOD_STEP_UPDATE_CNT_GET(x)     (((x) & AUDIO_PLL_MOD_STEP_UPDATE_CNT_MASK) >> AUDIO_PLL_MOD_STEP_UPDATE_CNT_LSB)
1322 #define AUDIO_PLL_MOD_STEP_UPDATE_CNT_SET(x)     (((x) << AUDIO_PLL_MOD_STEP_UPDATE_CNT_LSB) & AUDIO_PLL_MOD_STEP_UPDATE_CNT_MASK)
1323 
1324 #define CURRENT_AUDIO_PLL_MODULATION_ADDRESS     0x000002fc
1325 #define CURRENT_AUDIO_PLL_MODULATION_OFFSET      0x000002fc
1326 #define CURRENT_AUDIO_PLL_MODULATION_FRAC_MSB    27
1327 #define CURRENT_AUDIO_PLL_MODULATION_FRAC_LSB    10
1328 #define CURRENT_AUDIO_PLL_MODULATION_FRAC_MASK   0x0ffffc00
1329 #define CURRENT_AUDIO_PLL_MODULATION_FRAC_GET(x) (((x) & CURRENT_AUDIO_PLL_MODULATION_FRAC_MASK) >> CURRENT_AUDIO_PLL_MODULATION_FRAC_LSB)
1330 #define CURRENT_AUDIO_PLL_MODULATION_FRAC_SET(x) (((x) << CURRENT_AUDIO_PLL_MODULATION_FRAC_LSB) & CURRENT_AUDIO_PLL_MODULATION_FRAC_MASK)
1331 #define CURRENT_AUDIO_PLL_MODULATION_INT_MSB     6
1332 #define CURRENT_AUDIO_PLL_MODULATION_INT_LSB     1
1333 #define CURRENT_AUDIO_PLL_MODULATION_INT_MASK    0x0000007e
1334 #define CURRENT_AUDIO_PLL_MODULATION_INT_GET(x)  (((x) & CURRENT_AUDIO_PLL_MODULATION_INT_MASK) >> CURRENT_AUDIO_PLL_MODULATION_INT_LSB)
1335 #define CURRENT_AUDIO_PLL_MODULATION_INT_SET(x)  (((x) << CURRENT_AUDIO_PLL_MODULATION_INT_LSB) & CURRENT_AUDIO_PLL_MODULATION_INT_MASK)
1336 
1337 #define ETH_PLL_CONFIG_ADDRESS                   0x00000300
1338 #define ETH_PLL_CONFIG_OFFSET                    0x00000300
1339 #define ETH_PLL_CONFIG_GE0_MASTER_MSB            30
1340 #define ETH_PLL_CONFIG_GE0_MASTER_LSB            30
1341 #define ETH_PLL_CONFIG_GE0_MASTER_MASK           0x40000000
1342 #define ETH_PLL_CONFIG_GE0_MASTER_GET(x)         (((x) & ETH_PLL_CONFIG_GE0_MASTER_MASK) >> ETH_PLL_CONFIG_GE0_MASTER_LSB)
1343 #define ETH_PLL_CONFIG_GE0_MASTER_SET(x)         (((x) << ETH_PLL_CONFIG_GE0_MASTER_LSB) & ETH_PLL_CONFIG_GE0_MASTER_MASK)
1344 #define ETH_PLL_CONFIG_GE0_MSB                   29
1345 #define ETH_PLL_CONFIG_GE0_LSB                   29
1346 #define ETH_PLL_CONFIG_GE0_MASK                  0x20000000
1347 #define ETH_PLL_CONFIG_GE0_GET(x)                (((x) & ETH_PLL_CONFIG_GE0_MASK) >> ETH_PLL_CONFIG_GE0_LSB)
1348 #define ETH_PLL_CONFIG_GE0_SET(x)                (((x) << ETH_PLL_CONFIG_GE0_LSB) & ETH_PLL_CONFIG_GE0_MASK)
1349 #define ETH_PLL_CONFIG_RANGE_MSB                 28
1350 #define ETH_PLL_CONFIG_RANGE_LSB                 28
1351 #define ETH_PLL_CONFIG_RANGE_MASK                0x10000000
1352 #define ETH_PLL_CONFIG_RANGE_GET(x)              (((x) & ETH_PLL_CONFIG_RANGE_MASK) >> ETH_PLL_CONFIG_RANGE_LSB)
1353 #define ETH_PLL_CONFIG_RANGE_SET(x)              (((x) << ETH_PLL_CONFIG_RANGE_LSB) & ETH_PLL_CONFIG_RANGE_MASK)
1354 #define ETH_PLL_CONFIG_FRAC_MSB                  27
1355 #define ETH_PLL_CONFIG_FRAC_LSB                  18
1356 #define ETH_PLL_CONFIG_FRAC_MASK                 0x0ffc0000
1357 #define ETH_PLL_CONFIG_FRAC_GET(x)               (((x) & ETH_PLL_CONFIG_FRAC_MASK) >> ETH_PLL_CONFIG_FRAC_LSB)
1358 #define ETH_PLL_CONFIG_FRAC_SET(x)               (((x) << ETH_PLL_CONFIG_FRAC_LSB) & ETH_PLL_CONFIG_FRAC_MASK)
1359 #define ETH_PLL_CONFIG_INT_MSB                   17
1360 #define ETH_PLL_CONFIG_INT_LSB                   12
1361 #define ETH_PLL_CONFIG_INT_MASK                  0x0003f000
1362 #define ETH_PLL_CONFIG_INT_GET(x)                (((x) & ETH_PLL_CONFIG_INT_MASK) >> ETH_PLL_CONFIG_INT_LSB)
1363 #define ETH_PLL_CONFIG_INT_SET(x)                (((x) << ETH_PLL_CONFIG_INT_LSB) & ETH_PLL_CONFIG_INT_MASK)
1364 #define ETH_PLL_CONFIG_OUTDIV_MSB                9
1365 #define ETH_PLL_CONFIG_OUTDIV_LSB                7
1366 #define ETH_PLL_CONFIG_OUTDIV_MASK               0x00000380
1367 #define ETH_PLL_CONFIG_OUTDIV_GET(x)             (((x) & ETH_PLL_CONFIG_OUTDIV_MASK) >> ETH_PLL_CONFIG_OUTDIV_LSB)
1368 #define ETH_PLL_CONFIG_OUTDIV_SET(x)             (((x) << ETH_PLL_CONFIG_OUTDIV_LSB) & ETH_PLL_CONFIG_OUTDIV_MASK)
1369 #define ETH_PLL_CONFIG_PLLPWD_MSB                6
1370 #define ETH_PLL_CONFIG_PLLPWD_LSB                6
1371 #define ETH_PLL_CONFIG_PLLPWD_MASK               0x00000040
1372 #define ETH_PLL_CONFIG_PLLPWD_GET(x)             (((x) & ETH_PLL_CONFIG_PLLPWD_MASK) >> ETH_PLL_CONFIG_PLLPWD_LSB)
1373 #define ETH_PLL_CONFIG_PLLPWD_SET(x)             (((x) << ETH_PLL_CONFIG_PLLPWD_LSB) & ETH_PLL_CONFIG_PLLPWD_MASK)
1374 #define ETH_PLL_CONFIG_BYPASS_MSB                5
1375 #define ETH_PLL_CONFIG_BYPASS_LSB                5
1376 #define ETH_PLL_CONFIG_BYPASS_MASK               0x00000020
1377 #define ETH_PLL_CONFIG_BYPASS_GET(x)             (((x) & ETH_PLL_CONFIG_BYPASS_MASK) >> ETH_PLL_CONFIG_BYPASS_LSB)
1378 #define ETH_PLL_CONFIG_BYPASS_SET(x)             (((x) << ETH_PLL_CONFIG_BYPASS_LSB) & ETH_PLL_CONFIG_BYPASS_MASK)
1379 #define ETH_PLL_CONFIG_REFDIV_MSB                4
1380 #define ETH_PLL_CONFIG_REFDIV_LSB                0
1381 #define ETH_PLL_CONFIG_REFDIV_MASK               0x0000001f
1382 #define ETH_PLL_CONFIG_REFDIV_GET(x)             (((x) & ETH_PLL_CONFIG_REFDIV_MASK) >> ETH_PLL_CONFIG_REFDIV_LSB)
1383 #define ETH_PLL_CONFIG_REFDIV_SET(x)             (((x) << ETH_PLL_CONFIG_REFDIV_LSB) & ETH_PLL_CONFIG_REFDIV_MASK)
1384 
1385 #define CPU_PLL_CONFIG_ADDRESS                   0x00000304
1386 #define CPU_PLL_CONFIG_OFFSET                    0x00000304
1387 #define CPU_PLL_CONFIG_RANGE_MSB                 28
1388 #define CPU_PLL_CONFIG_RANGE_LSB                 28
1389 #define CPU_PLL_CONFIG_RANGE_MASK                0x10000000
1390 #define CPU_PLL_CONFIG_RANGE_GET(x)              (((x) & CPU_PLL_CONFIG_RANGE_MASK) >> CPU_PLL_CONFIG_RANGE_LSB)
1391 #define CPU_PLL_CONFIG_RANGE_SET(x)              (((x) << CPU_PLL_CONFIG_RANGE_LSB) & CPU_PLL_CONFIG_RANGE_MASK)
1392 #define CPU_PLL_CONFIG_FRAC_MSB                  25
1393 #define CPU_PLL_CONFIG_FRAC_LSB                  20
1394 #define CPU_PLL_CONFIG_FRAC_MASK                 0x03f00000
1395 #define CPU_PLL_CONFIG_FRAC_GET(x)               (((x) & CPU_PLL_CONFIG_FRAC_MASK) >> CPU_PLL_CONFIG_FRAC_LSB)
1396 #define CPU_PLL_CONFIG_FRAC_SET(x)               (((x) << CPU_PLL_CONFIG_FRAC_LSB) & CPU_PLL_CONFIG_FRAC_MASK)
1397 #define CPU_PLL_CONFIG_INT_MSB                   17
1398 #define CPU_PLL_CONFIG_INT_LSB                   12
1399 #define CPU_PLL_CONFIG_INT_MASK                  0x0003f000
1400 #define CPU_PLL_CONFIG_INT_GET(x)                (((x) & CPU_PLL_CONFIG_INT_MASK) >> CPU_PLL_CONFIG_INT_LSB)
1401 #define CPU_PLL_CONFIG_INT_SET(x)                (((x) << CPU_PLL_CONFIG_INT_LSB) & CPU_PLL_CONFIG_INT_MASK)
1402 #define CPU_PLL_CONFIG_OUTDIV_MSB                9
1403 #define CPU_PLL_CONFIG_OUTDIV_LSB                7
1404 #define CPU_PLL_CONFIG_OUTDIV_MASK               0x00000380
1405 #define CPU_PLL_CONFIG_OUTDIV_GET(x)             (((x) & CPU_PLL_CONFIG_OUTDIV_MASK) >> CPU_PLL_CONFIG_OUTDIV_LSB)
1406 #define CPU_PLL_CONFIG_OUTDIV_SET(x)             (((x) << CPU_PLL_CONFIG_OUTDIV_LSB) & CPU_PLL_CONFIG_OUTDIV_MASK)
1407 #define CPU_PLL_CONFIG_PLLPWD_MSB                6
1408 #define CPU_PLL_CONFIG_PLLPWD_LSB                6
1409 #define CPU_PLL_CONFIG_PLLPWD_MASK               0x00000040
1410 #define CPU_PLL_CONFIG_PLLPWD_GET(x)             (((x) & CPU_PLL_CONFIG_PLLPWD_MASK) >> CPU_PLL_CONFIG_PLLPWD_LSB)
1411 #define CPU_PLL_CONFIG_PLLPWD_SET(x)             (((x) << CPU_PLL_CONFIG_PLLPWD_LSB) & CPU_PLL_CONFIG_PLLPWD_MASK)
1412 #define CPU_PLL_CONFIG_REFDIV_MSB                4
1413 #define CPU_PLL_CONFIG_REFDIV_LSB                0
1414 #define CPU_PLL_CONFIG_REFDIV_MASK               0x0000001f
1415 #define CPU_PLL_CONFIG_REFDIV_GET(x)             (((x) & CPU_PLL_CONFIG_REFDIV_MASK) >> CPU_PLL_CONFIG_REFDIV_LSB)
1416 #define CPU_PLL_CONFIG_REFDIV_SET(x)             (((x) << CPU_PLL_CONFIG_REFDIV_LSB) & CPU_PLL_CONFIG_REFDIV_MASK)
1417 
1418 #define BB_PLL_CONFIG_ADDRESS                    0x00000308
1419 #define BB_PLL_CONFIG_OFFSET                     0x00000308
1420 #define BB_PLL_CONFIG_FRAC_MSB                   17
1421 #define BB_PLL_CONFIG_FRAC_LSB                   0
1422 #define BB_PLL_CONFIG_FRAC_MASK                  0x0003ffff
1423 #define BB_PLL_CONFIG_FRAC_GET(x)                (((x) & BB_PLL_CONFIG_FRAC_MASK) >> BB_PLL_CONFIG_FRAC_LSB)
1424 #define BB_PLL_CONFIG_FRAC_SET(x)                (((x) << BB_PLL_CONFIG_FRAC_LSB) & BB_PLL_CONFIG_FRAC_MASK)
1425 
1426 #define ETH_XMII_ADDRESS                         0x0000030c
1427 #define ETH_XMII_OFFSET                          0x0000030c
1428 #define ETH_XMII_TX_INVERT_MSB                   31
1429 #define ETH_XMII_TX_INVERT_LSB                   31
1430 #define ETH_XMII_TX_INVERT_MASK                  0x80000000
1431 #define ETH_XMII_TX_INVERT_GET(x)                (((x) & ETH_XMII_TX_INVERT_MASK) >> ETH_XMII_TX_INVERT_LSB)
1432 #define ETH_XMII_TX_INVERT_SET(x)                (((x) << ETH_XMII_TX_INVERT_LSB) & ETH_XMII_TX_INVERT_MASK)
1433 #define ETH_XMII_GIGE_QUAD_MSB                   30
1434 #define ETH_XMII_GIGE_QUAD_LSB                   30
1435 #define ETH_XMII_GIGE_QUAD_MASK                  0x40000000
1436 #define ETH_XMII_GIGE_QUAD_GET(x)                (((x) & ETH_XMII_GIGE_QUAD_MASK) >> ETH_XMII_GIGE_QUAD_LSB)
1437 #define ETH_XMII_GIGE_QUAD_SET(x)                (((x) << ETH_XMII_GIGE_QUAD_LSB) & ETH_XMII_GIGE_QUAD_MASK)
1438 #define ETH_XMII_RX_DELAY_MSB                    29
1439 #define ETH_XMII_RX_DELAY_LSB                    28
1440 #define ETH_XMII_RX_DELAY_MASK                   0x30000000
1441 #define ETH_XMII_RX_DELAY_GET(x)                 (((x) & ETH_XMII_RX_DELAY_MASK) >> ETH_XMII_RX_DELAY_LSB)
1442 #define ETH_XMII_RX_DELAY_SET(x)                 (((x) << ETH_XMII_RX_DELAY_LSB) & ETH_XMII_RX_DELAY_MASK)
1443 #define ETH_XMII_TX_DELAY_MSB                    27
1444 #define ETH_XMII_TX_DELAY_LSB                    26
1445 #define ETH_XMII_TX_DELAY_MASK                   0x0c000000
1446 #define ETH_XMII_TX_DELAY_GET(x)                 (((x) & ETH_XMII_TX_DELAY_MASK) >> ETH_XMII_TX_DELAY_LSB)
1447 #define ETH_XMII_TX_DELAY_SET(x)                 (((x) << ETH_XMII_TX_DELAY_LSB) & ETH_XMII_TX_DELAY_MASK)
1448 #define ETH_XMII_GIGE_MSB                        25
1449 #define ETH_XMII_GIGE_LSB                        25
1450 #define ETH_XMII_GIGE_MASK                       0x02000000
1451 #define ETH_XMII_GIGE_GET(x)                     (((x) & ETH_XMII_GIGE_MASK) >> ETH_XMII_GIGE_LSB)
1452 #define ETH_XMII_GIGE_SET(x)                     (((x) << ETH_XMII_GIGE_LSB) & ETH_XMII_GIGE_MASK)
1453 #define ETH_XMII_OFFSET_PHASE_MSB                24
1454 #define ETH_XMII_OFFSET_PHASE_LSB                24
1455 #define ETH_XMII_OFFSET_PHASE_MASK               0x01000000
1456 #define ETH_XMII_OFFSET_PHASE_GET(x)             (((x) & ETH_XMII_OFFSET_PHASE_MASK) >> ETH_XMII_OFFSET_PHASE_LSB)
1457 #define ETH_XMII_OFFSET_PHASE_SET(x)             (((x) << ETH_XMII_OFFSET_PHASE_LSB) & ETH_XMII_OFFSET_PHASE_MASK)
1458 #define ETH_XMII_OFFSET_COUNT_MSB                23
1459 #define ETH_XMII_OFFSET_COUNT_LSB                16
1460 #define ETH_XMII_OFFSET_COUNT_MASK               0x00ff0000
1461 #define ETH_XMII_OFFSET_COUNT_GET(x)             (((x) & ETH_XMII_OFFSET_COUNT_MASK) >> ETH_XMII_OFFSET_COUNT_LSB)
1462 #define ETH_XMII_OFFSET_COUNT_SET(x)             (((x) << ETH_XMII_OFFSET_COUNT_LSB) & ETH_XMII_OFFSET_COUNT_MASK)
1463 #define ETH_XMII_PHASE1_COUNT_MSB                15
1464 #define ETH_XMII_PHASE1_COUNT_LSB                8
1465 #define ETH_XMII_PHASE1_COUNT_MASK               0x0000ff00
1466 #define ETH_XMII_PHASE1_COUNT_GET(x)             (((x) & ETH_XMII_PHASE1_COUNT_MASK) >> ETH_XMII_PHASE1_COUNT_LSB)
1467 #define ETH_XMII_PHASE1_COUNT_SET(x)             (((x) << ETH_XMII_PHASE1_COUNT_LSB) & ETH_XMII_PHASE1_COUNT_MASK)
1468 #define ETH_XMII_PHASE0_COUNT_MSB                7
1469 #define ETH_XMII_PHASE0_COUNT_LSB                0
1470 #define ETH_XMII_PHASE0_COUNT_MASK               0x000000ff
1471 #define ETH_XMII_PHASE0_COUNT_GET(x)             (((x) & ETH_XMII_PHASE0_COUNT_MASK) >> ETH_XMII_PHASE0_COUNT_LSB)
1472 #define ETH_XMII_PHASE0_COUNT_SET(x)             (((x) << ETH_XMII_PHASE0_COUNT_LSB) & ETH_XMII_PHASE0_COUNT_MASK)
1473 
1474 #define USB_PHY_CONFIG_ADDRESS                   0x00000310
1475 #define USB_PHY_CONFIG_OFFSET                    0x00000310
1476 #define USB_PHY_CONFIG_REFCLK_SEL_MSB            7
1477 #define USB_PHY_CONFIG_REFCLK_SEL_LSB            4
1478 #define USB_PHY_CONFIG_REFCLK_SEL_MASK           0x000000f0
1479 #define USB_PHY_CONFIG_REFCLK_SEL_GET(x)         (((x) & USB_PHY_CONFIG_REFCLK_SEL_MASK) >> USB_PHY_CONFIG_REFCLK_SEL_LSB)
1480 #define USB_PHY_CONFIG_REFCLK_SEL_SET(x)         (((x) << USB_PHY_CONFIG_REFCLK_SEL_LSB) & USB_PHY_CONFIG_REFCLK_SEL_MASK)
1481 #define USB_PHY_CONFIG_REFDIV_MSB                3
1482 #define USB_PHY_CONFIG_REFDIV_LSB                3
1483 #define USB_PHY_CONFIG_REFDIV_MASK               0x00000008
1484 #define USB_PHY_CONFIG_REFDIV_GET(x)             (((x) & USB_PHY_CONFIG_REFDIV_MASK) >> USB_PHY_CONFIG_REFDIV_LSB)
1485 #define USB_PHY_CONFIG_REFDIV_SET(x)             (((x) << USB_PHY_CONFIG_REFDIV_LSB) & USB_PHY_CONFIG_REFDIV_MASK)
1486 #define USB_PHY_CONFIG_TESTMODE_MSB              2
1487 #define USB_PHY_CONFIG_TESTMODE_LSB              2
1488 #define USB_PHY_CONFIG_TESTMODE_MASK             0x00000004
1489 #define USB_PHY_CONFIG_TESTMODE_GET(x)           (((x) & USB_PHY_CONFIG_TESTMODE_MASK) >> USB_PHY_CONFIG_TESTMODE_LSB)
1490 #define USB_PHY_CONFIG_TESTMODE_SET(x)           (((x) << USB_PHY_CONFIG_TESTMODE_LSB) & USB_PHY_CONFIG_TESTMODE_MASK)
1491 #define USB_PHY_CONFIG_PLL_PWD_MSB               1
1492 #define USB_PHY_CONFIG_PLL_PWD_LSB               1
1493 #define USB_PHY_CONFIG_PLL_PWD_MASK              0x00000002
1494 #define USB_PHY_CONFIG_PLL_PWD_GET(x)            (((x) & USB_PHY_CONFIG_PLL_PWD_MASK) >> USB_PHY_CONFIG_PLL_PWD_LSB)
1495 #define USB_PHY_CONFIG_PLL_PWD_SET(x)            (((x) << USB_PHY_CONFIG_PLL_PWD_LSB) & USB_PHY_CONFIG_PLL_PWD_MASK)
1496 #define USB_PHY_CONFIG_HOSTMODE_MSB              0
1497 #define USB_PHY_CONFIG_HOSTMODE_LSB              0
1498 #define USB_PHY_CONFIG_HOSTMODE_MASK             0x00000001
1499 #define USB_PHY_CONFIG_HOSTMODE_GET(x)           (((x) & USB_PHY_CONFIG_HOSTMODE_MASK) >> USB_PHY_CONFIG_HOSTMODE_LSB)
1500 #define USB_PHY_CONFIG_HOSTMODE_SET(x)           (((x) << USB_PHY_CONFIG_HOSTMODE_LSB) & USB_PHY_CONFIG_HOSTMODE_MASK)
1501 
1502 #define USBCORE_CLK60M_ADDRESS                   0x00000314
1503 #define USBCORE_CLK60M_OFFSET                    0x00000314
1504 #define USBCORE_CLK60M_SEL_MSB                   0
1505 #define USBCORE_CLK60M_SEL_LSB                   0
1506 #define USBCORE_CLK60M_SEL_MASK                  0x00000001
1507 #define USBCORE_CLK60M_SEL_GET(x)                (((x) & USBCORE_CLK60M_SEL_MASK) >> USBCORE_CLK60M_SEL_LSB)
1508 #define USBCORE_CLK60M_SEL_SET(x)                (((x) << USBCORE_CLK60M_SEL_LSB) & USBCORE_CLK60M_SEL_MASK)
1509 
1510 #define USBPHY_UTMI_CLK_ADDRESS                  0x00000318
1511 #define USBPHY_UTMI_CLK_OFFSET                   0x00000318
1512 #define USBPHY_UTMI_CLK_EN_MSB                   0
1513 #define USBPHY_UTMI_CLK_EN_LSB                   0
1514 #define USBPHY_UTMI_CLK_EN_MASK                  0x00000001
1515 #define USBPHY_UTMI_CLK_EN_GET(x)                (((x) & USBPHY_UTMI_CLK_EN_MASK) >> USBPHY_UTMI_CLK_EN_LSB)
1516 #define USBPHY_UTMI_CLK_EN_SET(x)                (((x) << USBPHY_UTMI_CLK_EN_LSB) & USBPHY_UTMI_CLK_EN_MASK)
1517 
1518 #define USB_TXVALID_DLY_CONFIG_ADDRESS           0x0000031c
1519 #define USB_TXVALID_DLY_CONFIG_OFFSET            0x0000031c
1520 #define USB_TXVALID_DLY_CONFIG_UTMI16_MSB        7
1521 #define USB_TXVALID_DLY_CONFIG_UTMI16_LSB        4
1522 #define USB_TXVALID_DLY_CONFIG_UTMI16_MASK       0x000000f0
1523 #define USB_TXVALID_DLY_CONFIG_UTMI16_GET(x)     (((x) & USB_TXVALID_DLY_CONFIG_UTMI16_MASK) >> USB_TXVALID_DLY_CONFIG_UTMI16_LSB)
1524 #define USB_TXVALID_DLY_CONFIG_UTMI16_SET(x)     (((x) << USB_TXVALID_DLY_CONFIG_UTMI16_LSB) & USB_TXVALID_DLY_CONFIG_UTMI16_MASK)
1525 #define USB_TXVALID_DLY_CONFIG_UTMI8_MSB         3
1526 #define USB_TXVALID_DLY_CONFIG_UTMI8_LSB         0
1527 #define USB_TXVALID_DLY_CONFIG_UTMI8_MASK        0x0000000f
1528 #define USB_TXVALID_DLY_CONFIG_UTMI8_GET(x)      (((x) & USB_TXVALID_DLY_CONFIG_UTMI8_MASK) >> USB_TXVALID_DLY_CONFIG_UTMI8_LSB)
1529 #define USB_TXVALID_DLY_CONFIG_UTMI8_SET(x)      (((x) << USB_TXVALID_DLY_CONFIG_UTMI8_LSB) & USB_TXVALID_DLY_CONFIG_UTMI8_MASK)
1530 
1531 #define SECOND_HOST_INFT_ADDRESS                 0x00000320
1532 #define SECOND_HOST_INFT_OFFSET                  0x00000320
1533 #define SECOND_HOST_INFT_SDIO_MODE_MSB           0
1534 #define SECOND_HOST_INFT_SDIO_MODE_LSB           0
1535 #define SECOND_HOST_INFT_SDIO_MODE_MASK          0x00000001
1536 #define SECOND_HOST_INFT_SDIO_MODE_GET(x)        (((x) & SECOND_HOST_INFT_SDIO_MODE_MASK) >> SECOND_HOST_INFT_SDIO_MODE_LSB)
1537 #define SECOND_HOST_INFT_SDIO_MODE_SET(x)        (((x) << SECOND_HOST_INFT_SDIO_MODE_LSB) & SECOND_HOST_INFT_SDIO_MODE_MASK)
1538 
1539 #define SDIO_HOST_ADDRESS                        0x00000324
1540 #define SDIO_HOST_OFFSET                         0x00000324
1541 #define SDIO_HOST_RESET_MSB                      0
1542 #define SDIO_HOST_RESET_LSB                      0
1543 #define SDIO_HOST_RESET_MASK                     0x00000001
1544 #define SDIO_HOST_RESET_GET(x)                   (((x) & SDIO_HOST_RESET_MASK) >> SDIO_HOST_RESET_LSB)
1545 #define SDIO_HOST_RESET_SET(x)                   (((x) << SDIO_HOST_RESET_LSB) & SDIO_HOST_RESET_MASK)
1546 
1547 #define ENTERPRISE_CONFIG_ADDRESS                0x00000328
1548 #define ENTERPRISE_CONFIG_OFFSET                 0x00000328
1549 #define ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_MSB 12
1550 #define ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_LSB 12
1551 #define ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_MASK 0x00001000
1552 #define ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_GET(x) (((x) & ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_MASK) >> ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_LSB)
1553 #define ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_SET(x) (((x) << ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_LSB) & ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_MASK)
1554 #define ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_MSB    11
1555 #define ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_LSB    11
1556 #define ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_MASK   0x00000800
1557 #define ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_GET(x) (((x) & ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_MASK) >> ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_LSB)
1558 #define ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_SET(x) (((x) << ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_LSB) & ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_MASK)
1559 #define ENTERPRISE_CONFIG_STBC_DISABLE_MSB       10
1560 #define ENTERPRISE_CONFIG_STBC_DISABLE_LSB       10
1561 #define ENTERPRISE_CONFIG_STBC_DISABLE_MASK      0x00000400
1562 #define ENTERPRISE_CONFIG_STBC_DISABLE_GET(x)    (((x) & ENTERPRISE_CONFIG_STBC_DISABLE_MASK) >> ENTERPRISE_CONFIG_STBC_DISABLE_LSB)
1563 #define ENTERPRISE_CONFIG_STBC_DISABLE_SET(x)    (((x) << ENTERPRISE_CONFIG_STBC_DISABLE_LSB) & ENTERPRISE_CONFIG_STBC_DISABLE_MASK)
1564 #define ENTERPRISE_CONFIG_LDPC_DISABLE_MSB       9
1565 #define ENTERPRISE_CONFIG_LDPC_DISABLE_LSB       9
1566 #define ENTERPRISE_CONFIG_LDPC_DISABLE_MASK      0x00000200
1567 #define ENTERPRISE_CONFIG_LDPC_DISABLE_GET(x)    (((x) & ENTERPRISE_CONFIG_LDPC_DISABLE_MASK) >> ENTERPRISE_CONFIG_LDPC_DISABLE_LSB)
1568 #define ENTERPRISE_CONFIG_LDPC_DISABLE_SET(x)    (((x) << ENTERPRISE_CONFIG_LDPC_DISABLE_LSB) & ENTERPRISE_CONFIG_LDPC_DISABLE_MASK)
1569 #define ENTERPRISE_CONFIG_GREEN_TX_DISABLE_MSB   8
1570 #define ENTERPRISE_CONFIG_GREEN_TX_DISABLE_LSB   8
1571 #define ENTERPRISE_CONFIG_GREEN_TX_DISABLE_MASK  0x00000100
1572 #define ENTERPRISE_CONFIG_GREEN_TX_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_GREEN_TX_DISABLE_MASK) >> ENTERPRISE_CONFIG_GREEN_TX_DISABLE_LSB)
1573 #define ENTERPRISE_CONFIG_GREEN_TX_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_GREEN_TX_DISABLE_LSB) & ENTERPRISE_CONFIG_GREEN_TX_DISABLE_MASK)
1574 #define ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_MSB  7
1575 #define ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_LSB  7
1576 #define ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_MASK 0x00000080
1577 #define ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_MASK) >> ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_LSB)
1578 #define ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_LSB) & ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_MASK)
1579 #define ENTERPRISE_CONFIG_CHAIN1_DISABLE_MSB     6
1580 #define ENTERPRISE_CONFIG_CHAIN1_DISABLE_LSB     6
1581 #define ENTERPRISE_CONFIG_CHAIN1_DISABLE_MASK    0x00000040
1582 #define ENTERPRISE_CONFIG_CHAIN1_DISABLE_GET(x)  (((x) & ENTERPRISE_CONFIG_CHAIN1_DISABLE_MASK) >> ENTERPRISE_CONFIG_CHAIN1_DISABLE_LSB)
1583 #define ENTERPRISE_CONFIG_CHAIN1_DISABLE_SET(x)  (((x) << ENTERPRISE_CONFIG_CHAIN1_DISABLE_LSB) & ENTERPRISE_CONFIG_CHAIN1_DISABLE_MASK)
1584 #define ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_MSB    5
1585 #define ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_LSB    5
1586 #define ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_MASK   0x00000020
1587 #define ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_MASK) >> ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_LSB)
1588 #define ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_LSB) & ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_MASK)
1589 #define ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_MSB   4
1590 #define ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_LSB   4
1591 #define ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_MASK  0x00000010
1592 #define ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_MASK) >> ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_LSB)
1593 #define ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_LSB) & ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_MASK)
1594 #define ENTERPRISE_CONFIG_TXBF_DISABLE_MSB       3
1595 #define ENTERPRISE_CONFIG_TXBF_DISABLE_LSB       3
1596 #define ENTERPRISE_CONFIG_TXBF_DISABLE_MASK      0x00000008
1597 #define ENTERPRISE_CONFIG_TXBF_DISABLE_GET(x)    (((x) & ENTERPRISE_CONFIG_TXBF_DISABLE_MASK) >> ENTERPRISE_CONFIG_TXBF_DISABLE_LSB)
1598 #define ENTERPRISE_CONFIG_TXBF_DISABLE_SET(x)    (((x) << ENTERPRISE_CONFIG_TXBF_DISABLE_LSB) & ENTERPRISE_CONFIG_TXBF_DISABLE_MASK)
1599 #define ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_MSB 2
1600 #define ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_LSB 2
1601 #define ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_MASK 0x00000004
1602 #define ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_MASK) >> ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_LSB)
1603 #define ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_LSB) & ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_MASK)
1604 #define ENTERPRISE_CONFIG_LOOPBACK_DISABLE_MSB   1
1605 #define ENTERPRISE_CONFIG_LOOPBACK_DISABLE_LSB   1
1606 #define ENTERPRISE_CONFIG_LOOPBACK_DISABLE_MASK  0x00000002
1607 #define ENTERPRISE_CONFIG_LOOPBACK_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_LOOPBACK_DISABLE_MASK) >> ENTERPRISE_CONFIG_LOOPBACK_DISABLE_LSB)
1608 #define ENTERPRISE_CONFIG_LOOPBACK_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_LOOPBACK_DISABLE_LSB) & ENTERPRISE_CONFIG_LOOPBACK_DISABLE_MASK)
1609 #define ENTERPRISE_CONFIG_LOCATION_DISABLE_MSB   0
1610 #define ENTERPRISE_CONFIG_LOCATION_DISABLE_LSB   0
1611 #define ENTERPRISE_CONFIG_LOCATION_DISABLE_MASK  0x00000001
1612 #define ENTERPRISE_CONFIG_LOCATION_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_LOCATION_DISABLE_MASK) >> ENTERPRISE_CONFIG_LOCATION_DISABLE_LSB)
1613 #define ENTERPRISE_CONFIG_LOCATION_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_LOCATION_DISABLE_LSB) & ENTERPRISE_CONFIG_LOCATION_DISABLE_MASK)
1614 
1615 #define RTC_DEBUG_BUS_ADDRESS                    0x0000032c
1616 #define RTC_DEBUG_BUS_OFFSET                     0x0000032c
1617 #define RTC_DEBUG_BUS_SEL_MSB                    0
1618 #define RTC_DEBUG_BUS_SEL_LSB                    0
1619 #define RTC_DEBUG_BUS_SEL_MASK                   0x00000001
1620 #define RTC_DEBUG_BUS_SEL_GET(x)                 (((x) & RTC_DEBUG_BUS_SEL_MASK) >> RTC_DEBUG_BUS_SEL_LSB)
1621 #define RTC_DEBUG_BUS_SEL_SET(x)                 (((x) << RTC_DEBUG_BUS_SEL_LSB) & RTC_DEBUG_BUS_SEL_MASK)
1622 
1623 #define RTC_EXT_CLK_BUF_ADDRESS                  0x00000330
1624 #define RTC_EXT_CLK_BUF_OFFSET                   0x00000330
1625 #define RTC_EXT_CLK_BUF_EN_MSB                   0
1626 #define RTC_EXT_CLK_BUF_EN_LSB                   0
1627 #define RTC_EXT_CLK_BUF_EN_MASK                  0x00000001
1628 #define RTC_EXT_CLK_BUF_EN_GET(x)                (((x) & RTC_EXT_CLK_BUF_EN_MASK) >> RTC_EXT_CLK_BUF_EN_LSB)
1629 #define RTC_EXT_CLK_BUF_EN_SET(x)                (((x) << RTC_EXT_CLK_BUF_EN_LSB) & RTC_EXT_CLK_BUF_EN_MASK)
1630 
1631 #define WLAN_AHB_BRIDGE_TIMEOUT_ADDRESS          0x00000334
1632 #define WLAN_AHB_BRIDGE_TIMEOUT_OFFSET           0x00000334
1633 #define WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_MSB       13
1634 #define WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_LSB       0
1635 #define WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_MASK      0x00003fff
1636 #define WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_GET(x)    (((x) & WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_MASK) >> WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_LSB)
1637 #define WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_SET(x)    (((x) << WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_LSB) & WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_MASK)
1638 
1639 #define WLAN_AHB_CONFIG_ADDRESS                  0x00000338
1640 #define WLAN_AHB_CONFIG_OFFSET                   0x00000338
1641 #define WLAN_AHB_CONFIG_MAX_BURST_16_MSB         2
1642 #define WLAN_AHB_CONFIG_MAX_BURST_16_LSB         2
1643 #define WLAN_AHB_CONFIG_MAX_BURST_16_MASK        0x00000004
1644 #define WLAN_AHB_CONFIG_MAX_BURST_16_GET(x)      (((x) & WLAN_AHB_CONFIG_MAX_BURST_16_MASK) >> WLAN_AHB_CONFIG_MAX_BURST_16_LSB)
1645 #define WLAN_AHB_CONFIG_MAX_BURST_16_SET(x)      (((x) << WLAN_AHB_CONFIG_MAX_BURST_16_LSB) & WLAN_AHB_CONFIG_MAX_BURST_16_MASK)
1646 #define WLAN_AHB_CONFIG_MAX_BURST_8_MSB          1
1647 #define WLAN_AHB_CONFIG_MAX_BURST_8_LSB          1
1648 #define WLAN_AHB_CONFIG_MAX_BURST_8_MASK         0x00000002
1649 #define WLAN_AHB_CONFIG_MAX_BURST_8_GET(x)       (((x) & WLAN_AHB_CONFIG_MAX_BURST_8_MASK) >> WLAN_AHB_CONFIG_MAX_BURST_8_LSB)
1650 #define WLAN_AHB_CONFIG_MAX_BURST_8_SET(x)       (((x) << WLAN_AHB_CONFIG_MAX_BURST_8_LSB) & WLAN_AHB_CONFIG_MAX_BURST_8_MASK)
1651 #define WLAN_AHB_CONFIG_MAX_BURST_4_MSB          0
1652 #define WLAN_AHB_CONFIG_MAX_BURST_4_LSB          0
1653 #define WLAN_AHB_CONFIG_MAX_BURST_4_MASK         0x00000001
1654 #define WLAN_AHB_CONFIG_MAX_BURST_4_GET(x)       (((x) & WLAN_AHB_CONFIG_MAX_BURST_4_MASK) >> WLAN_AHB_CONFIG_MAX_BURST_4_LSB)
1655 #define WLAN_AHB_CONFIG_MAX_BURST_4_SET(x)       (((x) << WLAN_AHB_CONFIG_MAX_BURST_4_LSB) & WLAN_AHB_CONFIG_MAX_BURST_4_MASK)
1656 
1657 #define RTC_AXI_AHB_BRIDGE_ADDRESS               0x0000033c
1658 #define RTC_AXI_AHB_BRIDGE_OFFSET                0x0000033c
1659 #define RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_MSB 3
1660 #define RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_LSB 3
1661 #define RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_MASK 0x00000008
1662 #define RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_GET(x) (((x) & RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_MASK) >> RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_LSB)
1663 #define RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_SET(x) (((x) << RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_LSB) & RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_MASK)
1664 #define RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_MSB 2
1665 #define RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_LSB 2
1666 #define RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_MASK 0x00000004
1667 #define RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_GET(x) (((x) & RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_MASK) >> RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_LSB)
1668 #define RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_SET(x) (((x) << RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_LSB) & RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_MASK)
1669 #define RTC_AXI_AHB_BRIDGE_MAX_BEATS_MSB         1
1670 #define RTC_AXI_AHB_BRIDGE_MAX_BEATS_LSB         0
1671 #define RTC_AXI_AHB_BRIDGE_MAX_BEATS_MASK        0x00000003
1672 #define RTC_AXI_AHB_BRIDGE_MAX_BEATS_GET(x)      (((x) & RTC_AXI_AHB_BRIDGE_MAX_BEATS_MASK) >> RTC_AXI_AHB_BRIDGE_MAX_BEATS_LSB)
1673 #define RTC_AXI_AHB_BRIDGE_MAX_BEATS_SET(x)      (((x) << RTC_AXI_AHB_BRIDGE_MAX_BEATS_LSB) & RTC_AXI_AHB_BRIDGE_MAX_BEATS_MASK)
1674 
1675 #define WLAN2BT_CPUCOM_INT_STS_ADDRESS           0x00000400
1676 #define WLAN2BT_CPUCOM_INT_STS_OFFSET            0x00000400
1677 #define WLAN2BT_CPUCOM_INT_STS_REG_MSB           31
1678 #define WLAN2BT_CPUCOM_INT_STS_REG_LSB           0
1679 #define WLAN2BT_CPUCOM_INT_STS_REG_MASK          0xffffffff
1680 #define WLAN2BT_CPUCOM_INT_STS_REG_GET(x)        (((x) & WLAN2BT_CPUCOM_INT_STS_REG_MASK) >> WLAN2BT_CPUCOM_INT_STS_REG_LSB)
1681 #define WLAN2BT_CPUCOM_INT_STS_REG_SET(x)        (((x) << WLAN2BT_CPUCOM_INT_STS_REG_LSB) & WLAN2BT_CPUCOM_INT_STS_REG_MASK)
1682 
1683 #define WLAN2BT_CPUCOM_INT_MASK_N_ADDRESS        0x00000404
1684 #define WLAN2BT_CPUCOM_INT_MASK_N_OFFSET         0x00000404
1685 #define WLAN2BT_CPUCOM_INT_MASK_N_REG_MSB        31
1686 #define WLAN2BT_CPUCOM_INT_MASK_N_REG_LSB        0
1687 #define WLAN2BT_CPUCOM_INT_MASK_N_REG_MASK       0xffffffff
1688 #define WLAN2BT_CPUCOM_INT_MASK_N_REG_GET(x)     (((x) & WLAN2BT_CPUCOM_INT_MASK_N_REG_MASK) >> WLAN2BT_CPUCOM_INT_MASK_N_REG_LSB)
1689 #define WLAN2BT_CPUCOM_INT_MASK_N_REG_SET(x)     (((x) << WLAN2BT_CPUCOM_INT_MASK_N_REG_LSB) & WLAN2BT_CPUCOM_INT_MASK_N_REG_MASK)
1690 
1691 #define WLAN2BT_CPUCOM_INT_EOI_ADDRESS           0x00000408
1692 #define WLAN2BT_CPUCOM_INT_EOI_OFFSET            0x00000408
1693 #define WLAN2BT_CPUCOM_INT_EOI_REG_MSB           31
1694 #define WLAN2BT_CPUCOM_INT_EOI_REG_LSB           0
1695 #define WLAN2BT_CPUCOM_INT_EOI_REG_MASK          0xffffffff
1696 #define WLAN2BT_CPUCOM_INT_EOI_REG_GET(x)        (((x) & WLAN2BT_CPUCOM_INT_EOI_REG_MASK) >> WLAN2BT_CPUCOM_INT_EOI_REG_LSB)
1697 #define WLAN2BT_CPUCOM_INT_EOI_REG_SET(x)        (((x) << WLAN2BT_CPUCOM_INT_EOI_REG_LSB) & WLAN2BT_CPUCOM_INT_EOI_REG_MASK)
1698 
1699 #define WLAN2BT_CPUCOM_INT_ACK_STS_ADDRESS       0x0000040c
1700 #define WLAN2BT_CPUCOM_INT_ACK_STS_OFFSET        0x0000040c
1701 #define WLAN2BT_CPUCOM_INT_ACK_STS_REG_MSB       31
1702 #define WLAN2BT_CPUCOM_INT_ACK_STS_REG_LSB       0
1703 #define WLAN2BT_CPUCOM_INT_ACK_STS_REG_MASK      0xffffffff
1704 #define WLAN2BT_CPUCOM_INT_ACK_STS_REG_GET(x)    (((x) & WLAN2BT_CPUCOM_INT_ACK_STS_REG_MASK) >> WLAN2BT_CPUCOM_INT_ACK_STS_REG_LSB)
1705 #define WLAN2BT_CPUCOM_INT_ACK_STS_REG_SET(x)    (((x) << WLAN2BT_CPUCOM_INT_ACK_STS_REG_LSB) & WLAN2BT_CPUCOM_INT_ACK_STS_REG_MASK)
1706 
1707 #define WLAN2BT_CPUCOM_INT_ACK_MASK_N_ADDRESS    0x00000410
1708 #define WLAN2BT_CPUCOM_INT_ACK_MASK_N_OFFSET     0x00000410
1709 #define WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_MSB    31
1710 #define WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_LSB    0
1711 #define WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_MASK   0xffffffff
1712 #define WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_GET(x) (((x) & WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_MASK) >> WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_LSB)
1713 #define WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_SET(x) (((x) << WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_LSB) & WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_MASK)
1714 
1715 #define WLAN_CPUCOM_CRD_CNT0_ADDRESS             0x00000414
1716 #define WLAN_CPUCOM_CRD_CNT0_OFFSET              0x00000414
1717 #define WLAN_CPUCOM_CRD_CNT0_REG_MSB             15
1718 #define WLAN_CPUCOM_CRD_CNT0_REG_LSB             0
1719 #define WLAN_CPUCOM_CRD_CNT0_REG_MASK            0x0000ffff
1720 #define WLAN_CPUCOM_CRD_CNT0_REG_GET(x)          (((x) & WLAN_CPUCOM_CRD_CNT0_REG_MASK) >> WLAN_CPUCOM_CRD_CNT0_REG_LSB)
1721 #define WLAN_CPUCOM_CRD_CNT0_REG_SET(x)          (((x) << WLAN_CPUCOM_CRD_CNT0_REG_LSB) & WLAN_CPUCOM_CRD_CNT0_REG_MASK)
1722 
1723 #define WLAN_CPUCOM_CRD_INC0_ADDRESS             0x00000418
1724 #define WLAN_CPUCOM_CRD_INC0_OFFSET              0x00000418
1725 #define WLAN_CPUCOM_CRD_INC0_REG_MSB             15
1726 #define WLAN_CPUCOM_CRD_INC0_REG_LSB             0
1727 #define WLAN_CPUCOM_CRD_INC0_REG_MASK            0x0000ffff
1728 #define WLAN_CPUCOM_CRD_INC0_REG_GET(x)          (((x) & WLAN_CPUCOM_CRD_INC0_REG_MASK) >> WLAN_CPUCOM_CRD_INC0_REG_LSB)
1729 #define WLAN_CPUCOM_CRD_INC0_REG_SET(x)          (((x) << WLAN_CPUCOM_CRD_INC0_REG_LSB) & WLAN_CPUCOM_CRD_INC0_REG_MASK)
1730 
1731 #define WLAN_CPUCOM_CRD_DEC0_ADDRESS             0x0000041c
1732 #define WLAN_CPUCOM_CRD_DEC0_OFFSET              0x0000041c
1733 #define WLAN_CPUCOM_CRD_DEC0_REG_MSB             15
1734 #define WLAN_CPUCOM_CRD_DEC0_REG_LSB             0
1735 #define WLAN_CPUCOM_CRD_DEC0_REG_MASK            0x0000ffff
1736 #define WLAN_CPUCOM_CRD_DEC0_REG_GET(x)          (((x) & WLAN_CPUCOM_CRD_DEC0_REG_MASK) >> WLAN_CPUCOM_CRD_DEC0_REG_LSB)
1737 #define WLAN_CPUCOM_CRD_DEC0_REG_SET(x)          (((x) << WLAN_CPUCOM_CRD_DEC0_REG_LSB) & WLAN_CPUCOM_CRD_DEC0_REG_MASK)
1738 
1739 #define WLAN_CPUCOM_CRD_CNT1_ADDRESS             0x00000420
1740 #define WLAN_CPUCOM_CRD_CNT1_OFFSET              0x00000420
1741 #define WLAN_CPUCOM_CRD_CNT1_REG_MSB             15
1742 #define WLAN_CPUCOM_CRD_CNT1_REG_LSB             0
1743 #define WLAN_CPUCOM_CRD_CNT1_REG_MASK            0x0000ffff
1744 #define WLAN_CPUCOM_CRD_CNT1_REG_GET(x)          (((x) & WLAN_CPUCOM_CRD_CNT1_REG_MASK) >> WLAN_CPUCOM_CRD_CNT1_REG_LSB)
1745 #define WLAN_CPUCOM_CRD_CNT1_REG_SET(x)          (((x) << WLAN_CPUCOM_CRD_CNT1_REG_LSB) & WLAN_CPUCOM_CRD_CNT1_REG_MASK)
1746 
1747 #define WLAN_CPUCOM_CRD_INC1_ADDRESS             0x00000424
1748 #define WLAN_CPUCOM_CRD_INC1_OFFSET              0x00000424
1749 #define WLAN_CPUCOM_CRD_INC1_REG_MSB             15
1750 #define WLAN_CPUCOM_CRD_INC1_REG_LSB             0
1751 #define WLAN_CPUCOM_CRD_INC1_REG_MASK            0x0000ffff
1752 #define WLAN_CPUCOM_CRD_INC1_REG_GET(x)          (((x) & WLAN_CPUCOM_CRD_INC1_REG_MASK) >> WLAN_CPUCOM_CRD_INC1_REG_LSB)
1753 #define WLAN_CPUCOM_CRD_INC1_REG_SET(x)          (((x) << WLAN_CPUCOM_CRD_INC1_REG_LSB) & WLAN_CPUCOM_CRD_INC1_REG_MASK)
1754 
1755 #define WLAN_CPUCOM_CRD_DEC1_ADDRESS             0x00000428
1756 #define WLAN_CPUCOM_CRD_DEC1_OFFSET              0x00000428
1757 #define WLAN_CPUCOM_CRD_DEC1_REG_MSB             15
1758 #define WLAN_CPUCOM_CRD_DEC1_REG_LSB             0
1759 #define WLAN_CPUCOM_CRD_DEC1_REG_MASK            0x0000ffff
1760 #define WLAN_CPUCOM_CRD_DEC1_REG_GET(x)          (((x) & WLAN_CPUCOM_CRD_DEC1_REG_MASK) >> WLAN_CPUCOM_CRD_DEC1_REG_LSB)
1761 #define WLAN_CPUCOM_CRD_DEC1_REG_SET(x)          (((x) << WLAN_CPUCOM_CRD_DEC1_REG_LSB) & WLAN_CPUCOM_CRD_DEC1_REG_MASK)
1762 
1763 #define WLAN_CPUCOM_SCRATCH0_ADDRESS             0x0000042c
1764 #define WLAN_CPUCOM_SCRATCH0_OFFSET              0x0000042c
1765 #define WLAN_CPUCOM_SCRATCH0_REG_MSB             31
1766 #define WLAN_CPUCOM_SCRATCH0_REG_LSB             0
1767 #define WLAN_CPUCOM_SCRATCH0_REG_MASK            0xffffffff
1768 #define WLAN_CPUCOM_SCRATCH0_REG_GET(x)          (((x) & WLAN_CPUCOM_SCRATCH0_REG_MASK) >> WLAN_CPUCOM_SCRATCH0_REG_LSB)
1769 #define WLAN_CPUCOM_SCRATCH0_REG_SET(x)          (((x) << WLAN_CPUCOM_SCRATCH0_REG_LSB) & WLAN_CPUCOM_SCRATCH0_REG_MASK)
1770 
1771 #define WLAN_CPUCOM_SCRATCH1_ADDRESS             0x00000430
1772 #define WLAN_CPUCOM_SCRATCH1_OFFSET              0x00000430
1773 #define WLAN_CPUCOM_SCRATCH1_REG_MSB             31
1774 #define WLAN_CPUCOM_SCRATCH1_REG_LSB             0
1775 #define WLAN_CPUCOM_SCRATCH1_REG_MASK            0xffffffff
1776 #define WLAN_CPUCOM_SCRATCH1_REG_GET(x)          (((x) & WLAN_CPUCOM_SCRATCH1_REG_MASK) >> WLAN_CPUCOM_SCRATCH1_REG_LSB)
1777 #define WLAN_CPUCOM_SCRATCH1_REG_SET(x)          (((x) << WLAN_CPUCOM_SCRATCH1_REG_LSB) & WLAN_CPUCOM_SCRATCH1_REG_MASK)
1778 
1779 #define WLAN_CPUCOM_SCRATCH2_ADDRESS             0x00000434
1780 #define WLAN_CPUCOM_SCRATCH2_OFFSET              0x00000434
1781 #define WLAN_CPUCOM_SCRATCH2_REG_MSB             31
1782 #define WLAN_CPUCOM_SCRATCH2_REG_LSB             0
1783 #define WLAN_CPUCOM_SCRATCH2_REG_MASK            0xffffffff
1784 #define WLAN_CPUCOM_SCRATCH2_REG_GET(x)          (((x) & WLAN_CPUCOM_SCRATCH2_REG_MASK) >> WLAN_CPUCOM_SCRATCH2_REG_LSB)
1785 #define WLAN_CPUCOM_SCRATCH2_REG_SET(x)          (((x) << WLAN_CPUCOM_SCRATCH2_REG_LSB) & WLAN_CPUCOM_SCRATCH2_REG_MASK)
1786 
1787 #define WLAN_CPUCOM_SCRATCH3_ADDRESS             0x00000438
1788 #define WLAN_CPUCOM_SCRATCH3_OFFSET              0x00000438
1789 #define WLAN_CPUCOM_SCRATCH3_REG_MSB             31
1790 #define WLAN_CPUCOM_SCRATCH3_REG_LSB             0
1791 #define WLAN_CPUCOM_SCRATCH3_REG_MASK            0xffffffff
1792 #define WLAN_CPUCOM_SCRATCH3_REG_GET(x)          (((x) & WLAN_CPUCOM_SCRATCH3_REG_MASK) >> WLAN_CPUCOM_SCRATCH3_REG_LSB)
1793 #define WLAN_CPUCOM_SCRATCH3_REG_SET(x)          (((x) << WLAN_CPUCOM_SCRATCH3_REG_LSB) & WLAN_CPUCOM_SCRATCH3_REG_MASK)
1794 
1795 #define WLAN_CPUCOM_DBG_ADDRESS                  0x0000043c
1796 #define WLAN_CPUCOM_DBG_OFFSET                   0x0000043c
1797 #define WLAN_CPUCOM_DBG_RESERVE_MSB              7
1798 #define WLAN_CPUCOM_DBG_RESERVE_LSB              4
1799 #define WLAN_CPUCOM_DBG_RESERVE_MASK             0x000000f0
1800 #define WLAN_CPUCOM_DBG_RESERVE_GET(x)           (((x) & WLAN_CPUCOM_DBG_RESERVE_MASK) >> WLAN_CPUCOM_DBG_RESERVE_LSB)
1801 #define WLAN_CPUCOM_DBG_RESERVE_SET(x)           (((x) << WLAN_CPUCOM_DBG_RESERVE_LSB) & WLAN_CPUCOM_DBG_RESERVE_MASK)
1802 #define WLAN_CPUCOM_DBG_CRD1_DEC_ERR_MSB         3
1803 #define WLAN_CPUCOM_DBG_CRD1_DEC_ERR_LSB         3
1804 #define WLAN_CPUCOM_DBG_CRD1_DEC_ERR_MASK        0x00000008
1805 #define WLAN_CPUCOM_DBG_CRD1_DEC_ERR_GET(x)      (((x) & WLAN_CPUCOM_DBG_CRD1_DEC_ERR_MASK) >> WLAN_CPUCOM_DBG_CRD1_DEC_ERR_LSB)
1806 #define WLAN_CPUCOM_DBG_CRD1_DEC_ERR_SET(x)      (((x) << WLAN_CPUCOM_DBG_CRD1_DEC_ERR_LSB) & WLAN_CPUCOM_DBG_CRD1_DEC_ERR_MASK)
1807 #define WLAN_CPUCOM_DBG_CRD1_INC_ERR_MSB         2
1808 #define WLAN_CPUCOM_DBG_CRD1_INC_ERR_LSB         2
1809 #define WLAN_CPUCOM_DBG_CRD1_INC_ERR_MASK        0x00000004
1810 #define WLAN_CPUCOM_DBG_CRD1_INC_ERR_GET(x)      (((x) & WLAN_CPUCOM_DBG_CRD1_INC_ERR_MASK) >> WLAN_CPUCOM_DBG_CRD1_INC_ERR_LSB)
1811 #define WLAN_CPUCOM_DBG_CRD1_INC_ERR_SET(x)      (((x) << WLAN_CPUCOM_DBG_CRD1_INC_ERR_LSB) & WLAN_CPUCOM_DBG_CRD1_INC_ERR_MASK)
1812 #define WLAN_CPUCOM_DBG_CRD0_DEC_ERR_MSB         1
1813 #define WLAN_CPUCOM_DBG_CRD0_DEC_ERR_LSB         1
1814 #define WLAN_CPUCOM_DBG_CRD0_DEC_ERR_MASK        0x00000002
1815 #define WLAN_CPUCOM_DBG_CRD0_DEC_ERR_GET(x)      (((x) & WLAN_CPUCOM_DBG_CRD0_DEC_ERR_MASK) >> WLAN_CPUCOM_DBG_CRD0_DEC_ERR_LSB)
1816 #define WLAN_CPUCOM_DBG_CRD0_DEC_ERR_SET(x)      (((x) << WLAN_CPUCOM_DBG_CRD0_DEC_ERR_LSB) & WLAN_CPUCOM_DBG_CRD0_DEC_ERR_MASK)
1817 #define WLAN_CPUCOM_DBG_CRD0_INC_ERR_MSB         0
1818 #define WLAN_CPUCOM_DBG_CRD0_INC_ERR_LSB         0
1819 #define WLAN_CPUCOM_DBG_CRD0_INC_ERR_MASK        0x00000001
1820 #define WLAN_CPUCOM_DBG_CRD0_INC_ERR_GET(x)      (((x) & WLAN_CPUCOM_DBG_CRD0_INC_ERR_MASK) >> WLAN_CPUCOM_DBG_CRD0_INC_ERR_LSB)
1821 #define WLAN_CPUCOM_DBG_CRD0_INC_ERR_SET(x)      (((x) << WLAN_CPUCOM_DBG_CRD0_INC_ERR_LSB) & WLAN_CPUCOM_DBG_CRD0_INC_ERR_MASK)
1822 
1823 #define WLAN2BT_CPUCOM_INT_ACK_EN_ADDRESS        0x00000440
1824 #define WLAN2BT_CPUCOM_INT_ACK_EN_OFFSET         0x00000440
1825 #define WLAN2BT_CPUCOM_INT_ACK_EN_REG_MSB        0
1826 #define WLAN2BT_CPUCOM_INT_ACK_EN_REG_LSB        0
1827 #define WLAN2BT_CPUCOM_INT_ACK_EN_REG_MASK       0x00000001
1828 #define WLAN2BT_CPUCOM_INT_ACK_EN_REG_GET(x)     (((x) & WLAN2BT_CPUCOM_INT_ACK_EN_REG_MASK) >> WLAN2BT_CPUCOM_INT_ACK_EN_REG_LSB)
1829 #define WLAN2BT_CPUCOM_INT_ACK_EN_REG_SET(x)     (((x) << WLAN2BT_CPUCOM_INT_ACK_EN_REG_LSB) & WLAN2BT_CPUCOM_INT_ACK_EN_REG_MASK)
1830 
1831 #define BT2WLAN_CPUCOM_INT_EN_ADDRESS            0x00000444
1832 #define BT2WLAN_CPUCOM_INT_EN_OFFSET             0x00000444
1833 #define BT2WLAN_CPUCOM_INT_EN_REG_MSB            0
1834 #define BT2WLAN_CPUCOM_INT_EN_REG_LSB            0
1835 #define BT2WLAN_CPUCOM_INT_EN_REG_MASK           0x00000001
1836 #define BT2WLAN_CPUCOM_INT_EN_REG_GET(x)         (((x) & BT2WLAN_CPUCOM_INT_EN_REG_MASK) >> BT2WLAN_CPUCOM_INT_EN_REG_LSB)
1837 #define BT2WLAN_CPUCOM_INT_EN_REG_SET(x)         (((x) << BT2WLAN_CPUCOM_INT_EN_REG_LSB) & BT2WLAN_CPUCOM_INT_EN_REG_MASK)
1838 
1839 #ifndef __ASSEMBLER__
1840 typedef struct rtc_soc_reg_reg_s {
1841 	volatile unsigned int soc_reset_control;
1842 	volatile unsigned int soc_tcxo_detect;
1843 	volatile unsigned int soc_xtal_test;
1844 	unsigned char pad0[20]; /* pad to 0x20 */
1845 	volatile unsigned int soc_cpu_clock;
1846 	unsigned char pad1[4];  /* pad to 0x28 */
1847 	volatile unsigned int soc_clock_control;
1848 	unsigned char pad2[4];  /* pad to 0x30 */
1849 	volatile unsigned int soc_wdt_control;
1850 	volatile unsigned int soc_wdt_status;
1851 	volatile unsigned int soc_wdt;
1852 	volatile unsigned int soc_wdt_count;
1853 	volatile unsigned int soc_wdt_reset;
1854 	volatile unsigned int soc_int_status;
1855 	volatile unsigned int soc_lf_timer0;
1856 	volatile unsigned int soc_lf_timer_count0;
1857 	volatile unsigned int soc_lf_timer_control0;
1858 	volatile unsigned int soc_lf_timer_status0;
1859 	volatile unsigned int soc_lf_timer1;
1860 	volatile unsigned int soc_lf_timer_count1;
1861 	volatile unsigned int soc_lf_timer_control1;
1862 	volatile unsigned int soc_lf_timer_status1;
1863 	volatile unsigned int soc_lf_timer2;
1864 	volatile unsigned int soc_lf_timer_count2;
1865 	volatile unsigned int soc_lf_timer_control2;
1866 	volatile unsigned int soc_lf_timer_status2;
1867 	volatile unsigned int soc_lf_timer3;
1868 	volatile unsigned int soc_lf_timer_count3;
1869 	volatile unsigned int soc_lf_timer_control3;
1870 	volatile unsigned int soc_lf_timer_status3;
1871 	volatile unsigned int soc_hf_timer;
1872 	volatile unsigned int soc_hf_timer_count;
1873 	volatile unsigned int soc_hf_lf_count;
1874 	volatile unsigned int soc_hf_timer_control;
1875 	volatile unsigned int soc_hf_timer_status;
1876 	volatile unsigned int soc_rtc_control;
1877 	volatile unsigned int soc_rtc_time;
1878 	volatile unsigned int soc_rtc_date;
1879 	volatile unsigned int soc_rtc_set_time;
1880 	volatile unsigned int soc_rtc_set_date;
1881 	volatile unsigned int soc_rtc_set_alarm;
1882 	volatile unsigned int soc_rtc_config;
1883 	volatile unsigned int soc_rtc_alarm_status;
1884 	volatile unsigned int soc_uart_wakeup;
1885 	volatile unsigned int soc_reset_cause;
1886 	volatile unsigned int soc_system_sleep;
1887 	volatile unsigned int soc_sdio_wrapper;
1888 	volatile unsigned int soc_int_sleep_mask;
1889 	unsigned char pad3[4];  /* pad to 0xd4 */
1890 	volatile unsigned int soc_lpo_cal_time;
1891 	volatile unsigned int soc_lpo_init_dividend_int;
1892 	volatile unsigned int soc_lpo_init_dividend_fraction;
1893 	volatile unsigned int soc_lpo_cal;
1894 	volatile unsigned int soc_lpo_cal_test_control;
1895 	volatile unsigned int soc_lpo_cal_test_status;
1896 	volatile unsigned int legacy_soc_chip_id;
1897 	volatile unsigned int soc_chip_id;
1898 	unsigned char pad4[24]; /* pad to 0x10c */
1899 	volatile unsigned int soc_power_reg;
1900 	volatile unsigned int soc_core_clk_ctrl;
1901 	volatile unsigned int soc_gpio_wakeup_control;
1902 	unsigned char pad5[252];        /* pad to 0x214 */
1903 	volatile unsigned int sleep_retention;
1904 	unsigned char pad6[108];        /* pad to 0x284 */
1905 	volatile unsigned int lp_perf_counter;
1906 	volatile unsigned int lp_perf_light_sleep;
1907 	volatile unsigned int lp_perf_deep_sleep;
1908 	volatile unsigned int lp_perf_on;
1909 	unsigned char pad7[20]; /* pad to 0x2a8 */
1910 	volatile unsigned int chip_mode;
1911 	volatile unsigned int clk_req_fall_edge;
1912 	volatile unsigned int otp;
1913 	volatile unsigned int otp_status;
1914 	volatile unsigned int pmu;
1915 	volatile unsigned int pmu_config;
1916 	volatile unsigned int pmu_pareg;
1917 	volatile unsigned int pmu_bypass;
1918 	unsigned char pad8[20]; /* pad to 0x2dc */
1919 	volatile unsigned int therm_ctrl1;
1920 	volatile unsigned int therm_ctrl2;
1921 	volatile unsigned int therm_ctrl3;
1922 	volatile unsigned int listen_mode1;
1923 	volatile unsigned int listen_mode2;
1924 	volatile unsigned int audio_pll_config;
1925 	volatile unsigned int audio_pll_modulation;
1926 	volatile unsigned int audio_pll_mod_step;
1927 	volatile unsigned int current_audio_pll_modulation;
1928 	volatile unsigned int eth_pll_config;
1929 	volatile unsigned int cpu_pll_config;
1930 	volatile unsigned int bb_pll_config;
1931 	volatile unsigned int eth_xmii;
1932 	volatile unsigned int usb_phy_config;
1933 	volatile unsigned int usbcore_clk60m;
1934 	volatile unsigned int usbphy_utmi_clk;
1935 	volatile unsigned int usb_txvalid_dly_config;
1936 	volatile unsigned int second_host_inft;
1937 	volatile unsigned int sdio_host;
1938 	volatile unsigned int enterprise_config;
1939 	volatile unsigned int rtc_debug_bus;
1940 	volatile unsigned int rtc_ext_clk_buf;
1941 	volatile unsigned int wlan_ahb_bridge_timeout;
1942 	volatile unsigned int wlan_ahb_config;
1943 	volatile unsigned int rtc_axi_ahb_bridge;
1944 	unsigned char pad9[192];        /* pad to 0x400 */
1945 	volatile unsigned int wlan2bt_cpucom_int_sts;
1946 	volatile unsigned int wlan2bt_cpucom_int_mask_n;
1947 	volatile unsigned int wlan2bt_cpucom_int_eoi;
1948 	volatile unsigned int wlan2bt_cpucom_int_ack_sts;
1949 	volatile unsigned int wlan2bt_cpucom_int_ack_mask_n;
1950 	volatile unsigned int wlan_cpucom_crd_cnt0;
1951 	volatile unsigned int wlan_cpucom_crd_inc0[1];
1952 	volatile unsigned int wlan_cpucom_crd_dec0[1];
1953 	volatile unsigned int wlan_cpucom_crd_cnt1;
1954 	volatile unsigned int wlan_cpucom_crd_inc1[1];
1955 	volatile unsigned int wlan_cpucom_crd_dec1[1];
1956 	volatile unsigned int wlan_cpucom_scratch0;
1957 	volatile unsigned int wlan_cpucom_scratch1;
1958 	volatile unsigned int wlan_cpucom_scratch2;
1959 	volatile unsigned int wlan_cpucom_scratch3;
1960 	volatile unsigned int wlan_cpucom_dbg;
1961 	volatile unsigned int wlan2bt_cpucom_int_ack_en;
1962 	volatile unsigned int bt2wlan_cpucom_int_en;
1963 } rtc_soc_reg_reg_t;
1964 #endif /* __ASSEMBLER__ */
1965 
1966 #endif /* _RTC_SOC_REG_H_ */
1967