Searched refs:DRAM (Results 1 – 3 of 3) sorted by relevance
15 Tegra124 chips. The EMC controls the external DRAM on the board.
81 Support for error detection and correction of DRAM ECC errors on91 errors into DRAM.101 which trigger the DRAM ECC Read and Write respectively.165 E3-1200 based DRAM controllers.353 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
882 #define DRAM 1 macro