Searched refs:PLLE_AUX (Results 1 – 4 of 4) sorted by relevance
| /linux-4.19.296/drivers/clk/tegra/ |
| D | clk-tegra30.c | 92 #define PLLE_AUX 0x48c macro
898 clk_base + PLLE_AUX, 2, 1, 0, NULL); in tegra30_pll_init()
1069 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra30_periph_clk_init()
1074 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra30_periph_clk_init()
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| D | clk-tegra124.c | 72 #define PLLE_AUX 0x48c macro
473 .aux_reg = PLLE_AUX,
1037 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
1043 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
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| D | clk-tegra114.c | 104 #define PLLE_AUX 0x48c macro
574 .aux_reg = PLLE_AUX,
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| D | clk-tegra210.c | 100 #define PLLE_AUX 0x48c macro
1901 .aux_reg = PLLE_AUX,
3017 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra210_periph_clk_init()
3023 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra210_periph_clk_init()
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