Searched refs:PLL_ENABLE (Results 1 – 3 of 3) sorted by relevance
50 #define PLL_ENABLE 2 macro315 parent_name, 0, mode_reg, PLL_ENABLE, 0, lock); in clk_register_vco_pll()
327 #define PLL_ENABLE (1 << 30) macro718 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) { in tegra210_pllcx_set_defaults()771 if (val & PLL_ENABLE) { in tegra210_plla_set_defaults()824 PLL_ENABLE) { in tegra210_plld_set_defaults()877 if (val & PLL_ENABLE) { in plldss_defaults()996 if (val & PLL_ENABLE) { in tegra210_pllre_set_defaults()1116 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) { in tegra210_pllx_set_defaults()1169 if (val & PLL_ENABLE) { in tegra210_pllmb_set_defaults()1230 if (val & PLL_ENABLE) { in tegra210_pllp_set_defaults()1293 if (val & PLL_ENABLE) { in tegra210_pllu_set_defaults()[all …]
378 #define PLL_ENABLE BIT(13) macro406 reg &= ~PLL_ENABLE; in disable_anatop_clocks()