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Searched refs:cfg1 (Results 1 – 6 of 6) sorted by relevance

/linux-4.19.296/drivers/iio/adc/
Dimx7d_adc.c239 u32 cfg1 = 0; in imx7d_adc_channel_set() local
246 cfg1 |= (IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN | in imx7d_adc_channel_set()
249 cfg1 |= IMX7D_REG_ADC_CH_CFG1_CHANNEL_AVG_EN; in imx7d_adc_channel_set()
257 cfg1 |= IMX7D_REG_ADC_CH_CFG1_CHANNEL_SEL(channel); in imx7d_adc_channel_set()
274 writel(cfg1, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel); in imx7d_adc_channel_set()
/linux-4.19.296/drivers/clk/zte/
Dclk-zx296702.c56 { .rate = 700000000, .cfg0 = 0x800405d1, .cfg1 = 0x04555555 },
57 { .rate = 800000000, .cfg0 = 0x80040691, .cfg1 = 0x04aaaaaa },
58 { .rate = 900000000, .cfg0 = 0x80040791, .cfg1 = 0x04000000 },
59 { .rate = 1000000000, .cfg0 = 0x80040851, .cfg1 = 0x04555555 },
60 { .rate = 1100000000, .cfg0 = 0x80040911, .cfg1 = 0x04aaaaaa },
61 { .rate = 1200000000, .cfg0 = 0x80040a11, .cfg1 = 0x04000000 },
Dclk.h20 u32 cfg1; member
37 .cfg1 = _cfg1, \
Dclk.c61 if (hw_cfg0 == config[i].cfg0 && hw_cfg1 == config[i].cfg1) in hw_to_idx()
104 writel_relaxed(config->cfg1, zx_pll->reg_base + CFG0_CFG1_OFFSET); in zx_pll_set_rate()
/linux-4.19.296/include/linux/
Dswitchtec.h151 struct partition_info cfg1; member
/linux-4.19.296/drivers/pci/switch/
Dswitchtec.c567 set_fw_info_part(&info, &fi->cfg1); in ioctl_flash_part_info()