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Searched refs:enable_bit (Results 1 – 25 of 32) sorted by relevance

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/linux-4.19.296/drivers/clk/sirf/
Dclk-common.c43 signed char enable_bit; /* enable bit: 0 ~ 63 */ member
51 signed char enable_bit; /* enable bit: 0 ~ 63 */ member
540 .enable_bit = 0,
555 .enable_bit = 8,
570 .enable_bit = 9,
590 .enable_bit = 10,
605 .enable_bit = 11,
642 bit = clk->enable_bit % 32; in std_clk_is_enabled()
643 reg = clk->enable_bit / 32; in std_clk_is_enabled()
655 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63); in std_clk_enable()
[all …]
Dclk-atlas6.c23 .enable_bit = 59,
31 .enable_bit = 60,
39 .enable_bit = 61,
54 .enable_bit = 34,
Dclk-prima2.c23 .enable_bit = 59,
31 .enable_bit = 60,
39 .enable_bit = 61,
53 .enable_bit = 34,
/linux-4.19.296/drivers/clk/ti/
Dclkt_dflt.c154 *other_bit = clk->enable_bit; in omap2_clk_dflt_find_companion()
180 *idlest_bit = clk->enable_bit; in omap2_clk_dflt_find_idlest()
230 v &= ~(1 << clk->enable_bit); in omap2_dflt_clk_enable()
232 v |= (1 << clk->enable_bit); in omap2_dflt_clk_enable()
260 v |= (1 << clk->enable_bit); in omap2_dflt_clk_disable()
262 v &= ~(1 << clk->enable_bit); in omap2_dflt_clk_disable()
287 v ^= BIT(clk->enable_bit); in omap2_dflt_clk_is_enabled()
289 v &= BIT(clk->enable_bit); in omap2_dflt_clk_is_enabled()
Dgate.c113 clk_hw->enable_bit = bit_idx; in _register_gate()
148 gate->enable_bit = setup->bit_shift; in ti_clk_build_component_gate()
168 u8 enable_bit = 0; in _of_ti_gate_clk_setup() local
178 enable_bit = val; in _of_ti_gate_clk_setup()
195 enable_bit, clk_gate_flags, ops, hw_ops); in _of_ti_gate_clk_setup()
217 gate->enable_bit = val; in _of_ti_composite_gate_clk_setup()
Dclkt_iclk.c40 v |= (1 << clk->enable_bit); in omap2_clkt_iclk_allow_idle()
55 v &= ~(1 << clk->enable_bit); in omap2_clkt_iclk_deny_idle()
78 *idlest_bit = clk->enable_bit; in omap2430_clk_i2chs_find_idlest()
Dinterface.c51 clk_hw->enable_bit = bit_idx; in _register_interface()
76 u8 enable_bit = 0; in _of_ti_interface_clk_setup() local
83 enable_bit = val; in _of_ti_interface_clk_setup()
92 enable_bit, ops); in _of_ti_interface_clk_setup()
Dclk-3xxx.c161 *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET; in am35xx_clk_find_idlest()
184 if (clk->enable_bit & AM35XX_IPSS_ICK_MASK) in am35xx_clk_find_companion()
185 *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET; in am35xx_clk_find_companion()
187 *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET; in am35xx_clk_find_companion()
Dclkctrl.c152 if (!clk->enable_bit) in _omap4_clkctrl_clk_enable()
158 val |= clk->enable_bit; in _omap4_clkctrl_clk_enable()
182 if (!clk->enable_bit) in _omap4_clkctrl_clk_disable()
215 if (val & clk->enable_bit) in _omap4_clkctrl_clk_is_enabled()
312 clk_hw->enable_bit = data->bit; in _ti_clkctrl_setup_gate()
530 hw->enable_bit = MODULEMODE_SWCTRL; in _ti_omap4_clkctrl_setup()
532 hw->enable_bit = MODULEMODE_HWCTRL; in _ti_omap4_clkctrl_setup()
/linux-4.19.296/drivers/clk/
Dclk-max9485.c73 u8 enable_bit; member
115 clk_hw->enable_bit, in max9485_clk_prepare()
116 clk_hw->enable_bit); in max9485_clk_prepare()
123 max9485_update_bits(clk_hw->drvdata, clk_hw->enable_bit, 0); in max9485_clk_unprepare()
206 u8 enable_bit; member
213 .enable_bit = MAX9485_MCLK_ENABLE,
231 .enable_bit = MAX9485_CLKOUT1_ENABLE,
240 .enable_bit = MAX9485_CLKOUT2_ENABLE,
322 drvdata->hw[i].enable_bit = max9485_clks[i].enable_bit; in max9485_i2c_probe()
/linux-4.19.296/drivers/regulator/
Dmc13xxx.h20 int enable_bit; member
71 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
89 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
104 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
Dtps6586x-regulator.c62 int enable_bit[2]; member
131 .enable_bit[0] = (ebit0), \
133 .enable_bit[1] = (ebit1),
156 .enable_bit[0] = (ebit0), \
158 .enable_bit[1] = (ebit1),
277 ri->enable_bit[0] == ri->enable_bit[1]) in tps6586x_regulator_preinit()
288 if (!(val2 & (1 << ri->enable_bit[1]))) in tps6586x_regulator_preinit()
295 if (!(val1 & (1 << ri->enable_bit[0]))) { in tps6586x_regulator_preinit()
297 1 << ri->enable_bit[0]); in tps6586x_regulator_preinit()
303 1 << ri->enable_bit[1]); in tps6586x_regulator_preinit()
Dmc13xxx-regulator-core.c36 mc13xxx_regulators[id].enable_bit, in mc13xxx_regulator_enable()
37 mc13xxx_regulators[id].enable_bit); in mc13xxx_regulator_enable()
49 mc13xxx_regulators[id].enable_bit, 0); in mc13xxx_regulator_disable()
63 return (val & mc13xxx_regulators[id].enable_bit) != 0; in mc13xxx_regulator_is_enabled()
Dmc13783-regulator.c330 u32 en_val = mc13xxx_regulators[id].enable_bit; in mc13783_gpo_regulator_enable()
339 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit, in mc13783_gpo_regulator_enable()
355 dis_val = mc13xxx_regulators[id].enable_bit; in mc13783_gpo_regulator_disable()
357 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit, in mc13783_gpo_regulator_disable()
380 return (val & mc13xxx_regulators[id].enable_bit) != 0; in mc13783_gpo_regulator_is_enabled()
Dda903x.c86 int enable_bit; member
145 1 << info->enable_bit); in da903x_enable()
154 1 << info->enable_bit); in da903x_disable()
168 return !!(reg_val & (1 << info->enable_bit)); in da903x_is_enabled()
330 .enable_bit = (ebit), \
352 .enable_bit = (ebit), \
Dmc13892-regulator.c337 u32 en_val = mc13892_regulators[id].enable_bit; in mc13892_gpo_regulator_enable()
338 u32 mask = mc13892_regulators[id].enable_bit; in mc13892_gpo_regulator_enable()
362 dis_val = mc13892_regulators[id].enable_bit; in mc13892_gpo_regulator_disable()
364 return mc13892_powermisc_rmw(priv, mc13892_regulators[id].enable_bit, in mc13892_gpo_regulator_disable()
386 return (val & mc13892_regulators[id].enable_bit) != 0; in mc13892_gpo_regulator_is_enabled()
Danatop-regulator.c299 u32 enable_bit; in anatop_regulator_probe() local
304 &enable_bit)) { in anatop_regulator_probe()
310 rdesc->enable_mask = BIT(enable_bit); in anatop_regulator_probe()
/linux-4.19.296/drivers/clk/renesas/
Dclk-sh73a0.c94 u32 enable_bit = name[3] - '0'; in sh73a0_cpg_register_clock() local
97 switch (enable_bit) { in sh73a0_cpg_register_clock()
113 if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) { in sh73a0_cpg_register_clock()
116 if (enable_bit == 1 || enable_bit == 2) in sh73a0_cpg_register_clock()
/linux-4.19.296/include/linux/
Dsh_clk.h57 unsigned int enable_bit; member
121 .enable_bit = _enable_bit, \
155 .enable_bit = _shift, \
179 .enable_bit = 0, /* unused */ \
192 .enable_bit = 0, /* unused */ \
/linux-4.19.296/drivers/sh/clk/
Dcpg.c56 sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk); in sh_clk_mstp_enable()
71 (read(mapped_status) & (1 << clk->enable_bit)) && i; in sh_clk_mstp_enable()
76 clk->enable_reg, clk->enable_bit); in sh_clk_mstp_enable()
85 sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk); in sh_clk_mstp_disable()
138 idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; in sh_clk_div_recalc()
154 value &= ~(clk->div_mask << clk->enable_bit); in sh_clk_div_set_rate()
155 value |= (idx << clk->enable_bit); in sh_clk_div_set_rate()
/linux-4.19.296/drivers/clk/ingenic/
Djz4740-cgu.c84 .enable_bit = 8,
281 cppcr &= ~BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.enable_bit); in jz4740_clock_suspend()
290 cppcr |= BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.enable_bit); in jz4740_clock_resume()
Dcgu.h60 u8 enable_bit; member
Djz4770-cgu.c114 .enable_bit = 8,
135 .enable_bit = 7,
/linux-4.19.296/drivers/clk/spear/
Dclk-aux-synth.c41 .enable_bit = AUX_SYNT_ENB,
182 aux->masks->enable_bit, 0, lock); in clk_register_aux()
Dclk.h40 u32 enable_bit; member

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