Searched refs:HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS (Results 1 – 2 of 2) sorted by relevance
5760 #define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */ macro5865 A_UINT32 rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];5869 A_UINT32 rx_stbc[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];5877 A_UINT32 rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];5895 A_UINT32 ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];5897 A_UINT32 ul_ofdma_rx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];5953 A_UINT32 rx_11ax_su_txbf_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];5955 A_UINT32 rx_11ax_mu_txbf_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];5957 A_UINT32 rx_11ax_dl_ofdma_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];6120 A_UINT32 ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];[all …]
67 #define DP_HTT_RX_MCS_LEN HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS1294 for (i = 0; i < HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS; i++) { in dp_print_rx_peer_rate_stats_tlv()1302 " %u:%u,", i + HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS, in dp_print_rx_peer_rate_stats_tlv()1330 for (i = 0; i < HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS; i++) { in dp_print_rx_peer_rate_stats_tlv()3832 for (i = 0; i < HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS; i++) { in dp_print_rx_pdev_rate_stats_tlv()3862 for (i = 0; i < HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS; i++) { in dp_print_rx_pdev_rate_stats_tlv()3906 for (i = 0; i < HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS; i++) { in dp_print_rx_pdev_rate_stats_tlv()3920 for (i = 0; i < HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS; i++) { in dp_print_rx_pdev_rate_stats_tlv()3995 for (i = 0; i < HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS; i++) { in dp_print_rx_pdev_rate_stats_tlv()4005 for (i = 0; i < HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS; i++) { in dp_print_rx_pdev_rate_stats_tlv()