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Searched refs:reg_val (Results 1 – 25 of 43) sorted by relevance

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/wlan-driver/qca-wifi-host-cmn/hal/wifi3.0/
H A Dhal_generic_api.h184 uint32_t reg_val = 0; in hal_srng_hw_disable_generic() local
192 reg_val = SRNG_DST_REG_READ(srng, MISC) & ~(SRNG_ENABLE_BIT); in hal_srng_hw_disable_generic()
193 SRNG_DST_REG_WRITE(srng, MISC, reg_val); in hal_srng_hw_disable_generic()
195 reg_val = SRNG_SRC_REG_READ(srng, MISC) & ~(SRNG_ENABLE_BIT); in hal_srng_hw_disable_generic()
196 SRNG_SRC_REG_WRITE(srng, MISC, reg_val); in hal_srng_hw_disable_generic()
252 uint32_t reg_val = 0; in hal_srng_src_hw_init_generic() local
258 reg_val = SRNG_SRC_REG_READ(srng, MISC); in hal_srng_src_hw_init_generic()
259 if (!(reg_val & SRNG_IDLE_STATE_BIT)) { in hal_srng_src_hw_init_generic()
267 reg_val = SRNG_SRC_REG_READ(srng, MISC) & ~(SRNG_ENABLE_BIT); in hal_srng_src_hw_init_generic()
268 SRNG_SRC_REG_WRITE(srng, MISC, reg_val); in hal_srng_src_hw_init_generic()
[all …]
H A Dhal_srng.c1408 uint32_t reg_val = 0; in hal_ce_dst_setup() local
1418 reg_val = HAL_REG_READ(hal, reg_addr); in hal_ce_dst_setup()
1419 reg_val &= ~HAL_CE_CHANNEL_DST_DEST_CTRL_DEST_MAX_LENGTH_BMSK; in hal_ce_dst_setup()
1420 reg_val |= srng->u.dst_ring.max_buffer_length & in hal_ce_dst_setup()
1422 HAL_REG_WRITE(hal, reg_addr, reg_val); in hal_ce_dst_setup()
1429 reg_val = HAL_REG_READ(hal, reg_addr); in hal_ce_dst_setup()
1430 reg_val &= ~HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK; in hal_ce_dst_setup()
1431 reg_val |= srng->prefetch_timer; in hal_ce_dst_setup()
1432 HAL_REG_WRITE(hal, reg_addr, reg_val); in hal_ce_dst_setup()
1433 reg_val = HAL_REG_READ(hal, reg_addr); in hal_ce_dst_setup()
/wlan-driver/qca-wifi-host-cmn/hal/wifi3.0/qcn6432/
H A Dhal_6432_tx.h221 uint32_t reg_val = 0; in hal_tx_config_rbm_mapping_be_6432() local
243 reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) << in hal_tx_config_rbm_mapping_be_6432()
247 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); in hal_tx_config_rbm_mapping_be_6432()
519 uint32_t reg_addr, reg_val = 0; in hal_tx_set_ppe_cmn_config_6432() local
523 reg_val = HAL_REG_READ(soc, reg_addr); in hal_tx_set_ppe_cmn_config_6432()
525 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK; in hal_tx_set_ppe_cmn_config_6432()
526 reg_val |= in hal_tx_set_ppe_cmn_config_6432()
531 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK; in hal_tx_set_ppe_cmn_config_6432()
532 reg_val |= in hal_tx_set_ppe_cmn_config_6432()
537 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK; in hal_tx_set_ppe_cmn_config_6432()
[all …]
H A Dhal_6432_rx.h70 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ argument
72 reg_val &= \
75 reg_val |= \
83 reg_val); \
84 reg_val = HAL_REG_READ(soc, \
87 reg_val &= ~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \
88 reg_val |= HAL_SM(HWIO_REO_R0_MISC_CTL, \
91 reg_val |= ((HAL_REO_MSDU_END_COPY) << \
95 reg_val); \
/wlan-driver/qca-wifi-host-cmn/hal/wifi3.0/qcn9224/
H A Dhal_9224_tx.h302 uint32_t reg_val = 0; in hal_tx_config_rbm_mapping_be_9224() local
324 reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) << in hal_tx_config_rbm_mapping_be_9224()
328 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); in hal_tx_config_rbm_mapping_be_9224()
600 uint32_t reg_addr, reg_val = 0; in hal_tx_set_ppe_cmn_config_9224() local
604 reg_val = HAL_REG_READ(soc, reg_addr); in hal_tx_set_ppe_cmn_config_9224()
606 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK; in hal_tx_set_ppe_cmn_config_9224()
607 reg_val |= in hal_tx_set_ppe_cmn_config_9224()
612 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK; in hal_tx_set_ppe_cmn_config_9224()
613 reg_val |= in hal_tx_set_ppe_cmn_config_9224()
618 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK; in hal_tx_set_ppe_cmn_config_9224()
[all …]
H A Dhal_9224_rx.h77 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ argument
79 reg_val &= \
82 reg_val |= \
90 reg_val); \
91 reg_val = HAL_REG_READ(soc, \
94 reg_val &= ~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \
95 reg_val |= HAL_SM(HWIO_REO_R0_MISC_CTL, \
98 reg_val |= ((HAL_REO_MSDU_END_COPY) << \
103 reg_val); \
H A Dhal_9224.h1176 uint32_t reg_val, in hal_reo_config_9224() argument
1179 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); in hal_reo_config_9224()
1518 uint32_t reg_addr, reg_val = 0, i; in hal_tx_dump_ppe_vp_entry_9224() local
1525 reg_val = HAL_REG_READ(soc, reg_addr); in hal_tx_dump_ppe_vp_entry_9224()
1526 hal_verbose_debug("%d: 0x%x\n", i, reg_val); in hal_tx_dump_ppe_vp_entry_9224()
1599 uint32_t reg_val; in hal_reo_setup_9224() local
1602 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( in hal_reo_setup_9224()
1605 hal_reo_config_9224(soc, reg_val, reo_params); in hal_reo_setup_9224()
/wlan-driver/qcacld-3.0/core/bmi/src/
H A Dol_fw.c1067 uint32_t reg_val = 0; in ol_patch_pll_switch() local
1104 status = bmi_read_soc_register(addr, &reg_val, ol_ctx); in ol_patch_pll_switch()
1110 status = ol_fw_populate_clk_settings(EFUSE_XTAL_SEL_GET(reg_val), in ol_patch_pll_switch()
1119 reg_val = 0; in ol_patch_pll_switch()
1121 status = bmi_read_soc_register(addr, &reg_val, ol_ctx); in ol_patch_pll_switch()
1126 BMI_DBG("Step 1a: %8X", reg_val); in ol_patch_pll_switch()
1128 reg_val &= ~(BB_PLL_CONFIG_FRAC_MASK | BB_PLL_CONFIG_OUTDIV_MASK); in ol_patch_pll_switch()
1129 reg_val |= (BB_PLL_CONFIG_FRAC_SET(clock_s.wlan_pll.rnfrac) | in ol_patch_pll_switch()
1131 status = bmi_write_soc_register(addr, reg_val, ol_ctx); in ol_patch_pll_switch()
1137 reg_val = 0; in ol_patch_pll_switch()
[all …]
/wlan-driver/qca-wifi-host-cmn/hal/wifi3.0/qca5332/
H A Dhal_5332_rx.h70 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ argument
72 reg_val &= \
75 reg_val |= \
83 reg_val); \
84 reg_val = HAL_REG_READ(soc, \
87 reg_val &= ~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \
88 reg_val |= HAL_SM(HWIO_REO_R0_MISC_CTL, \
91 reg_val |= ((HAL_REO_MSDU_END_COPY) << \
95 reg_val); \
H A Dhal_5332_tx.h206 uint32_t reg_val = 0; in hal_tx_config_rbm_mapping_be_5332() local
226 reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) << in hal_tx_config_rbm_mapping_be_5332()
230 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); in hal_tx_config_rbm_mapping_be_5332()
/wlan-driver/qca-wifi-host-cmn/hal/wifi3.0/kiwi/
H A Dhal_kiwi_rx.h67 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ argument
69 reg_val &= \
72 reg_val |= \
80 (reg_val)); \
81 reg_val = \
85 reg_val &= \
87 reg_val |= \
91 reg_val &= \
97 (reg_val)); \
H A Dhal_kiwi_tx.h175 uint32_t reg_val = 0; in hal_tx_config_rbm_mapping_be_kiwi() local
197 reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) << in hal_tx_config_rbm_mapping_be_kiwi()
201 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); in hal_tx_config_rbm_mapping_be_kiwi()
H A Dhal_kiwi.c1349 uint32_t reg_val, in hal_reo_config_kiwi() argument
1352 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); in hal_reo_config_kiwi()
2052 uint32_t reg_val = 0; in hal_srng_dst_hw_init_misc_1_kiwi() local
2056 reg_val |= SRNG_SM(SRNG_DST_HW_FLD(MISC_1, in hal_srng_dst_hw_init_misc_1_kiwi()
2061 reg_val |= SRNG_SM(SRNG_DST_HW_FLD(MISC_1, in hal_srng_dst_hw_init_misc_1_kiwi()
2065 if (reg_val) in hal_srng_dst_hw_init_misc_1_kiwi()
2066 SRNG_DST_REG_WRITE(srng, MISC_1, reg_val); in hal_srng_dst_hw_init_misc_1_kiwi()
/wlan-driver/qca-wifi-host-cmn/hal/wifi3.0/be/
H A Dhal_be_generic_api.h3327 uint32_t reg_val = 0; in hal_reo_shared_qaddr_cache_clear_be() local
3332 reg_val = HAL_REG_READ(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE)); in hal_reo_shared_qaddr_cache_clear_be()
3333 reg_val |= HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1); in hal_reo_shared_qaddr_cache_clear_be()
3336 reg_val); in hal_reo_shared_qaddr_cache_clear_be()
3341 reg_val &= ~(HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1)); in hal_reo_shared_qaddr_cache_clear_be()
3344 reg_val); in hal_reo_shared_qaddr_cache_clear_be()
3348 "to erase stale entries in reo storage: regval:%x", hal, reg_val); in hal_reo_shared_qaddr_cache_clear_be()
3542 uint32_t reg_addr, reg_val = 0; in hal_tx_vdev_mismatch_routing_set_generic_be() local
3553 reg_val = val | (config << in hal_tx_vdev_mismatch_routing_set_generic_be()
3556 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); in hal_tx_vdev_mismatch_routing_set_generic_be()
[all …]
H A Dhal_be_generic_api.c58 uint32_t reg_val; in hal_setup_reo_swap() local
60 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR( in hal_setup_reo_swap()
63 reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, WRITE_STRUCT_SWAP, 1); in hal_setup_reo_swap()
64 reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, READ_STRUCT_SWAP, 1); in hal_setup_reo_swap()
67 REO_REG_REG_BASE), reg_val); in hal_setup_reo_swap()
91 uint32_t reg_val; in hal_reo_setup_generic_be() local
94 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( in hal_reo_setup_generic_be()
97 hal_reo_config(soc, reg_val, reo_params); in hal_reo_setup_generic_be()
/wlan-driver/qca-wifi-host-cmn/hal/wifi3.0/qca5018/
H A Dhal_5018_rx.h59 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ argument
61 (reg_val) &= \
64 (reg_val) |= \
72 (reg_val)); \
73 (reg_val) = \
77 (reg_val) &= \
79 (reg_val) |= \
86 (reg_val)); \
87 (reg_val) = \
91 (reg_val) &= \
[all …]
/wlan-driver/qca-wifi-host-cmn/hal/wifi3.0/qcn6122/
H A Dhal_qcn6122_rx.h65 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ argument
67 (reg_val) &= \
70 (reg_val) |= \
78 (reg_val)); \
79 (reg_val) = \
83 (reg_val) &= \
85 (reg_val) |= \
92 (reg_val)); \
93 (reg_val) = \
97 (reg_val) &= \
[all …]
/wlan-driver/qca-wifi-host-cmn/hal/wifi3.0/qca6750/
H A Dhal_6750_rx.h292 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ argument
294 reg_val &= \
297 reg_val |= \
305 (reg_val)); \
306 reg_val = \
310 reg_val &= \
312 reg_val |= \
319 (reg_val)); \
320 reg_val = \
324 reg_val &= \
[all …]
/wlan-driver/qca-wifi-host-cmn/hal/wifi3.0/qca6490/
H A Dhal_6490_rx.h286 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ argument
288 reg_val &= \
291 reg_val |= \
299 (reg_val)); \
300 reg_val = \
304 reg_val &= \
306 reg_val |= \
313 (reg_val)); \
314 reg_val = \
318 reg_val &= \
[all …]
/wlan-driver/qca-wifi-host-cmn/hal/wifi3.0/qcn9000/
H A Dhal_9000_rx.h63 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ argument
65 reg_val &= \
69 reg_val |= \
80 (reg_val)); \
81 (reg_val) = \
85 (reg_val) &= \
87 (reg_val) |= \
94 (reg_val)); \
/wlan-driver/qca-wifi-host-cmn/hal/wifi3.0/qca8074v1/
H A Dhal_8074v1_rx.h266 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ argument
268 reg_val &= \
272 reg_val |= \
283 (reg_val)); \
284 (reg_val) = \
288 (reg_val) &= \
290 (reg_val) |= \
297 (reg_val)); \
/wlan-driver/qca-wifi-host-cmn/hal/wifi3.0/qca6390/
H A Dhal_6390_rx.h283 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ argument
285 reg_val &= \
289 reg_val |= \
300 (reg_val)); \
301 reg_val = \
305 reg_val &= \
311 (reg_val)); \
/wlan-driver/qca-wifi-host-cmn/hal/wifi3.0/qca8074v2/
H A Dhal_8074v2_rx.h275 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ argument
277 reg_val &= \
281 reg_val |= \
292 (reg_val)); \
293 (reg_val) = \
297 (reg_val) &= \
299 (reg_val) |= \
306 (reg_val)); \
/wlan-driver/platform/cnss2/
H A Ddebug.c403 u32 data_len = 0, reg_val = 0; in cnss_reg_read_debug_write() local
444 ret = cnss_bus_debug_reg_read(plat_priv, reg_offset, &reg_val, in cnss_reg_read_debug_write()
449 cnss_pr_dbg("Read 0x%x from register offset 0x%x\n", reg_val, in cnss_reg_read_debug_write()
519 u32 reg_offset, mem_type, reg_val; in cnss_reg_write_debug_write() local
554 if (kstrtou32(token, 0, &reg_val)) in cnss_reg_write_debug_write()
559 ret = cnss_bus_debug_reg_write(plat_priv, reg_offset, reg_val, in cnss_reg_write_debug_write()
564 cnss_pr_dbg("Wrote 0x%x to register offset 0x%x\n", reg_val, in cnss_reg_write_debug_write()
576 (u8 *)&reg_val); in cnss_reg_write_debug_write()
/wlan-driver/qca-wifi-host-cmn/hal/wifi3.0/qca6290/
H A Dhal_6290_rx.h277 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ argument
279 (reg_val) &= \
283 (reg_val) |= \
294 (reg_val)); \

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