1 /*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
24
25 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
26 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
27
28 #include "common.h"
29 #include "clk-regmap.h"
30 #include "clk-pll.h"
31 #include "clk-rcg.h"
32 #include "clk-branch.h"
33 #include "reset.h"
34
35 static struct clk_pll pll0 = {
36 .l_reg = 0x30c4,
37 .m_reg = 0x30c8,
38 .n_reg = 0x30cc,
39 .config_reg = 0x30d4,
40 .mode_reg = 0x30c0,
41 .status_reg = 0x30d8,
42 .status_bit = 16,
43 .clkr.hw.init = &(struct clk_init_data){
44 .name = "pll0",
45 .parent_names = (const char *[]){ "pxo" },
46 .num_parents = 1,
47 .ops = &clk_pll_ops,
48 },
49 };
50
51 static struct clk_regmap pll0_vote = {
52 .enable_reg = 0x34c0,
53 .enable_mask = BIT(0),
54 .hw.init = &(struct clk_init_data){
55 .name = "pll0_vote",
56 .parent_names = (const char *[]){ "pll0" },
57 .num_parents = 1,
58 .ops = &clk_pll_vote_ops,
59 },
60 };
61
62 static struct clk_pll pll3 = {
63 .l_reg = 0x3164,
64 .m_reg = 0x3168,
65 .n_reg = 0x316c,
66 .config_reg = 0x3174,
67 .mode_reg = 0x3160,
68 .status_reg = 0x3178,
69 .status_bit = 16,
70 .clkr.hw.init = &(struct clk_init_data){
71 .name = "pll3",
72 .parent_names = (const char *[]){ "pxo" },
73 .num_parents = 1,
74 .ops = &clk_pll_ops,
75 },
76 };
77
78 static struct clk_regmap pll4_vote = {
79 .enable_reg = 0x34c0,
80 .enable_mask = BIT(4),
81 .hw.init = &(struct clk_init_data){
82 .name = "pll4_vote",
83 .parent_names = (const char *[]){ "pll4" },
84 .num_parents = 1,
85 .ops = &clk_pll_vote_ops,
86 },
87 };
88
89 static struct clk_pll pll8 = {
90 .l_reg = 0x3144,
91 .m_reg = 0x3148,
92 .n_reg = 0x314c,
93 .config_reg = 0x3154,
94 .mode_reg = 0x3140,
95 .status_reg = 0x3158,
96 .status_bit = 16,
97 .clkr.hw.init = &(struct clk_init_data){
98 .name = "pll8",
99 .parent_names = (const char *[]){ "pxo" },
100 .num_parents = 1,
101 .ops = &clk_pll_ops,
102 },
103 };
104
105 static struct clk_regmap pll8_vote = {
106 .enable_reg = 0x34c0,
107 .enable_mask = BIT(8),
108 .hw.init = &(struct clk_init_data){
109 .name = "pll8_vote",
110 .parent_names = (const char *[]){ "pll8" },
111 .num_parents = 1,
112 .ops = &clk_pll_vote_ops,
113 },
114 };
115
116 static struct clk_pll pll14 = {
117 .l_reg = 0x31c4,
118 .m_reg = 0x31c8,
119 .n_reg = 0x31cc,
120 .config_reg = 0x31d4,
121 .mode_reg = 0x31c0,
122 .status_reg = 0x31d8,
123 .status_bit = 16,
124 .clkr.hw.init = &(struct clk_init_data){
125 .name = "pll14",
126 .parent_names = (const char *[]){ "pxo" },
127 .num_parents = 1,
128 .ops = &clk_pll_ops,
129 },
130 };
131
132 static struct clk_regmap pll14_vote = {
133 .enable_reg = 0x34c0,
134 .enable_mask = BIT(14),
135 .hw.init = &(struct clk_init_data){
136 .name = "pll14_vote",
137 .parent_names = (const char *[]){ "pll14" },
138 .num_parents = 1,
139 .ops = &clk_pll_vote_ops,
140 },
141 };
142
143 #define NSS_PLL_RATE(f, _l, _m, _n, i) \
144 { \
145 .freq = f, \
146 .l = _l, \
147 .m = _m, \
148 .n = _n, \
149 .ibits = i, \
150 }
151
152 static struct pll_freq_tbl pll18_freq_tbl[] = {
153 NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
154 NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
155 };
156
157 static struct clk_pll pll18 = {
158 .l_reg = 0x31a4,
159 .m_reg = 0x31a8,
160 .n_reg = 0x31ac,
161 .config_reg = 0x31b4,
162 .mode_reg = 0x31a0,
163 .status_reg = 0x31b8,
164 .status_bit = 16,
165 .post_div_shift = 16,
166 .post_div_width = 1,
167 .freq_tbl = pll18_freq_tbl,
168 .clkr.hw.init = &(struct clk_init_data){
169 .name = "pll18",
170 .parent_names = (const char *[]){ "pxo" },
171 .num_parents = 1,
172 .ops = &clk_pll_ops,
173 },
174 };
175
176 enum {
177 P_PXO,
178 P_PLL8,
179 P_PLL3,
180 P_PLL0,
181 P_CXO,
182 P_PLL14,
183 P_PLL18,
184 };
185
186 static const struct parent_map gcc_pxo_pll8_map[] = {
187 { P_PXO, 0 },
188 { P_PLL8, 3 }
189 };
190
191 static const char * const gcc_pxo_pll8[] = {
192 "pxo",
193 "pll8_vote",
194 };
195
196 static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
197 { P_PXO, 0 },
198 { P_PLL8, 3 },
199 { P_CXO, 5 }
200 };
201
202 static const char * const gcc_pxo_pll8_cxo[] = {
203 "pxo",
204 "pll8_vote",
205 "cxo",
206 };
207
208 static const struct parent_map gcc_pxo_pll3_map[] = {
209 { P_PXO, 0 },
210 { P_PLL3, 1 }
211 };
212
213 static const struct parent_map gcc_pxo_pll3_sata_map[] = {
214 { P_PXO, 0 },
215 { P_PLL3, 6 }
216 };
217
218 static const char * const gcc_pxo_pll3[] = {
219 "pxo",
220 "pll3",
221 };
222
223 static const struct parent_map gcc_pxo_pll8_pll0[] = {
224 { P_PXO, 0 },
225 { P_PLL8, 3 },
226 { P_PLL0, 2 }
227 };
228
229 static const char * const gcc_pxo_pll8_pll0_map[] = {
230 "pxo",
231 "pll8_vote",
232 "pll0_vote",
233 };
234
235 static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
236 { P_PXO, 0 },
237 { P_PLL8, 4 },
238 { P_PLL0, 2 },
239 { P_PLL14, 5 },
240 { P_PLL18, 1 }
241 };
242
243 static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = {
244 "pxo",
245 "pll8_vote",
246 "pll0_vote",
247 "pll14",
248 "pll18",
249 };
250
251 static struct freq_tbl clk_tbl_gsbi_uart[] = {
252 { 1843200, P_PLL8, 2, 6, 625 },
253 { 3686400, P_PLL8, 2, 12, 625 },
254 { 7372800, P_PLL8, 2, 24, 625 },
255 { 14745600, P_PLL8, 2, 48, 625 },
256 { 16000000, P_PLL8, 4, 1, 6 },
257 { 24000000, P_PLL8, 4, 1, 4 },
258 { 32000000, P_PLL8, 4, 1, 3 },
259 { 40000000, P_PLL8, 1, 5, 48 },
260 { 46400000, P_PLL8, 1, 29, 240 },
261 { 48000000, P_PLL8, 4, 1, 2 },
262 { 51200000, P_PLL8, 1, 2, 15 },
263 { 56000000, P_PLL8, 1, 7, 48 },
264 { 58982400, P_PLL8, 1, 96, 625 },
265 { 64000000, P_PLL8, 2, 1, 3 },
266 { }
267 };
268
269 static struct clk_rcg gsbi1_uart_src = {
270 .ns_reg = 0x29d4,
271 .md_reg = 0x29d0,
272 .mn = {
273 .mnctr_en_bit = 8,
274 .mnctr_reset_bit = 7,
275 .mnctr_mode_shift = 5,
276 .n_val_shift = 16,
277 .m_val_shift = 16,
278 .width = 16,
279 },
280 .p = {
281 .pre_div_shift = 3,
282 .pre_div_width = 2,
283 },
284 .s = {
285 .src_sel_shift = 0,
286 .parent_map = gcc_pxo_pll8_map,
287 },
288 .freq_tbl = clk_tbl_gsbi_uart,
289 .clkr = {
290 .enable_reg = 0x29d4,
291 .enable_mask = BIT(11),
292 .hw.init = &(struct clk_init_data){
293 .name = "gsbi1_uart_src",
294 .parent_names = gcc_pxo_pll8,
295 .num_parents = 2,
296 .ops = &clk_rcg_ops,
297 .flags = CLK_SET_PARENT_GATE,
298 },
299 },
300 };
301
302 static struct clk_branch gsbi1_uart_clk = {
303 .halt_reg = 0x2fcc,
304 .halt_bit = 12,
305 .clkr = {
306 .enable_reg = 0x29d4,
307 .enable_mask = BIT(9),
308 .hw.init = &(struct clk_init_data){
309 .name = "gsbi1_uart_clk",
310 .parent_names = (const char *[]){
311 "gsbi1_uart_src",
312 },
313 .num_parents = 1,
314 .ops = &clk_branch_ops,
315 .flags = CLK_SET_RATE_PARENT,
316 },
317 },
318 };
319
320 static struct clk_rcg gsbi2_uart_src = {
321 .ns_reg = 0x29f4,
322 .md_reg = 0x29f0,
323 .mn = {
324 .mnctr_en_bit = 8,
325 .mnctr_reset_bit = 7,
326 .mnctr_mode_shift = 5,
327 .n_val_shift = 16,
328 .m_val_shift = 16,
329 .width = 16,
330 },
331 .p = {
332 .pre_div_shift = 3,
333 .pre_div_width = 2,
334 },
335 .s = {
336 .src_sel_shift = 0,
337 .parent_map = gcc_pxo_pll8_map,
338 },
339 .freq_tbl = clk_tbl_gsbi_uart,
340 .clkr = {
341 .enable_reg = 0x29f4,
342 .enable_mask = BIT(11),
343 .hw.init = &(struct clk_init_data){
344 .name = "gsbi2_uart_src",
345 .parent_names = gcc_pxo_pll8,
346 .num_parents = 2,
347 .ops = &clk_rcg_ops,
348 .flags = CLK_SET_PARENT_GATE,
349 },
350 },
351 };
352
353 static struct clk_branch gsbi2_uart_clk = {
354 .halt_reg = 0x2fcc,
355 .halt_bit = 8,
356 .clkr = {
357 .enable_reg = 0x29f4,
358 .enable_mask = BIT(9),
359 .hw.init = &(struct clk_init_data){
360 .name = "gsbi2_uart_clk",
361 .parent_names = (const char *[]){
362 "gsbi2_uart_src",
363 },
364 .num_parents = 1,
365 .ops = &clk_branch_ops,
366 .flags = CLK_SET_RATE_PARENT,
367 },
368 },
369 };
370
371 static struct clk_rcg gsbi4_uart_src = {
372 .ns_reg = 0x2a34,
373 .md_reg = 0x2a30,
374 .mn = {
375 .mnctr_en_bit = 8,
376 .mnctr_reset_bit = 7,
377 .mnctr_mode_shift = 5,
378 .n_val_shift = 16,
379 .m_val_shift = 16,
380 .width = 16,
381 },
382 .p = {
383 .pre_div_shift = 3,
384 .pre_div_width = 2,
385 },
386 .s = {
387 .src_sel_shift = 0,
388 .parent_map = gcc_pxo_pll8_map,
389 },
390 .freq_tbl = clk_tbl_gsbi_uart,
391 .clkr = {
392 .enable_reg = 0x2a34,
393 .enable_mask = BIT(11),
394 .hw.init = &(struct clk_init_data){
395 .name = "gsbi4_uart_src",
396 .parent_names = gcc_pxo_pll8,
397 .num_parents = 2,
398 .ops = &clk_rcg_ops,
399 .flags = CLK_SET_PARENT_GATE,
400 },
401 },
402 };
403
404 static struct clk_branch gsbi4_uart_clk = {
405 .halt_reg = 0x2fd0,
406 .halt_bit = 26,
407 .clkr = {
408 .enable_reg = 0x2a34,
409 .enable_mask = BIT(9),
410 .hw.init = &(struct clk_init_data){
411 .name = "gsbi4_uart_clk",
412 .parent_names = (const char *[]){
413 "gsbi4_uart_src",
414 },
415 .num_parents = 1,
416 .ops = &clk_branch_ops,
417 .flags = CLK_SET_RATE_PARENT,
418 },
419 },
420 };
421
422 static struct clk_rcg gsbi5_uart_src = {
423 .ns_reg = 0x2a54,
424 .md_reg = 0x2a50,
425 .mn = {
426 .mnctr_en_bit = 8,
427 .mnctr_reset_bit = 7,
428 .mnctr_mode_shift = 5,
429 .n_val_shift = 16,
430 .m_val_shift = 16,
431 .width = 16,
432 },
433 .p = {
434 .pre_div_shift = 3,
435 .pre_div_width = 2,
436 },
437 .s = {
438 .src_sel_shift = 0,
439 .parent_map = gcc_pxo_pll8_map,
440 },
441 .freq_tbl = clk_tbl_gsbi_uart,
442 .clkr = {
443 .enable_reg = 0x2a54,
444 .enable_mask = BIT(11),
445 .hw.init = &(struct clk_init_data){
446 .name = "gsbi5_uart_src",
447 .parent_names = gcc_pxo_pll8,
448 .num_parents = 2,
449 .ops = &clk_rcg_ops,
450 .flags = CLK_SET_PARENT_GATE,
451 },
452 },
453 };
454
455 static struct clk_branch gsbi5_uart_clk = {
456 .halt_reg = 0x2fd0,
457 .halt_bit = 22,
458 .clkr = {
459 .enable_reg = 0x2a54,
460 .enable_mask = BIT(9),
461 .hw.init = &(struct clk_init_data){
462 .name = "gsbi5_uart_clk",
463 .parent_names = (const char *[]){
464 "gsbi5_uart_src",
465 },
466 .num_parents = 1,
467 .ops = &clk_branch_ops,
468 .flags = CLK_SET_RATE_PARENT,
469 },
470 },
471 };
472
473 static struct clk_rcg gsbi6_uart_src = {
474 .ns_reg = 0x2a74,
475 .md_reg = 0x2a70,
476 .mn = {
477 .mnctr_en_bit = 8,
478 .mnctr_reset_bit = 7,
479 .mnctr_mode_shift = 5,
480 .n_val_shift = 16,
481 .m_val_shift = 16,
482 .width = 16,
483 },
484 .p = {
485 .pre_div_shift = 3,
486 .pre_div_width = 2,
487 },
488 .s = {
489 .src_sel_shift = 0,
490 .parent_map = gcc_pxo_pll8_map,
491 },
492 .freq_tbl = clk_tbl_gsbi_uart,
493 .clkr = {
494 .enable_reg = 0x2a74,
495 .enable_mask = BIT(11),
496 .hw.init = &(struct clk_init_data){
497 .name = "gsbi6_uart_src",
498 .parent_names = gcc_pxo_pll8,
499 .num_parents = 2,
500 .ops = &clk_rcg_ops,
501 .flags = CLK_SET_PARENT_GATE,
502 },
503 },
504 };
505
506 static struct clk_branch gsbi6_uart_clk = {
507 .halt_reg = 0x2fd0,
508 .halt_bit = 18,
509 .clkr = {
510 .enable_reg = 0x2a74,
511 .enable_mask = BIT(9),
512 .hw.init = &(struct clk_init_data){
513 .name = "gsbi6_uart_clk",
514 .parent_names = (const char *[]){
515 "gsbi6_uart_src",
516 },
517 .num_parents = 1,
518 .ops = &clk_branch_ops,
519 .flags = CLK_SET_RATE_PARENT,
520 },
521 },
522 };
523
524 static struct clk_rcg gsbi7_uart_src = {
525 .ns_reg = 0x2a94,
526 .md_reg = 0x2a90,
527 .mn = {
528 .mnctr_en_bit = 8,
529 .mnctr_reset_bit = 7,
530 .mnctr_mode_shift = 5,
531 .n_val_shift = 16,
532 .m_val_shift = 16,
533 .width = 16,
534 },
535 .p = {
536 .pre_div_shift = 3,
537 .pre_div_width = 2,
538 },
539 .s = {
540 .src_sel_shift = 0,
541 .parent_map = gcc_pxo_pll8_map,
542 },
543 .freq_tbl = clk_tbl_gsbi_uart,
544 .clkr = {
545 .enable_reg = 0x2a94,
546 .enable_mask = BIT(11),
547 .hw.init = &(struct clk_init_data){
548 .name = "gsbi7_uart_src",
549 .parent_names = gcc_pxo_pll8,
550 .num_parents = 2,
551 .ops = &clk_rcg_ops,
552 .flags = CLK_SET_PARENT_GATE,
553 },
554 },
555 };
556
557 static struct clk_branch gsbi7_uart_clk = {
558 .halt_reg = 0x2fd0,
559 .halt_bit = 14,
560 .clkr = {
561 .enable_reg = 0x2a94,
562 .enable_mask = BIT(9),
563 .hw.init = &(struct clk_init_data){
564 .name = "gsbi7_uart_clk",
565 .parent_names = (const char *[]){
566 "gsbi7_uart_src",
567 },
568 .num_parents = 1,
569 .ops = &clk_branch_ops,
570 .flags = CLK_SET_RATE_PARENT,
571 },
572 },
573 };
574
575 static struct freq_tbl clk_tbl_gsbi_qup[] = {
576 { 1100000, P_PXO, 1, 2, 49 },
577 { 5400000, P_PXO, 1, 1, 5 },
578 { 10800000, P_PXO, 1, 2, 5 },
579 { 15060000, P_PLL8, 1, 2, 51 },
580 { 24000000, P_PLL8, 4, 1, 4 },
581 { 25000000, P_PXO, 1, 0, 0 },
582 { 25600000, P_PLL8, 1, 1, 15 },
583 { 48000000, P_PLL8, 4, 1, 2 },
584 { 51200000, P_PLL8, 1, 2, 15 },
585 { }
586 };
587
588 static struct clk_rcg gsbi1_qup_src = {
589 .ns_reg = 0x29cc,
590 .md_reg = 0x29c8,
591 .mn = {
592 .mnctr_en_bit = 8,
593 .mnctr_reset_bit = 7,
594 .mnctr_mode_shift = 5,
595 .n_val_shift = 16,
596 .m_val_shift = 16,
597 .width = 8,
598 },
599 .p = {
600 .pre_div_shift = 3,
601 .pre_div_width = 2,
602 },
603 .s = {
604 .src_sel_shift = 0,
605 .parent_map = gcc_pxo_pll8_map,
606 },
607 .freq_tbl = clk_tbl_gsbi_qup,
608 .clkr = {
609 .enable_reg = 0x29cc,
610 .enable_mask = BIT(11),
611 .hw.init = &(struct clk_init_data){
612 .name = "gsbi1_qup_src",
613 .parent_names = gcc_pxo_pll8,
614 .num_parents = 2,
615 .ops = &clk_rcg_ops,
616 .flags = CLK_SET_PARENT_GATE,
617 },
618 },
619 };
620
621 static struct clk_branch gsbi1_qup_clk = {
622 .halt_reg = 0x2fcc,
623 .halt_bit = 11,
624 .clkr = {
625 .enable_reg = 0x29cc,
626 .enable_mask = BIT(9),
627 .hw.init = &(struct clk_init_data){
628 .name = "gsbi1_qup_clk",
629 .parent_names = (const char *[]){ "gsbi1_qup_src" },
630 .num_parents = 1,
631 .ops = &clk_branch_ops,
632 .flags = CLK_SET_RATE_PARENT,
633 },
634 },
635 };
636
637 static struct clk_rcg gsbi2_qup_src = {
638 .ns_reg = 0x29ec,
639 .md_reg = 0x29e8,
640 .mn = {
641 .mnctr_en_bit = 8,
642 .mnctr_reset_bit = 7,
643 .mnctr_mode_shift = 5,
644 .n_val_shift = 16,
645 .m_val_shift = 16,
646 .width = 8,
647 },
648 .p = {
649 .pre_div_shift = 3,
650 .pre_div_width = 2,
651 },
652 .s = {
653 .src_sel_shift = 0,
654 .parent_map = gcc_pxo_pll8_map,
655 },
656 .freq_tbl = clk_tbl_gsbi_qup,
657 .clkr = {
658 .enable_reg = 0x29ec,
659 .enable_mask = BIT(11),
660 .hw.init = &(struct clk_init_data){
661 .name = "gsbi2_qup_src",
662 .parent_names = gcc_pxo_pll8,
663 .num_parents = 2,
664 .ops = &clk_rcg_ops,
665 .flags = CLK_SET_PARENT_GATE,
666 },
667 },
668 };
669
670 static struct clk_branch gsbi2_qup_clk = {
671 .halt_reg = 0x2fcc,
672 .halt_bit = 6,
673 .clkr = {
674 .enable_reg = 0x29ec,
675 .enable_mask = BIT(9),
676 .hw.init = &(struct clk_init_data){
677 .name = "gsbi2_qup_clk",
678 .parent_names = (const char *[]){ "gsbi2_qup_src" },
679 .num_parents = 1,
680 .ops = &clk_branch_ops,
681 .flags = CLK_SET_RATE_PARENT,
682 },
683 },
684 };
685
686 static struct clk_rcg gsbi4_qup_src = {
687 .ns_reg = 0x2a2c,
688 .md_reg = 0x2a28,
689 .mn = {
690 .mnctr_en_bit = 8,
691 .mnctr_reset_bit = 7,
692 .mnctr_mode_shift = 5,
693 .n_val_shift = 16,
694 .m_val_shift = 16,
695 .width = 8,
696 },
697 .p = {
698 .pre_div_shift = 3,
699 .pre_div_width = 2,
700 },
701 .s = {
702 .src_sel_shift = 0,
703 .parent_map = gcc_pxo_pll8_map,
704 },
705 .freq_tbl = clk_tbl_gsbi_qup,
706 .clkr = {
707 .enable_reg = 0x2a2c,
708 .enable_mask = BIT(11),
709 .hw.init = &(struct clk_init_data){
710 .name = "gsbi4_qup_src",
711 .parent_names = gcc_pxo_pll8,
712 .num_parents = 2,
713 .ops = &clk_rcg_ops,
714 .flags = CLK_SET_PARENT_GATE,
715 },
716 },
717 };
718
719 static struct clk_branch gsbi4_qup_clk = {
720 .halt_reg = 0x2fd0,
721 .halt_bit = 24,
722 .clkr = {
723 .enable_reg = 0x2a2c,
724 .enable_mask = BIT(9),
725 .hw.init = &(struct clk_init_data){
726 .name = "gsbi4_qup_clk",
727 .parent_names = (const char *[]){ "gsbi4_qup_src" },
728 .num_parents = 1,
729 .ops = &clk_branch_ops,
730 .flags = CLK_SET_RATE_PARENT,
731 },
732 },
733 };
734
735 static struct clk_rcg gsbi5_qup_src = {
736 .ns_reg = 0x2a4c,
737 .md_reg = 0x2a48,
738 .mn = {
739 .mnctr_en_bit = 8,
740 .mnctr_reset_bit = 7,
741 .mnctr_mode_shift = 5,
742 .n_val_shift = 16,
743 .m_val_shift = 16,
744 .width = 8,
745 },
746 .p = {
747 .pre_div_shift = 3,
748 .pre_div_width = 2,
749 },
750 .s = {
751 .src_sel_shift = 0,
752 .parent_map = gcc_pxo_pll8_map,
753 },
754 .freq_tbl = clk_tbl_gsbi_qup,
755 .clkr = {
756 .enable_reg = 0x2a4c,
757 .enable_mask = BIT(11),
758 .hw.init = &(struct clk_init_data){
759 .name = "gsbi5_qup_src",
760 .parent_names = gcc_pxo_pll8,
761 .num_parents = 2,
762 .ops = &clk_rcg_ops,
763 .flags = CLK_SET_PARENT_GATE,
764 },
765 },
766 };
767
768 static struct clk_branch gsbi5_qup_clk = {
769 .halt_reg = 0x2fd0,
770 .halt_bit = 20,
771 .clkr = {
772 .enable_reg = 0x2a4c,
773 .enable_mask = BIT(9),
774 .hw.init = &(struct clk_init_data){
775 .name = "gsbi5_qup_clk",
776 .parent_names = (const char *[]){ "gsbi5_qup_src" },
777 .num_parents = 1,
778 .ops = &clk_branch_ops,
779 .flags = CLK_SET_RATE_PARENT,
780 },
781 },
782 };
783
784 static struct clk_rcg gsbi6_qup_src = {
785 .ns_reg = 0x2a6c,
786 .md_reg = 0x2a68,
787 .mn = {
788 .mnctr_en_bit = 8,
789 .mnctr_reset_bit = 7,
790 .mnctr_mode_shift = 5,
791 .n_val_shift = 16,
792 .m_val_shift = 16,
793 .width = 8,
794 },
795 .p = {
796 .pre_div_shift = 3,
797 .pre_div_width = 2,
798 },
799 .s = {
800 .src_sel_shift = 0,
801 .parent_map = gcc_pxo_pll8_map,
802 },
803 .freq_tbl = clk_tbl_gsbi_qup,
804 .clkr = {
805 .enable_reg = 0x2a6c,
806 .enable_mask = BIT(11),
807 .hw.init = &(struct clk_init_data){
808 .name = "gsbi6_qup_src",
809 .parent_names = gcc_pxo_pll8,
810 .num_parents = 2,
811 .ops = &clk_rcg_ops,
812 .flags = CLK_SET_PARENT_GATE,
813 },
814 },
815 };
816
817 static struct clk_branch gsbi6_qup_clk = {
818 .halt_reg = 0x2fd0,
819 .halt_bit = 16,
820 .clkr = {
821 .enable_reg = 0x2a6c,
822 .enable_mask = BIT(9),
823 .hw.init = &(struct clk_init_data){
824 .name = "gsbi6_qup_clk",
825 .parent_names = (const char *[]){ "gsbi6_qup_src" },
826 .num_parents = 1,
827 .ops = &clk_branch_ops,
828 .flags = CLK_SET_RATE_PARENT,
829 },
830 },
831 };
832
833 static struct clk_rcg gsbi7_qup_src = {
834 .ns_reg = 0x2a8c,
835 .md_reg = 0x2a88,
836 .mn = {
837 .mnctr_en_bit = 8,
838 .mnctr_reset_bit = 7,
839 .mnctr_mode_shift = 5,
840 .n_val_shift = 16,
841 .m_val_shift = 16,
842 .width = 8,
843 },
844 .p = {
845 .pre_div_shift = 3,
846 .pre_div_width = 2,
847 },
848 .s = {
849 .src_sel_shift = 0,
850 .parent_map = gcc_pxo_pll8_map,
851 },
852 .freq_tbl = clk_tbl_gsbi_qup,
853 .clkr = {
854 .enable_reg = 0x2a8c,
855 .enable_mask = BIT(11),
856 .hw.init = &(struct clk_init_data){
857 .name = "gsbi7_qup_src",
858 .parent_names = gcc_pxo_pll8,
859 .num_parents = 2,
860 .ops = &clk_rcg_ops,
861 .flags = CLK_SET_PARENT_GATE,
862 },
863 },
864 };
865
866 static struct clk_branch gsbi7_qup_clk = {
867 .halt_reg = 0x2fd0,
868 .halt_bit = 12,
869 .clkr = {
870 .enable_reg = 0x2a8c,
871 .enable_mask = BIT(9),
872 .hw.init = &(struct clk_init_data){
873 .name = "gsbi7_qup_clk",
874 .parent_names = (const char *[]){ "gsbi7_qup_src" },
875 .num_parents = 1,
876 .ops = &clk_branch_ops,
877 .flags = CLK_SET_RATE_PARENT,
878 },
879 },
880 };
881
882 static struct clk_branch gsbi1_h_clk = {
883 .hwcg_reg = 0x29c0,
884 .hwcg_bit = 6,
885 .halt_reg = 0x2fcc,
886 .halt_bit = 13,
887 .clkr = {
888 .enable_reg = 0x29c0,
889 .enable_mask = BIT(4),
890 .hw.init = &(struct clk_init_data){
891 .name = "gsbi1_h_clk",
892 .ops = &clk_branch_ops,
893 },
894 },
895 };
896
897 static struct clk_branch gsbi2_h_clk = {
898 .hwcg_reg = 0x29e0,
899 .hwcg_bit = 6,
900 .halt_reg = 0x2fcc,
901 .halt_bit = 9,
902 .clkr = {
903 .enable_reg = 0x29e0,
904 .enable_mask = BIT(4),
905 .hw.init = &(struct clk_init_data){
906 .name = "gsbi2_h_clk",
907 .ops = &clk_branch_ops,
908 },
909 },
910 };
911
912 static struct clk_branch gsbi4_h_clk = {
913 .hwcg_reg = 0x2a20,
914 .hwcg_bit = 6,
915 .halt_reg = 0x2fd0,
916 .halt_bit = 27,
917 .clkr = {
918 .enable_reg = 0x2a20,
919 .enable_mask = BIT(4),
920 .hw.init = &(struct clk_init_data){
921 .name = "gsbi4_h_clk",
922 .ops = &clk_branch_ops,
923 },
924 },
925 };
926
927 static struct clk_branch gsbi5_h_clk = {
928 .hwcg_reg = 0x2a40,
929 .hwcg_bit = 6,
930 .halt_reg = 0x2fd0,
931 .halt_bit = 23,
932 .clkr = {
933 .enable_reg = 0x2a40,
934 .enable_mask = BIT(4),
935 .hw.init = &(struct clk_init_data){
936 .name = "gsbi5_h_clk",
937 .ops = &clk_branch_ops,
938 },
939 },
940 };
941
942 static struct clk_branch gsbi6_h_clk = {
943 .hwcg_reg = 0x2a60,
944 .hwcg_bit = 6,
945 .halt_reg = 0x2fd0,
946 .halt_bit = 19,
947 .clkr = {
948 .enable_reg = 0x2a60,
949 .enable_mask = BIT(4),
950 .hw.init = &(struct clk_init_data){
951 .name = "gsbi6_h_clk",
952 .ops = &clk_branch_ops,
953 },
954 },
955 };
956
957 static struct clk_branch gsbi7_h_clk = {
958 .hwcg_reg = 0x2a80,
959 .hwcg_bit = 6,
960 .halt_reg = 0x2fd0,
961 .halt_bit = 15,
962 .clkr = {
963 .enable_reg = 0x2a80,
964 .enable_mask = BIT(4),
965 .hw.init = &(struct clk_init_data){
966 .name = "gsbi7_h_clk",
967 .ops = &clk_branch_ops,
968 },
969 },
970 };
971
972 static const struct freq_tbl clk_tbl_gp[] = {
973 { 12500000, P_PXO, 2, 0, 0 },
974 { 25000000, P_PXO, 1, 0, 0 },
975 { 64000000, P_PLL8, 2, 1, 3 },
976 { 76800000, P_PLL8, 1, 1, 5 },
977 { 96000000, P_PLL8, 4, 0, 0 },
978 { 128000000, P_PLL8, 3, 0, 0 },
979 { 192000000, P_PLL8, 2, 0, 0 },
980 { }
981 };
982
983 static struct clk_rcg gp0_src = {
984 .ns_reg = 0x2d24,
985 .md_reg = 0x2d00,
986 .mn = {
987 .mnctr_en_bit = 8,
988 .mnctr_reset_bit = 7,
989 .mnctr_mode_shift = 5,
990 .n_val_shift = 16,
991 .m_val_shift = 16,
992 .width = 8,
993 },
994 .p = {
995 .pre_div_shift = 3,
996 .pre_div_width = 2,
997 },
998 .s = {
999 .src_sel_shift = 0,
1000 .parent_map = gcc_pxo_pll8_cxo_map,
1001 },
1002 .freq_tbl = clk_tbl_gp,
1003 .clkr = {
1004 .enable_reg = 0x2d24,
1005 .enable_mask = BIT(11),
1006 .hw.init = &(struct clk_init_data){
1007 .name = "gp0_src",
1008 .parent_names = gcc_pxo_pll8_cxo,
1009 .num_parents = 3,
1010 .ops = &clk_rcg_ops,
1011 .flags = CLK_SET_PARENT_GATE,
1012 },
1013 }
1014 };
1015
1016 static struct clk_branch gp0_clk = {
1017 .halt_reg = 0x2fd8,
1018 .halt_bit = 7,
1019 .clkr = {
1020 .enable_reg = 0x2d24,
1021 .enable_mask = BIT(9),
1022 .hw.init = &(struct clk_init_data){
1023 .name = "gp0_clk",
1024 .parent_names = (const char *[]){ "gp0_src" },
1025 .num_parents = 1,
1026 .ops = &clk_branch_ops,
1027 .flags = CLK_SET_RATE_PARENT,
1028 },
1029 },
1030 };
1031
1032 static struct clk_rcg gp1_src = {
1033 .ns_reg = 0x2d44,
1034 .md_reg = 0x2d40,
1035 .mn = {
1036 .mnctr_en_bit = 8,
1037 .mnctr_reset_bit = 7,
1038 .mnctr_mode_shift = 5,
1039 .n_val_shift = 16,
1040 .m_val_shift = 16,
1041 .width = 8,
1042 },
1043 .p = {
1044 .pre_div_shift = 3,
1045 .pre_div_width = 2,
1046 },
1047 .s = {
1048 .src_sel_shift = 0,
1049 .parent_map = gcc_pxo_pll8_cxo_map,
1050 },
1051 .freq_tbl = clk_tbl_gp,
1052 .clkr = {
1053 .enable_reg = 0x2d44,
1054 .enable_mask = BIT(11),
1055 .hw.init = &(struct clk_init_data){
1056 .name = "gp1_src",
1057 .parent_names = gcc_pxo_pll8_cxo,
1058 .num_parents = 3,
1059 .ops = &clk_rcg_ops,
1060 .flags = CLK_SET_RATE_GATE,
1061 },
1062 }
1063 };
1064
1065 static struct clk_branch gp1_clk = {
1066 .halt_reg = 0x2fd8,
1067 .halt_bit = 6,
1068 .clkr = {
1069 .enable_reg = 0x2d44,
1070 .enable_mask = BIT(9),
1071 .hw.init = &(struct clk_init_data){
1072 .name = "gp1_clk",
1073 .parent_names = (const char *[]){ "gp1_src" },
1074 .num_parents = 1,
1075 .ops = &clk_branch_ops,
1076 .flags = CLK_SET_RATE_PARENT,
1077 },
1078 },
1079 };
1080
1081 static struct clk_rcg gp2_src = {
1082 .ns_reg = 0x2d64,
1083 .md_reg = 0x2d60,
1084 .mn = {
1085 .mnctr_en_bit = 8,
1086 .mnctr_reset_bit = 7,
1087 .mnctr_mode_shift = 5,
1088 .n_val_shift = 16,
1089 .m_val_shift = 16,
1090 .width = 8,
1091 },
1092 .p = {
1093 .pre_div_shift = 3,
1094 .pre_div_width = 2,
1095 },
1096 .s = {
1097 .src_sel_shift = 0,
1098 .parent_map = gcc_pxo_pll8_cxo_map,
1099 },
1100 .freq_tbl = clk_tbl_gp,
1101 .clkr = {
1102 .enable_reg = 0x2d64,
1103 .enable_mask = BIT(11),
1104 .hw.init = &(struct clk_init_data){
1105 .name = "gp2_src",
1106 .parent_names = gcc_pxo_pll8_cxo,
1107 .num_parents = 3,
1108 .ops = &clk_rcg_ops,
1109 .flags = CLK_SET_RATE_GATE,
1110 },
1111 }
1112 };
1113
1114 static struct clk_branch gp2_clk = {
1115 .halt_reg = 0x2fd8,
1116 .halt_bit = 5,
1117 .clkr = {
1118 .enable_reg = 0x2d64,
1119 .enable_mask = BIT(9),
1120 .hw.init = &(struct clk_init_data){
1121 .name = "gp2_clk",
1122 .parent_names = (const char *[]){ "gp2_src" },
1123 .num_parents = 1,
1124 .ops = &clk_branch_ops,
1125 .flags = CLK_SET_RATE_PARENT,
1126 },
1127 },
1128 };
1129
1130 static struct clk_branch pmem_clk = {
1131 .hwcg_reg = 0x25a0,
1132 .hwcg_bit = 6,
1133 .halt_reg = 0x2fc8,
1134 .halt_bit = 20,
1135 .clkr = {
1136 .enable_reg = 0x25a0,
1137 .enable_mask = BIT(4),
1138 .hw.init = &(struct clk_init_data){
1139 .name = "pmem_clk",
1140 .ops = &clk_branch_ops,
1141 },
1142 },
1143 };
1144
1145 static struct clk_rcg prng_src = {
1146 .ns_reg = 0x2e80,
1147 .p = {
1148 .pre_div_shift = 3,
1149 .pre_div_width = 4,
1150 },
1151 .s = {
1152 .src_sel_shift = 0,
1153 .parent_map = gcc_pxo_pll8_map,
1154 },
1155 .clkr = {
1156 .hw.init = &(struct clk_init_data){
1157 .name = "prng_src",
1158 .parent_names = gcc_pxo_pll8,
1159 .num_parents = 2,
1160 .ops = &clk_rcg_ops,
1161 },
1162 },
1163 };
1164
1165 static struct clk_branch prng_clk = {
1166 .halt_reg = 0x2fd8,
1167 .halt_check = BRANCH_HALT_VOTED,
1168 .halt_bit = 10,
1169 .clkr = {
1170 .enable_reg = 0x3080,
1171 .enable_mask = BIT(10),
1172 .hw.init = &(struct clk_init_data){
1173 .name = "prng_clk",
1174 .parent_names = (const char *[]){ "prng_src" },
1175 .num_parents = 1,
1176 .ops = &clk_branch_ops,
1177 },
1178 },
1179 };
1180
1181 static const struct freq_tbl clk_tbl_sdc[] = {
1182 { 200000, P_PXO, 2, 2, 125 },
1183 { 400000, P_PLL8, 4, 1, 240 },
1184 { 16000000, P_PLL8, 4, 1, 6 },
1185 { 17070000, P_PLL8, 1, 2, 45 },
1186 { 20210000, P_PLL8, 1, 1, 19 },
1187 { 24000000, P_PLL8, 4, 1, 4 },
1188 { 48000000, P_PLL8, 4, 1, 2 },
1189 { 64000000, P_PLL8, 3, 1, 2 },
1190 { 96000000, P_PLL8, 4, 0, 0 },
1191 { 192000000, P_PLL8, 2, 0, 0 },
1192 { }
1193 };
1194
1195 static struct clk_rcg sdc1_src = {
1196 .ns_reg = 0x282c,
1197 .md_reg = 0x2828,
1198 .mn = {
1199 .mnctr_en_bit = 8,
1200 .mnctr_reset_bit = 7,
1201 .mnctr_mode_shift = 5,
1202 .n_val_shift = 16,
1203 .m_val_shift = 16,
1204 .width = 8,
1205 },
1206 .p = {
1207 .pre_div_shift = 3,
1208 .pre_div_width = 2,
1209 },
1210 .s = {
1211 .src_sel_shift = 0,
1212 .parent_map = gcc_pxo_pll8_map,
1213 },
1214 .freq_tbl = clk_tbl_sdc,
1215 .clkr = {
1216 .enable_reg = 0x282c,
1217 .enable_mask = BIT(11),
1218 .hw.init = &(struct clk_init_data){
1219 .name = "sdc1_src",
1220 .parent_names = gcc_pxo_pll8,
1221 .num_parents = 2,
1222 .ops = &clk_rcg_ops,
1223 },
1224 }
1225 };
1226
1227 static struct clk_branch sdc1_clk = {
1228 .halt_reg = 0x2fc8,
1229 .halt_bit = 6,
1230 .clkr = {
1231 .enable_reg = 0x282c,
1232 .enable_mask = BIT(9),
1233 .hw.init = &(struct clk_init_data){
1234 .name = "sdc1_clk",
1235 .parent_names = (const char *[]){ "sdc1_src" },
1236 .num_parents = 1,
1237 .ops = &clk_branch_ops,
1238 .flags = CLK_SET_RATE_PARENT,
1239 },
1240 },
1241 };
1242
1243 static struct clk_rcg sdc3_src = {
1244 .ns_reg = 0x286c,
1245 .md_reg = 0x2868,
1246 .mn = {
1247 .mnctr_en_bit = 8,
1248 .mnctr_reset_bit = 7,
1249 .mnctr_mode_shift = 5,
1250 .n_val_shift = 16,
1251 .m_val_shift = 16,
1252 .width = 8,
1253 },
1254 .p = {
1255 .pre_div_shift = 3,
1256 .pre_div_width = 2,
1257 },
1258 .s = {
1259 .src_sel_shift = 0,
1260 .parent_map = gcc_pxo_pll8_map,
1261 },
1262 .freq_tbl = clk_tbl_sdc,
1263 .clkr = {
1264 .enable_reg = 0x286c,
1265 .enable_mask = BIT(11),
1266 .hw.init = &(struct clk_init_data){
1267 .name = "sdc3_src",
1268 .parent_names = gcc_pxo_pll8,
1269 .num_parents = 2,
1270 .ops = &clk_rcg_ops,
1271 },
1272 }
1273 };
1274
1275 static struct clk_branch sdc3_clk = {
1276 .halt_reg = 0x2fc8,
1277 .halt_bit = 4,
1278 .clkr = {
1279 .enable_reg = 0x286c,
1280 .enable_mask = BIT(9),
1281 .hw.init = &(struct clk_init_data){
1282 .name = "sdc3_clk",
1283 .parent_names = (const char *[]){ "sdc3_src" },
1284 .num_parents = 1,
1285 .ops = &clk_branch_ops,
1286 .flags = CLK_SET_RATE_PARENT,
1287 },
1288 },
1289 };
1290
1291 static struct clk_branch sdc1_h_clk = {
1292 .hwcg_reg = 0x2820,
1293 .hwcg_bit = 6,
1294 .halt_reg = 0x2fc8,
1295 .halt_bit = 11,
1296 .clkr = {
1297 .enable_reg = 0x2820,
1298 .enable_mask = BIT(4),
1299 .hw.init = &(struct clk_init_data){
1300 .name = "sdc1_h_clk",
1301 .ops = &clk_branch_ops,
1302 },
1303 },
1304 };
1305
1306 static struct clk_branch sdc3_h_clk = {
1307 .hwcg_reg = 0x2860,
1308 .hwcg_bit = 6,
1309 .halt_reg = 0x2fc8,
1310 .halt_bit = 9,
1311 .clkr = {
1312 .enable_reg = 0x2860,
1313 .enable_mask = BIT(4),
1314 .hw.init = &(struct clk_init_data){
1315 .name = "sdc3_h_clk",
1316 .ops = &clk_branch_ops,
1317 },
1318 },
1319 };
1320
1321 static const struct freq_tbl clk_tbl_tsif_ref[] = {
1322 { 105000, P_PXO, 1, 1, 256 },
1323 { }
1324 };
1325
1326 static struct clk_rcg tsif_ref_src = {
1327 .ns_reg = 0x2710,
1328 .md_reg = 0x270c,
1329 .mn = {
1330 .mnctr_en_bit = 8,
1331 .mnctr_reset_bit = 7,
1332 .mnctr_mode_shift = 5,
1333 .n_val_shift = 16,
1334 .m_val_shift = 16,
1335 .width = 16,
1336 },
1337 .p = {
1338 .pre_div_shift = 3,
1339 .pre_div_width = 2,
1340 },
1341 .s = {
1342 .src_sel_shift = 0,
1343 .parent_map = gcc_pxo_pll8_map,
1344 },
1345 .freq_tbl = clk_tbl_tsif_ref,
1346 .clkr = {
1347 .enable_reg = 0x2710,
1348 .enable_mask = BIT(11),
1349 .hw.init = &(struct clk_init_data){
1350 .name = "tsif_ref_src",
1351 .parent_names = gcc_pxo_pll8,
1352 .num_parents = 2,
1353 .ops = &clk_rcg_ops,
1354 },
1355 }
1356 };
1357
1358 static struct clk_branch tsif_ref_clk = {
1359 .halt_reg = 0x2fd4,
1360 .halt_bit = 5,
1361 .clkr = {
1362 .enable_reg = 0x2710,
1363 .enable_mask = BIT(9),
1364 .hw.init = &(struct clk_init_data){
1365 .name = "tsif_ref_clk",
1366 .parent_names = (const char *[]){ "tsif_ref_src" },
1367 .num_parents = 1,
1368 .ops = &clk_branch_ops,
1369 .flags = CLK_SET_RATE_PARENT,
1370 },
1371 },
1372 };
1373
1374 static struct clk_branch tsif_h_clk = {
1375 .hwcg_reg = 0x2700,
1376 .hwcg_bit = 6,
1377 .halt_reg = 0x2fd4,
1378 .halt_bit = 7,
1379 .clkr = {
1380 .enable_reg = 0x2700,
1381 .enable_mask = BIT(4),
1382 .hw.init = &(struct clk_init_data){
1383 .name = "tsif_h_clk",
1384 .ops = &clk_branch_ops,
1385 },
1386 },
1387 };
1388
1389 static struct clk_branch dma_bam_h_clk = {
1390 .hwcg_reg = 0x25c0,
1391 .hwcg_bit = 6,
1392 .halt_reg = 0x2fc8,
1393 .halt_bit = 12,
1394 .clkr = {
1395 .enable_reg = 0x25c0,
1396 .enable_mask = BIT(4),
1397 .hw.init = &(struct clk_init_data){
1398 .name = "dma_bam_h_clk",
1399 .ops = &clk_branch_ops,
1400 },
1401 },
1402 };
1403
1404 static struct clk_branch adm0_clk = {
1405 .halt_reg = 0x2fdc,
1406 .halt_check = BRANCH_HALT_VOTED,
1407 .halt_bit = 12,
1408 .clkr = {
1409 .enable_reg = 0x3080,
1410 .enable_mask = BIT(2),
1411 .hw.init = &(struct clk_init_data){
1412 .name = "adm0_clk",
1413 .ops = &clk_branch_ops,
1414 },
1415 },
1416 };
1417
1418 static struct clk_branch adm0_pbus_clk = {
1419 .hwcg_reg = 0x2208,
1420 .hwcg_bit = 6,
1421 .halt_reg = 0x2fdc,
1422 .halt_check = BRANCH_HALT_VOTED,
1423 .halt_bit = 11,
1424 .clkr = {
1425 .enable_reg = 0x3080,
1426 .enable_mask = BIT(3),
1427 .hw.init = &(struct clk_init_data){
1428 .name = "adm0_pbus_clk",
1429 .ops = &clk_branch_ops,
1430 },
1431 },
1432 };
1433
1434 static struct clk_branch pmic_arb0_h_clk = {
1435 .halt_reg = 0x2fd8,
1436 .halt_check = BRANCH_HALT_VOTED,
1437 .halt_bit = 22,
1438 .clkr = {
1439 .enable_reg = 0x3080,
1440 .enable_mask = BIT(8),
1441 .hw.init = &(struct clk_init_data){
1442 .name = "pmic_arb0_h_clk",
1443 .ops = &clk_branch_ops,
1444 },
1445 },
1446 };
1447
1448 static struct clk_branch pmic_arb1_h_clk = {
1449 .halt_reg = 0x2fd8,
1450 .halt_check = BRANCH_HALT_VOTED,
1451 .halt_bit = 21,
1452 .clkr = {
1453 .enable_reg = 0x3080,
1454 .enable_mask = BIT(9),
1455 .hw.init = &(struct clk_init_data){
1456 .name = "pmic_arb1_h_clk",
1457 .ops = &clk_branch_ops,
1458 },
1459 },
1460 };
1461
1462 static struct clk_branch pmic_ssbi2_clk = {
1463 .halt_reg = 0x2fd8,
1464 .halt_check = BRANCH_HALT_VOTED,
1465 .halt_bit = 23,
1466 .clkr = {
1467 .enable_reg = 0x3080,
1468 .enable_mask = BIT(7),
1469 .hw.init = &(struct clk_init_data){
1470 .name = "pmic_ssbi2_clk",
1471 .ops = &clk_branch_ops,
1472 },
1473 },
1474 };
1475
1476 static struct clk_branch rpm_msg_ram_h_clk = {
1477 .hwcg_reg = 0x27e0,
1478 .hwcg_bit = 6,
1479 .halt_reg = 0x2fd8,
1480 .halt_check = BRANCH_HALT_VOTED,
1481 .halt_bit = 12,
1482 .clkr = {
1483 .enable_reg = 0x3080,
1484 .enable_mask = BIT(6),
1485 .hw.init = &(struct clk_init_data){
1486 .name = "rpm_msg_ram_h_clk",
1487 .ops = &clk_branch_ops,
1488 },
1489 },
1490 };
1491
1492 static const struct freq_tbl clk_tbl_pcie_ref[] = {
1493 { 100000000, P_PLL3, 12, 0, 0 },
1494 { }
1495 };
1496
1497 static struct clk_rcg pcie_ref_src = {
1498 .ns_reg = 0x3860,
1499 .p = {
1500 .pre_div_shift = 3,
1501 .pre_div_width = 4,
1502 },
1503 .s = {
1504 .src_sel_shift = 0,
1505 .parent_map = gcc_pxo_pll3_map,
1506 },
1507 .freq_tbl = clk_tbl_pcie_ref,
1508 .clkr = {
1509 .enable_reg = 0x3860,
1510 .enable_mask = BIT(11),
1511 .hw.init = &(struct clk_init_data){
1512 .name = "pcie_ref_src",
1513 .parent_names = gcc_pxo_pll3,
1514 .num_parents = 2,
1515 .ops = &clk_rcg_ops,
1516 .flags = CLK_SET_RATE_GATE,
1517 },
1518 },
1519 };
1520
1521 static struct clk_branch pcie_ref_src_clk = {
1522 .halt_reg = 0x2fdc,
1523 .halt_bit = 30,
1524 .clkr = {
1525 .enable_reg = 0x3860,
1526 .enable_mask = BIT(9),
1527 .hw.init = &(struct clk_init_data){
1528 .name = "pcie_ref_src_clk",
1529 .parent_names = (const char *[]){ "pcie_ref_src" },
1530 .num_parents = 1,
1531 .ops = &clk_branch_ops,
1532 .flags = CLK_SET_RATE_PARENT,
1533 },
1534 },
1535 };
1536
1537 static struct clk_branch pcie_a_clk = {
1538 .halt_reg = 0x2fc0,
1539 .halt_bit = 13,
1540 .clkr = {
1541 .enable_reg = 0x22c0,
1542 .enable_mask = BIT(4),
1543 .hw.init = &(struct clk_init_data){
1544 .name = "pcie_a_clk",
1545 .ops = &clk_branch_ops,
1546 },
1547 },
1548 };
1549
1550 static struct clk_branch pcie_aux_clk = {
1551 .halt_reg = 0x2fdc,
1552 .halt_bit = 31,
1553 .clkr = {
1554 .enable_reg = 0x22c8,
1555 .enable_mask = BIT(4),
1556 .hw.init = &(struct clk_init_data){
1557 .name = "pcie_aux_clk",
1558 .ops = &clk_branch_ops,
1559 },
1560 },
1561 };
1562
1563 static struct clk_branch pcie_h_clk = {
1564 .halt_reg = 0x2fd4,
1565 .halt_bit = 8,
1566 .clkr = {
1567 .enable_reg = 0x22cc,
1568 .enable_mask = BIT(4),
1569 .hw.init = &(struct clk_init_data){
1570 .name = "pcie_h_clk",
1571 .ops = &clk_branch_ops,
1572 },
1573 },
1574 };
1575
1576 static struct clk_branch pcie_phy_clk = {
1577 .halt_reg = 0x2fdc,
1578 .halt_bit = 29,
1579 .clkr = {
1580 .enable_reg = 0x22d0,
1581 .enable_mask = BIT(4),
1582 .hw.init = &(struct clk_init_data){
1583 .name = "pcie_phy_clk",
1584 .ops = &clk_branch_ops,
1585 },
1586 },
1587 };
1588
1589 static struct clk_rcg pcie1_ref_src = {
1590 .ns_reg = 0x3aa0,
1591 .p = {
1592 .pre_div_shift = 3,
1593 .pre_div_width = 4,
1594 },
1595 .s = {
1596 .src_sel_shift = 0,
1597 .parent_map = gcc_pxo_pll3_map,
1598 },
1599 .freq_tbl = clk_tbl_pcie_ref,
1600 .clkr = {
1601 .enable_reg = 0x3aa0,
1602 .enable_mask = BIT(11),
1603 .hw.init = &(struct clk_init_data){
1604 .name = "pcie1_ref_src",
1605 .parent_names = gcc_pxo_pll3,
1606 .num_parents = 2,
1607 .ops = &clk_rcg_ops,
1608 .flags = CLK_SET_RATE_GATE,
1609 },
1610 },
1611 };
1612
1613 static struct clk_branch pcie1_ref_src_clk = {
1614 .halt_reg = 0x2fdc,
1615 .halt_bit = 27,
1616 .clkr = {
1617 .enable_reg = 0x3aa0,
1618 .enable_mask = BIT(9),
1619 .hw.init = &(struct clk_init_data){
1620 .name = "pcie1_ref_src_clk",
1621 .parent_names = (const char *[]){ "pcie1_ref_src" },
1622 .num_parents = 1,
1623 .ops = &clk_branch_ops,
1624 .flags = CLK_SET_RATE_PARENT,
1625 },
1626 },
1627 };
1628
1629 static struct clk_branch pcie1_a_clk = {
1630 .halt_reg = 0x2fc0,
1631 .halt_bit = 10,
1632 .clkr = {
1633 .enable_reg = 0x3a80,
1634 .enable_mask = BIT(4),
1635 .hw.init = &(struct clk_init_data){
1636 .name = "pcie1_a_clk",
1637 .ops = &clk_branch_ops,
1638 },
1639 },
1640 };
1641
1642 static struct clk_branch pcie1_aux_clk = {
1643 .halt_reg = 0x2fdc,
1644 .halt_bit = 28,
1645 .clkr = {
1646 .enable_reg = 0x3a88,
1647 .enable_mask = BIT(4),
1648 .hw.init = &(struct clk_init_data){
1649 .name = "pcie1_aux_clk",
1650 .ops = &clk_branch_ops,
1651 },
1652 },
1653 };
1654
1655 static struct clk_branch pcie1_h_clk = {
1656 .halt_reg = 0x2fd4,
1657 .halt_bit = 9,
1658 .clkr = {
1659 .enable_reg = 0x3a8c,
1660 .enable_mask = BIT(4),
1661 .hw.init = &(struct clk_init_data){
1662 .name = "pcie1_h_clk",
1663 .ops = &clk_branch_ops,
1664 },
1665 },
1666 };
1667
1668 static struct clk_branch pcie1_phy_clk = {
1669 .halt_reg = 0x2fdc,
1670 .halt_bit = 26,
1671 .clkr = {
1672 .enable_reg = 0x3a90,
1673 .enable_mask = BIT(4),
1674 .hw.init = &(struct clk_init_data){
1675 .name = "pcie1_phy_clk",
1676 .ops = &clk_branch_ops,
1677 },
1678 },
1679 };
1680
1681 static struct clk_rcg pcie2_ref_src = {
1682 .ns_reg = 0x3ae0,
1683 .p = {
1684 .pre_div_shift = 3,
1685 .pre_div_width = 4,
1686 },
1687 .s = {
1688 .src_sel_shift = 0,
1689 .parent_map = gcc_pxo_pll3_map,
1690 },
1691 .freq_tbl = clk_tbl_pcie_ref,
1692 .clkr = {
1693 .enable_reg = 0x3ae0,
1694 .enable_mask = BIT(11),
1695 .hw.init = &(struct clk_init_data){
1696 .name = "pcie2_ref_src",
1697 .parent_names = gcc_pxo_pll3,
1698 .num_parents = 2,
1699 .ops = &clk_rcg_ops,
1700 .flags = CLK_SET_RATE_GATE,
1701 },
1702 },
1703 };
1704
1705 static struct clk_branch pcie2_ref_src_clk = {
1706 .halt_reg = 0x2fdc,
1707 .halt_bit = 24,
1708 .clkr = {
1709 .enable_reg = 0x3ae0,
1710 .enable_mask = BIT(9),
1711 .hw.init = &(struct clk_init_data){
1712 .name = "pcie2_ref_src_clk",
1713 .parent_names = (const char *[]){ "pcie2_ref_src" },
1714 .num_parents = 1,
1715 .ops = &clk_branch_ops,
1716 .flags = CLK_SET_RATE_PARENT,
1717 },
1718 },
1719 };
1720
1721 static struct clk_branch pcie2_a_clk = {
1722 .halt_reg = 0x2fc0,
1723 .halt_bit = 9,
1724 .clkr = {
1725 .enable_reg = 0x3ac0,
1726 .enable_mask = BIT(4),
1727 .hw.init = &(struct clk_init_data){
1728 .name = "pcie2_a_clk",
1729 .ops = &clk_branch_ops,
1730 },
1731 },
1732 };
1733
1734 static struct clk_branch pcie2_aux_clk = {
1735 .halt_reg = 0x2fdc,
1736 .halt_bit = 25,
1737 .clkr = {
1738 .enable_reg = 0x3ac8,
1739 .enable_mask = BIT(4),
1740 .hw.init = &(struct clk_init_data){
1741 .name = "pcie2_aux_clk",
1742 .ops = &clk_branch_ops,
1743 },
1744 },
1745 };
1746
1747 static struct clk_branch pcie2_h_clk = {
1748 .halt_reg = 0x2fd4,
1749 .halt_bit = 10,
1750 .clkr = {
1751 .enable_reg = 0x3acc,
1752 .enable_mask = BIT(4),
1753 .hw.init = &(struct clk_init_data){
1754 .name = "pcie2_h_clk",
1755 .ops = &clk_branch_ops,
1756 },
1757 },
1758 };
1759
1760 static struct clk_branch pcie2_phy_clk = {
1761 .halt_reg = 0x2fdc,
1762 .halt_bit = 23,
1763 .clkr = {
1764 .enable_reg = 0x3ad0,
1765 .enable_mask = BIT(4),
1766 .hw.init = &(struct clk_init_data){
1767 .name = "pcie2_phy_clk",
1768 .ops = &clk_branch_ops,
1769 },
1770 },
1771 };
1772
1773 static const struct freq_tbl clk_tbl_sata_ref[] = {
1774 { 100000000, P_PLL3, 12, 0, 0 },
1775 { }
1776 };
1777
1778 static struct clk_rcg sata_ref_src = {
1779 .ns_reg = 0x2c08,
1780 .p = {
1781 .pre_div_shift = 3,
1782 .pre_div_width = 4,
1783 },
1784 .s = {
1785 .src_sel_shift = 0,
1786 .parent_map = gcc_pxo_pll3_sata_map,
1787 },
1788 .freq_tbl = clk_tbl_sata_ref,
1789 .clkr = {
1790 .enable_reg = 0x2c08,
1791 .enable_mask = BIT(7),
1792 .hw.init = &(struct clk_init_data){
1793 .name = "sata_ref_src",
1794 .parent_names = gcc_pxo_pll3,
1795 .num_parents = 2,
1796 .ops = &clk_rcg_ops,
1797 .flags = CLK_SET_RATE_GATE,
1798 },
1799 },
1800 };
1801
1802 static struct clk_branch sata_rxoob_clk = {
1803 .halt_reg = 0x2fdc,
1804 .halt_bit = 20,
1805 .clkr = {
1806 .enable_reg = 0x2c0c,
1807 .enable_mask = BIT(4),
1808 .hw.init = &(struct clk_init_data){
1809 .name = "sata_rxoob_clk",
1810 .parent_names = (const char *[]){ "sata_ref_src" },
1811 .num_parents = 1,
1812 .ops = &clk_branch_ops,
1813 .flags = CLK_SET_RATE_PARENT,
1814 },
1815 },
1816 };
1817
1818 static struct clk_branch sata_pmalive_clk = {
1819 .halt_reg = 0x2fdc,
1820 .halt_bit = 19,
1821 .clkr = {
1822 .enable_reg = 0x2c10,
1823 .enable_mask = BIT(4),
1824 .hw.init = &(struct clk_init_data){
1825 .name = "sata_pmalive_clk",
1826 .parent_names = (const char *[]){ "sata_ref_src" },
1827 .num_parents = 1,
1828 .ops = &clk_branch_ops,
1829 .flags = CLK_SET_RATE_PARENT,
1830 },
1831 },
1832 };
1833
1834 static struct clk_branch sata_phy_ref_clk = {
1835 .halt_reg = 0x2fdc,
1836 .halt_bit = 18,
1837 .clkr = {
1838 .enable_reg = 0x2c14,
1839 .enable_mask = BIT(4),
1840 .hw.init = &(struct clk_init_data){
1841 .name = "sata_phy_ref_clk",
1842 .parent_names = (const char *[]){ "pxo" },
1843 .num_parents = 1,
1844 .ops = &clk_branch_ops,
1845 },
1846 },
1847 };
1848
1849 static struct clk_branch sata_a_clk = {
1850 .halt_reg = 0x2fc0,
1851 .halt_bit = 12,
1852 .clkr = {
1853 .enable_reg = 0x2c20,
1854 .enable_mask = BIT(4),
1855 .hw.init = &(struct clk_init_data){
1856 .name = "sata_a_clk",
1857 .ops = &clk_branch_ops,
1858 },
1859 },
1860 };
1861
1862 static struct clk_branch sata_h_clk = {
1863 .halt_reg = 0x2fdc,
1864 .halt_bit = 21,
1865 .clkr = {
1866 .enable_reg = 0x2c00,
1867 .enable_mask = BIT(4),
1868 .hw.init = &(struct clk_init_data){
1869 .name = "sata_h_clk",
1870 .ops = &clk_branch_ops,
1871 },
1872 },
1873 };
1874
1875 static struct clk_branch sfab_sata_s_h_clk = {
1876 .halt_reg = 0x2fc4,
1877 .halt_bit = 14,
1878 .clkr = {
1879 .enable_reg = 0x2480,
1880 .enable_mask = BIT(4),
1881 .hw.init = &(struct clk_init_data){
1882 .name = "sfab_sata_s_h_clk",
1883 .ops = &clk_branch_ops,
1884 },
1885 },
1886 };
1887
1888 static struct clk_branch sata_phy_cfg_clk = {
1889 .halt_reg = 0x2fcc,
1890 .halt_bit = 14,
1891 .clkr = {
1892 .enable_reg = 0x2c40,
1893 .enable_mask = BIT(4),
1894 .hw.init = &(struct clk_init_data){
1895 .name = "sata_phy_cfg_clk",
1896 .ops = &clk_branch_ops,
1897 },
1898 },
1899 };
1900
1901 static const struct freq_tbl clk_tbl_usb30_master[] = {
1902 { 125000000, P_PLL0, 1, 5, 32 },
1903 { }
1904 };
1905
1906 static struct clk_rcg usb30_master_clk_src = {
1907 .ns_reg = 0x3b2c,
1908 .md_reg = 0x3b28,
1909 .mn = {
1910 .mnctr_en_bit = 8,
1911 .mnctr_reset_bit = 7,
1912 .mnctr_mode_shift = 5,
1913 .n_val_shift = 16,
1914 .m_val_shift = 16,
1915 .width = 8,
1916 },
1917 .p = {
1918 .pre_div_shift = 3,
1919 .pre_div_width = 2,
1920 },
1921 .s = {
1922 .src_sel_shift = 0,
1923 .parent_map = gcc_pxo_pll8_pll0,
1924 },
1925 .freq_tbl = clk_tbl_usb30_master,
1926 .clkr = {
1927 .enable_reg = 0x3b2c,
1928 .enable_mask = BIT(11),
1929 .hw.init = &(struct clk_init_data){
1930 .name = "usb30_master_ref_src",
1931 .parent_names = gcc_pxo_pll8_pll0_map,
1932 .num_parents = 3,
1933 .ops = &clk_rcg_ops,
1934 .flags = CLK_SET_RATE_GATE,
1935 },
1936 },
1937 };
1938
1939 static struct clk_branch usb30_0_branch_clk = {
1940 .halt_reg = 0x2fc4,
1941 .halt_bit = 22,
1942 .clkr = {
1943 .enable_reg = 0x3b24,
1944 .enable_mask = BIT(4),
1945 .hw.init = &(struct clk_init_data){
1946 .name = "usb30_0_branch_clk",
1947 .parent_names = (const char *[]){ "usb30_master_ref_src", },
1948 .num_parents = 1,
1949 .ops = &clk_branch_ops,
1950 .flags = CLK_SET_RATE_PARENT,
1951 },
1952 },
1953 };
1954
1955 static struct clk_branch usb30_1_branch_clk = {
1956 .halt_reg = 0x2fc4,
1957 .halt_bit = 17,
1958 .clkr = {
1959 .enable_reg = 0x3b34,
1960 .enable_mask = BIT(4),
1961 .hw.init = &(struct clk_init_data){
1962 .name = "usb30_1_branch_clk",
1963 .parent_names = (const char *[]){ "usb30_master_ref_src", },
1964 .num_parents = 1,
1965 .ops = &clk_branch_ops,
1966 .flags = CLK_SET_RATE_PARENT,
1967 },
1968 },
1969 };
1970
1971 static const struct freq_tbl clk_tbl_usb30_utmi[] = {
1972 { 60000000, P_PLL8, 1, 5, 32 },
1973 { }
1974 };
1975
1976 static struct clk_rcg usb30_utmi_clk = {
1977 .ns_reg = 0x3b44,
1978 .md_reg = 0x3b40,
1979 .mn = {
1980 .mnctr_en_bit = 8,
1981 .mnctr_reset_bit = 7,
1982 .mnctr_mode_shift = 5,
1983 .n_val_shift = 16,
1984 .m_val_shift = 16,
1985 .width = 8,
1986 },
1987 .p = {
1988 .pre_div_shift = 3,
1989 .pre_div_width = 2,
1990 },
1991 .s = {
1992 .src_sel_shift = 0,
1993 .parent_map = gcc_pxo_pll8_pll0,
1994 },
1995 .freq_tbl = clk_tbl_usb30_utmi,
1996 .clkr = {
1997 .enable_reg = 0x3b44,
1998 .enable_mask = BIT(11),
1999 .hw.init = &(struct clk_init_data){
2000 .name = "usb30_utmi_clk",
2001 .parent_names = gcc_pxo_pll8_pll0_map,
2002 .num_parents = 3,
2003 .ops = &clk_rcg_ops,
2004 .flags = CLK_SET_RATE_GATE,
2005 },
2006 },
2007 };
2008
2009 static struct clk_branch usb30_0_utmi_clk_ctl = {
2010 .halt_reg = 0x2fc4,
2011 .halt_bit = 21,
2012 .clkr = {
2013 .enable_reg = 0x3b48,
2014 .enable_mask = BIT(4),
2015 .hw.init = &(struct clk_init_data){
2016 .name = "usb30_0_utmi_clk_ctl",
2017 .parent_names = (const char *[]){ "usb30_utmi_clk", },
2018 .num_parents = 1,
2019 .ops = &clk_branch_ops,
2020 .flags = CLK_SET_RATE_PARENT,
2021 },
2022 },
2023 };
2024
2025 static struct clk_branch usb30_1_utmi_clk_ctl = {
2026 .halt_reg = 0x2fc4,
2027 .halt_bit = 15,
2028 .clkr = {
2029 .enable_reg = 0x3b4c,
2030 .enable_mask = BIT(4),
2031 .hw.init = &(struct clk_init_data){
2032 .name = "usb30_1_utmi_clk_ctl",
2033 .parent_names = (const char *[]){ "usb30_utmi_clk", },
2034 .num_parents = 1,
2035 .ops = &clk_branch_ops,
2036 .flags = CLK_SET_RATE_PARENT,
2037 },
2038 },
2039 };
2040
2041 static const struct freq_tbl clk_tbl_usb[] = {
2042 { 60000000, P_PLL8, 1, 5, 32 },
2043 { }
2044 };
2045
2046 static struct clk_rcg usb_hs1_xcvr_clk_src = {
2047 .ns_reg = 0x290C,
2048 .md_reg = 0x2908,
2049 .mn = {
2050 .mnctr_en_bit = 8,
2051 .mnctr_reset_bit = 7,
2052 .mnctr_mode_shift = 5,
2053 .n_val_shift = 16,
2054 .m_val_shift = 16,
2055 .width = 8,
2056 },
2057 .p = {
2058 .pre_div_shift = 3,
2059 .pre_div_width = 2,
2060 },
2061 .s = {
2062 .src_sel_shift = 0,
2063 .parent_map = gcc_pxo_pll8_pll0,
2064 },
2065 .freq_tbl = clk_tbl_usb,
2066 .clkr = {
2067 .enable_reg = 0x2968,
2068 .enable_mask = BIT(11),
2069 .hw.init = &(struct clk_init_data){
2070 .name = "usb_hs1_xcvr_src",
2071 .parent_names = gcc_pxo_pll8_pll0_map,
2072 .num_parents = 3,
2073 .ops = &clk_rcg_ops,
2074 .flags = CLK_SET_RATE_GATE,
2075 },
2076 },
2077 };
2078
2079 static struct clk_branch usb_hs1_xcvr_clk = {
2080 .halt_reg = 0x2fcc,
2081 .halt_bit = 17,
2082 .clkr = {
2083 .enable_reg = 0x290c,
2084 .enable_mask = BIT(9),
2085 .hw.init = &(struct clk_init_data){
2086 .name = "usb_hs1_xcvr_clk",
2087 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
2088 .num_parents = 1,
2089 .ops = &clk_branch_ops,
2090 .flags = CLK_SET_RATE_PARENT,
2091 },
2092 },
2093 };
2094
2095 static struct clk_branch usb_hs1_h_clk = {
2096 .hwcg_reg = 0x2900,
2097 .hwcg_bit = 6,
2098 .halt_reg = 0x2fc8,
2099 .halt_bit = 1,
2100 .clkr = {
2101 .enable_reg = 0x2900,
2102 .enable_mask = BIT(4),
2103 .hw.init = &(struct clk_init_data){
2104 .name = "usb_hs1_h_clk",
2105 .ops = &clk_branch_ops,
2106 },
2107 },
2108 };
2109
2110 static struct clk_rcg usb_fs1_xcvr_clk_src = {
2111 .ns_reg = 0x2968,
2112 .md_reg = 0x2964,
2113 .mn = {
2114 .mnctr_en_bit = 8,
2115 .mnctr_reset_bit = 7,
2116 .mnctr_mode_shift = 5,
2117 .n_val_shift = 16,
2118 .m_val_shift = 16,
2119 .width = 8,
2120 },
2121 .p = {
2122 .pre_div_shift = 3,
2123 .pre_div_width = 2,
2124 },
2125 .s = {
2126 .src_sel_shift = 0,
2127 .parent_map = gcc_pxo_pll8_pll0,
2128 },
2129 .freq_tbl = clk_tbl_usb,
2130 .clkr = {
2131 .enable_reg = 0x2968,
2132 .enable_mask = BIT(11),
2133 .hw.init = &(struct clk_init_data){
2134 .name = "usb_fs1_xcvr_src",
2135 .parent_names = gcc_pxo_pll8_pll0_map,
2136 .num_parents = 3,
2137 .ops = &clk_rcg_ops,
2138 .flags = CLK_SET_RATE_GATE,
2139 },
2140 },
2141 };
2142
2143 static struct clk_branch usb_fs1_xcvr_clk = {
2144 .halt_reg = 0x2fcc,
2145 .halt_bit = 17,
2146 .clkr = {
2147 .enable_reg = 0x2968,
2148 .enable_mask = BIT(9),
2149 .hw.init = &(struct clk_init_data){
2150 .name = "usb_fs1_xcvr_clk",
2151 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2152 .num_parents = 1,
2153 .ops = &clk_branch_ops,
2154 .flags = CLK_SET_RATE_PARENT,
2155 },
2156 },
2157 };
2158
2159 static struct clk_branch usb_fs1_sys_clk = {
2160 .halt_reg = 0x2fcc,
2161 .halt_bit = 18,
2162 .clkr = {
2163 .enable_reg = 0x296c,
2164 .enable_mask = BIT(4),
2165 .hw.init = &(struct clk_init_data){
2166 .name = "usb_fs1_sys_clk",
2167 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2168 .num_parents = 1,
2169 .ops = &clk_branch_ops,
2170 .flags = CLK_SET_RATE_PARENT,
2171 },
2172 },
2173 };
2174
2175 static struct clk_branch usb_fs1_h_clk = {
2176 .halt_reg = 0x2fcc,
2177 .halt_bit = 19,
2178 .clkr = {
2179 .enable_reg = 0x2960,
2180 .enable_mask = BIT(4),
2181 .hw.init = &(struct clk_init_data){
2182 .name = "usb_fs1_h_clk",
2183 .ops = &clk_branch_ops,
2184 },
2185 },
2186 };
2187
2188 static struct clk_branch ebi2_clk = {
2189 .hwcg_reg = 0x3b00,
2190 .hwcg_bit = 6,
2191 .halt_reg = 0x2fcc,
2192 .halt_bit = 1,
2193 .clkr = {
2194 .enable_reg = 0x3b00,
2195 .enable_mask = BIT(4),
2196 .hw.init = &(struct clk_init_data){
2197 .name = "ebi2_clk",
2198 .ops = &clk_branch_ops,
2199 },
2200 },
2201 };
2202
2203 static struct clk_branch ebi2_aon_clk = {
2204 .halt_reg = 0x2fcc,
2205 .halt_bit = 0,
2206 .clkr = {
2207 .enable_reg = 0x3b00,
2208 .enable_mask = BIT(8),
2209 .hw.init = &(struct clk_init_data){
2210 .name = "ebi2_always_on_clk",
2211 .ops = &clk_branch_ops,
2212 },
2213 },
2214 };
2215
2216 static const struct freq_tbl clk_tbl_gmac[] = {
2217 { 133000000, P_PLL0, 1, 50, 301 },
2218 { 266000000, P_PLL0, 1, 127, 382 },
2219 { }
2220 };
2221
2222 static struct clk_dyn_rcg gmac_core1_src = {
2223 .ns_reg[0] = 0x3cac,
2224 .ns_reg[1] = 0x3cb0,
2225 .md_reg[0] = 0x3ca4,
2226 .md_reg[1] = 0x3ca8,
2227 .bank_reg = 0x3ca0,
2228 .mn[0] = {
2229 .mnctr_en_bit = 8,
2230 .mnctr_reset_bit = 7,
2231 .mnctr_mode_shift = 5,
2232 .n_val_shift = 16,
2233 .m_val_shift = 16,
2234 .width = 8,
2235 },
2236 .mn[1] = {
2237 .mnctr_en_bit = 8,
2238 .mnctr_reset_bit = 7,
2239 .mnctr_mode_shift = 5,
2240 .n_val_shift = 16,
2241 .m_val_shift = 16,
2242 .width = 8,
2243 },
2244 .s[0] = {
2245 .src_sel_shift = 0,
2246 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2247 },
2248 .s[1] = {
2249 .src_sel_shift = 0,
2250 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2251 },
2252 .p[0] = {
2253 .pre_div_shift = 3,
2254 .pre_div_width = 2,
2255 },
2256 .p[1] = {
2257 .pre_div_shift = 3,
2258 .pre_div_width = 2,
2259 },
2260 .mux_sel_bit = 0,
2261 .freq_tbl = clk_tbl_gmac,
2262 .clkr = {
2263 .enable_reg = 0x3ca0,
2264 .enable_mask = BIT(1),
2265 .hw.init = &(struct clk_init_data){
2266 .name = "gmac_core1_src",
2267 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2268 .num_parents = 5,
2269 .ops = &clk_dyn_rcg_ops,
2270 },
2271 },
2272 };
2273
2274 static struct clk_branch gmac_core1_clk = {
2275 .halt_reg = 0x3c20,
2276 .halt_bit = 4,
2277 .hwcg_reg = 0x3cb4,
2278 .hwcg_bit = 6,
2279 .clkr = {
2280 .enable_reg = 0x3cb4,
2281 .enable_mask = BIT(4),
2282 .hw.init = &(struct clk_init_data){
2283 .name = "gmac_core1_clk",
2284 .parent_names = (const char *[]){
2285 "gmac_core1_src",
2286 },
2287 .num_parents = 1,
2288 .ops = &clk_branch_ops,
2289 .flags = CLK_SET_RATE_PARENT,
2290 },
2291 },
2292 };
2293
2294 static struct clk_dyn_rcg gmac_core2_src = {
2295 .ns_reg[0] = 0x3ccc,
2296 .ns_reg[1] = 0x3cd0,
2297 .md_reg[0] = 0x3cc4,
2298 .md_reg[1] = 0x3cc8,
2299 .bank_reg = 0x3ca0,
2300 .mn[0] = {
2301 .mnctr_en_bit = 8,
2302 .mnctr_reset_bit = 7,
2303 .mnctr_mode_shift = 5,
2304 .n_val_shift = 16,
2305 .m_val_shift = 16,
2306 .width = 8,
2307 },
2308 .mn[1] = {
2309 .mnctr_en_bit = 8,
2310 .mnctr_reset_bit = 7,
2311 .mnctr_mode_shift = 5,
2312 .n_val_shift = 16,
2313 .m_val_shift = 16,
2314 .width = 8,
2315 },
2316 .s[0] = {
2317 .src_sel_shift = 0,
2318 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2319 },
2320 .s[1] = {
2321 .src_sel_shift = 0,
2322 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2323 },
2324 .p[0] = {
2325 .pre_div_shift = 3,
2326 .pre_div_width = 2,
2327 },
2328 .p[1] = {
2329 .pre_div_shift = 3,
2330 .pre_div_width = 2,
2331 },
2332 .mux_sel_bit = 0,
2333 .freq_tbl = clk_tbl_gmac,
2334 .clkr = {
2335 .enable_reg = 0x3cc0,
2336 .enable_mask = BIT(1),
2337 .hw.init = &(struct clk_init_data){
2338 .name = "gmac_core2_src",
2339 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2340 .num_parents = 5,
2341 .ops = &clk_dyn_rcg_ops,
2342 },
2343 },
2344 };
2345
2346 static struct clk_branch gmac_core2_clk = {
2347 .halt_reg = 0x3c20,
2348 .halt_bit = 5,
2349 .hwcg_reg = 0x3cd4,
2350 .hwcg_bit = 6,
2351 .clkr = {
2352 .enable_reg = 0x3cd4,
2353 .enable_mask = BIT(4),
2354 .hw.init = &(struct clk_init_data){
2355 .name = "gmac_core2_clk",
2356 .parent_names = (const char *[]){
2357 "gmac_core2_src",
2358 },
2359 .num_parents = 1,
2360 .ops = &clk_branch_ops,
2361 .flags = CLK_SET_RATE_PARENT,
2362 },
2363 },
2364 };
2365
2366 static struct clk_dyn_rcg gmac_core3_src = {
2367 .ns_reg[0] = 0x3cec,
2368 .ns_reg[1] = 0x3cf0,
2369 .md_reg[0] = 0x3ce4,
2370 .md_reg[1] = 0x3ce8,
2371 .bank_reg = 0x3ce0,
2372 .mn[0] = {
2373 .mnctr_en_bit = 8,
2374 .mnctr_reset_bit = 7,
2375 .mnctr_mode_shift = 5,
2376 .n_val_shift = 16,
2377 .m_val_shift = 16,
2378 .width = 8,
2379 },
2380 .mn[1] = {
2381 .mnctr_en_bit = 8,
2382 .mnctr_reset_bit = 7,
2383 .mnctr_mode_shift = 5,
2384 .n_val_shift = 16,
2385 .m_val_shift = 16,
2386 .width = 8,
2387 },
2388 .s[0] = {
2389 .src_sel_shift = 0,
2390 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2391 },
2392 .s[1] = {
2393 .src_sel_shift = 0,
2394 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2395 },
2396 .p[0] = {
2397 .pre_div_shift = 3,
2398 .pre_div_width = 2,
2399 },
2400 .p[1] = {
2401 .pre_div_shift = 3,
2402 .pre_div_width = 2,
2403 },
2404 .mux_sel_bit = 0,
2405 .freq_tbl = clk_tbl_gmac,
2406 .clkr = {
2407 .enable_reg = 0x3ce0,
2408 .enable_mask = BIT(1),
2409 .hw.init = &(struct clk_init_data){
2410 .name = "gmac_core3_src",
2411 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2412 .num_parents = 5,
2413 .ops = &clk_dyn_rcg_ops,
2414 },
2415 },
2416 };
2417
2418 static struct clk_branch gmac_core3_clk = {
2419 .halt_reg = 0x3c20,
2420 .halt_bit = 6,
2421 .hwcg_reg = 0x3cf4,
2422 .hwcg_bit = 6,
2423 .clkr = {
2424 .enable_reg = 0x3cf4,
2425 .enable_mask = BIT(4),
2426 .hw.init = &(struct clk_init_data){
2427 .name = "gmac_core3_clk",
2428 .parent_names = (const char *[]){
2429 "gmac_core3_src",
2430 },
2431 .num_parents = 1,
2432 .ops = &clk_branch_ops,
2433 .flags = CLK_SET_RATE_PARENT,
2434 },
2435 },
2436 };
2437
2438 static struct clk_dyn_rcg gmac_core4_src = {
2439 .ns_reg[0] = 0x3d0c,
2440 .ns_reg[1] = 0x3d10,
2441 .md_reg[0] = 0x3d04,
2442 .md_reg[1] = 0x3d08,
2443 .bank_reg = 0x3d00,
2444 .mn[0] = {
2445 .mnctr_en_bit = 8,
2446 .mnctr_reset_bit = 7,
2447 .mnctr_mode_shift = 5,
2448 .n_val_shift = 16,
2449 .m_val_shift = 16,
2450 .width = 8,
2451 },
2452 .mn[1] = {
2453 .mnctr_en_bit = 8,
2454 .mnctr_reset_bit = 7,
2455 .mnctr_mode_shift = 5,
2456 .n_val_shift = 16,
2457 .m_val_shift = 16,
2458 .width = 8,
2459 },
2460 .s[0] = {
2461 .src_sel_shift = 0,
2462 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2463 },
2464 .s[1] = {
2465 .src_sel_shift = 0,
2466 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2467 },
2468 .p[0] = {
2469 .pre_div_shift = 3,
2470 .pre_div_width = 2,
2471 },
2472 .p[1] = {
2473 .pre_div_shift = 3,
2474 .pre_div_width = 2,
2475 },
2476 .mux_sel_bit = 0,
2477 .freq_tbl = clk_tbl_gmac,
2478 .clkr = {
2479 .enable_reg = 0x3d00,
2480 .enable_mask = BIT(1),
2481 .hw.init = &(struct clk_init_data){
2482 .name = "gmac_core4_src",
2483 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2484 .num_parents = 5,
2485 .ops = &clk_dyn_rcg_ops,
2486 },
2487 },
2488 };
2489
2490 static struct clk_branch gmac_core4_clk = {
2491 .halt_reg = 0x3c20,
2492 .halt_bit = 7,
2493 .hwcg_reg = 0x3d14,
2494 .hwcg_bit = 6,
2495 .clkr = {
2496 .enable_reg = 0x3d14,
2497 .enable_mask = BIT(4),
2498 .hw.init = &(struct clk_init_data){
2499 .name = "gmac_core4_clk",
2500 .parent_names = (const char *[]){
2501 "gmac_core4_src",
2502 },
2503 .num_parents = 1,
2504 .ops = &clk_branch_ops,
2505 .flags = CLK_SET_RATE_PARENT,
2506 },
2507 },
2508 };
2509
2510 static const struct freq_tbl clk_tbl_nss_tcm[] = {
2511 { 266000000, P_PLL0, 3, 0, 0 },
2512 { 400000000, P_PLL0, 2, 0, 0 },
2513 { }
2514 };
2515
2516 static struct clk_dyn_rcg nss_tcm_src = {
2517 .ns_reg[0] = 0x3dc4,
2518 .ns_reg[1] = 0x3dc8,
2519 .bank_reg = 0x3dc0,
2520 .s[0] = {
2521 .src_sel_shift = 0,
2522 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2523 },
2524 .s[1] = {
2525 .src_sel_shift = 0,
2526 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2527 },
2528 .p[0] = {
2529 .pre_div_shift = 3,
2530 .pre_div_width = 4,
2531 },
2532 .p[1] = {
2533 .pre_div_shift = 3,
2534 .pre_div_width = 4,
2535 },
2536 .mux_sel_bit = 0,
2537 .freq_tbl = clk_tbl_nss_tcm,
2538 .clkr = {
2539 .enable_reg = 0x3dc0,
2540 .enable_mask = BIT(1),
2541 .hw.init = &(struct clk_init_data){
2542 .name = "nss_tcm_src",
2543 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2544 .num_parents = 5,
2545 .ops = &clk_dyn_rcg_ops,
2546 },
2547 },
2548 };
2549
2550 static struct clk_branch nss_tcm_clk = {
2551 .halt_reg = 0x3c20,
2552 .halt_bit = 14,
2553 .clkr = {
2554 .enable_reg = 0x3dd0,
2555 .enable_mask = BIT(6) | BIT(4),
2556 .hw.init = &(struct clk_init_data){
2557 .name = "nss_tcm_clk",
2558 .parent_names = (const char *[]){
2559 "nss_tcm_src",
2560 },
2561 .num_parents = 1,
2562 .ops = &clk_branch_ops,
2563 .flags = CLK_SET_RATE_PARENT,
2564 },
2565 },
2566 };
2567
2568 static const struct freq_tbl clk_tbl_nss[] = {
2569 { 110000000, P_PLL18, 1, 1, 5 },
2570 { 275000000, P_PLL18, 2, 0, 0 },
2571 { 550000000, P_PLL18, 1, 0, 0 },
2572 { 733000000, P_PLL18, 1, 0, 0 },
2573 { }
2574 };
2575
2576 static struct clk_dyn_rcg ubi32_core1_src_clk = {
2577 .ns_reg[0] = 0x3d2c,
2578 .ns_reg[1] = 0x3d30,
2579 .md_reg[0] = 0x3d24,
2580 .md_reg[1] = 0x3d28,
2581 .bank_reg = 0x3d20,
2582 .mn[0] = {
2583 .mnctr_en_bit = 8,
2584 .mnctr_reset_bit = 7,
2585 .mnctr_mode_shift = 5,
2586 .n_val_shift = 16,
2587 .m_val_shift = 16,
2588 .width = 8,
2589 },
2590 .mn[1] = {
2591 .mnctr_en_bit = 8,
2592 .mnctr_reset_bit = 7,
2593 .mnctr_mode_shift = 5,
2594 .n_val_shift = 16,
2595 .m_val_shift = 16,
2596 .width = 8,
2597 },
2598 .s[0] = {
2599 .src_sel_shift = 0,
2600 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2601 },
2602 .s[1] = {
2603 .src_sel_shift = 0,
2604 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2605 },
2606 .p[0] = {
2607 .pre_div_shift = 3,
2608 .pre_div_width = 2,
2609 },
2610 .p[1] = {
2611 .pre_div_shift = 3,
2612 .pre_div_width = 2,
2613 },
2614 .mux_sel_bit = 0,
2615 .freq_tbl = clk_tbl_nss,
2616 .clkr = {
2617 .enable_reg = 0x3d20,
2618 .enable_mask = BIT(1),
2619 .hw.init = &(struct clk_init_data){
2620 .name = "ubi32_core1_src_clk",
2621 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2622 .num_parents = 5,
2623 .ops = &clk_dyn_rcg_ops,
2624 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2625 },
2626 },
2627 };
2628
2629 static struct clk_dyn_rcg ubi32_core2_src_clk = {
2630 .ns_reg[0] = 0x3d4c,
2631 .ns_reg[1] = 0x3d50,
2632 .md_reg[0] = 0x3d44,
2633 .md_reg[1] = 0x3d48,
2634 .bank_reg = 0x3d40,
2635 .mn[0] = {
2636 .mnctr_en_bit = 8,
2637 .mnctr_reset_bit = 7,
2638 .mnctr_mode_shift = 5,
2639 .n_val_shift = 16,
2640 .m_val_shift = 16,
2641 .width = 8,
2642 },
2643 .mn[1] = {
2644 .mnctr_en_bit = 8,
2645 .mnctr_reset_bit = 7,
2646 .mnctr_mode_shift = 5,
2647 .n_val_shift = 16,
2648 .m_val_shift = 16,
2649 .width = 8,
2650 },
2651 .s[0] = {
2652 .src_sel_shift = 0,
2653 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2654 },
2655 .s[1] = {
2656 .src_sel_shift = 0,
2657 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2658 },
2659 .p[0] = {
2660 .pre_div_shift = 3,
2661 .pre_div_width = 2,
2662 },
2663 .p[1] = {
2664 .pre_div_shift = 3,
2665 .pre_div_width = 2,
2666 },
2667 .mux_sel_bit = 0,
2668 .freq_tbl = clk_tbl_nss,
2669 .clkr = {
2670 .enable_reg = 0x3d40,
2671 .enable_mask = BIT(1),
2672 .hw.init = &(struct clk_init_data){
2673 .name = "ubi32_core2_src_clk",
2674 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2675 .num_parents = 5,
2676 .ops = &clk_dyn_rcg_ops,
2677 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2678 },
2679 },
2680 };
2681
2682 static struct clk_regmap *gcc_ipq806x_clks[] = {
2683 [PLL0] = &pll0.clkr,
2684 [PLL0_VOTE] = &pll0_vote,
2685 [PLL3] = &pll3.clkr,
2686 [PLL4_VOTE] = &pll4_vote,
2687 [PLL8] = &pll8.clkr,
2688 [PLL8_VOTE] = &pll8_vote,
2689 [PLL14] = &pll14.clkr,
2690 [PLL14_VOTE] = &pll14_vote,
2691 [PLL18] = &pll18.clkr,
2692 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2693 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2694 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2695 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2696 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2697 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2698 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2699 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2700 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2701 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2702 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2703 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2704 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2705 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2706 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2707 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2708 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2709 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2710 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2711 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2712 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2713 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2714 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2715 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2716 [GP0_SRC] = &gp0_src.clkr,
2717 [GP0_CLK] = &gp0_clk.clkr,
2718 [GP1_SRC] = &gp1_src.clkr,
2719 [GP1_CLK] = &gp1_clk.clkr,
2720 [GP2_SRC] = &gp2_src.clkr,
2721 [GP2_CLK] = &gp2_clk.clkr,
2722 [PMEM_A_CLK] = &pmem_clk.clkr,
2723 [PRNG_SRC] = &prng_src.clkr,
2724 [PRNG_CLK] = &prng_clk.clkr,
2725 [SDC1_SRC] = &sdc1_src.clkr,
2726 [SDC1_CLK] = &sdc1_clk.clkr,
2727 [SDC3_SRC] = &sdc3_src.clkr,
2728 [SDC3_CLK] = &sdc3_clk.clkr,
2729 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
2730 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2731 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
2732 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2733 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2734 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2735 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2736 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2737 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2738 [TSIF_H_CLK] = &tsif_h_clk.clkr,
2739 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2740 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2741 [ADM0_CLK] = &adm0_clk.clkr,
2742 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2743 [PCIE_A_CLK] = &pcie_a_clk.clkr,
2744 [PCIE_AUX_CLK] = &pcie_aux_clk.clkr,
2745 [PCIE_H_CLK] = &pcie_h_clk.clkr,
2746 [PCIE_PHY_CLK] = &pcie_phy_clk.clkr,
2747 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
2748 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2749 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2750 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2751 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2752 [SATA_H_CLK] = &sata_h_clk.clkr,
2753 [SATA_CLK_SRC] = &sata_ref_src.clkr,
2754 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
2755 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
2756 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
2757 [SATA_A_CLK] = &sata_a_clk.clkr,
2758 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
2759 [PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr,
2760 [PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr,
2761 [PCIE_1_A_CLK] = &pcie1_a_clk.clkr,
2762 [PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr,
2763 [PCIE_1_H_CLK] = &pcie1_h_clk.clkr,
2764 [PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr,
2765 [PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr,
2766 [PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr,
2767 [PCIE_2_A_CLK] = &pcie2_a_clk.clkr,
2768 [PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr,
2769 [PCIE_2_H_CLK] = &pcie2_h_clk.clkr,
2770 [PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr,
2771 [PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr,
2772 [PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr,
2773 [USB30_MASTER_SRC] = &usb30_master_clk_src.clkr,
2774 [USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr,
2775 [USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr,
2776 [USB30_UTMI_SRC] = &usb30_utmi_clk.clkr,
2777 [USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr,
2778 [USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr,
2779 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2780 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr,
2781 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2782 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2783 [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
2784 [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
2785 [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
2786 [EBI2_CLK] = &ebi2_clk.clkr,
2787 [EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
2788 [GMAC_CORE1_CLK_SRC] = &gmac_core1_src.clkr,
2789 [GMAC_CORE1_CLK] = &gmac_core1_clk.clkr,
2790 [GMAC_CORE2_CLK_SRC] = &gmac_core2_src.clkr,
2791 [GMAC_CORE2_CLK] = &gmac_core2_clk.clkr,
2792 [GMAC_CORE3_CLK_SRC] = &gmac_core3_src.clkr,
2793 [GMAC_CORE3_CLK] = &gmac_core3_clk.clkr,
2794 [GMAC_CORE4_CLK_SRC] = &gmac_core4_src.clkr,
2795 [GMAC_CORE4_CLK] = &gmac_core4_clk.clkr,
2796 [UBI32_CORE1_CLK_SRC] = &ubi32_core1_src_clk.clkr,
2797 [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
2798 [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
2799 [NSSTCM_CLK] = &nss_tcm_clk.clkr,
2800 };
2801
2802 static const struct qcom_reset_map gcc_ipq806x_resets[] = {
2803 [QDSS_STM_RESET] = { 0x2060, 6 },
2804 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2805 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2806 [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 },
2807 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
2808 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 },
2809 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2810 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2811 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
2812 [ADM0_C2_RESET] = { 0x220c, 4 },
2813 [ADM0_C1_RESET] = { 0x220c, 3 },
2814 [ADM0_C0_RESET] = { 0x220c, 2 },
2815 [ADM0_PBUS_RESET] = { 0x220c, 1 },
2816 [ADM0_RESET] = { 0x220c, 0 },
2817 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
2818 [QDSS_POR_RESET] = { 0x2260, 4 },
2819 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
2820 [QDSS_HRESET_RESET] = { 0x2260, 2 },
2821 [QDSS_AXI_RESET] = { 0x2260, 1 },
2822 [QDSS_DBG_RESET] = { 0x2260, 0 },
2823 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
2824 [SFAB_PCIE_S_RESET] = { 0x22d8, 0 },
2825 [PCIE_EXT_RESET] = { 0x22dc, 6 },
2826 [PCIE_PHY_RESET] = { 0x22dc, 5 },
2827 [PCIE_PCI_RESET] = { 0x22dc, 4 },
2828 [PCIE_POR_RESET] = { 0x22dc, 3 },
2829 [PCIE_HCLK_RESET] = { 0x22dc, 2 },
2830 [PCIE_ACLK_RESET] = { 0x22dc, 0 },
2831 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
2832 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2833 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2834 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2835 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
2836 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2837 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2838 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2839 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2840 [DFAB_ARB0_RESET] = { 0x2560, 7 },
2841 [DFAB_ARB1_RESET] = { 0x2564, 7 },
2842 [PPSS_PROC_RESET] = { 0x2594, 1 },
2843 [PPSS_RESET] = { 0x2594, 0 },
2844 [DMA_BAM_RESET] = { 0x25c0, 7 },
2845 [SPS_TIC_H_RESET] = { 0x2600, 7 },
2846 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2847 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2848 [TSIF_H_RESET] = { 0x2700, 7 },
2849 [CE1_H_RESET] = { 0x2720, 7 },
2850 [CE1_CORE_RESET] = { 0x2724, 7 },
2851 [CE1_SLEEP_RESET] = { 0x2728, 7 },
2852 [CE2_H_RESET] = { 0x2740, 7 },
2853 [CE2_CORE_RESET] = { 0x2744, 7 },
2854 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2855 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2856 [RPM_PROC_RESET] = { 0x27c0, 7 },
2857 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
2858 [SDC1_RESET] = { 0x2830, 0 },
2859 [SDC2_RESET] = { 0x2850, 0 },
2860 [SDC3_RESET] = { 0x2870, 0 },
2861 [SDC4_RESET] = { 0x2890, 0 },
2862 [USB_HS1_RESET] = { 0x2910, 0 },
2863 [USB_HSIC_RESET] = { 0x2934, 0 },
2864 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2865 [USB_FS1_RESET] = { 0x2974, 0 },
2866 [GSBI1_RESET] = { 0x29dc, 0 },
2867 [GSBI2_RESET] = { 0x29fc, 0 },
2868 [GSBI3_RESET] = { 0x2a1c, 0 },
2869 [GSBI4_RESET] = { 0x2a3c, 0 },
2870 [GSBI5_RESET] = { 0x2a5c, 0 },
2871 [GSBI6_RESET] = { 0x2a7c, 0 },
2872 [GSBI7_RESET] = { 0x2a9c, 0 },
2873 [SPDM_RESET] = { 0x2b6c, 0 },
2874 [SEC_CTRL_RESET] = { 0x2b80, 7 },
2875 [TLMM_H_RESET] = { 0x2ba0, 7 },
2876 [SFAB_SATA_M_RESET] = { 0x2c18, 0 },
2877 [SATA_RESET] = { 0x2c1c, 0 },
2878 [TSSC_RESET] = { 0x2ca0, 7 },
2879 [PDM_RESET] = { 0x2cc0, 12 },
2880 [MPM_H_RESET] = { 0x2da0, 7 },
2881 [MPM_RESET] = { 0x2da4, 0 },
2882 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2883 [PRNG_RESET] = { 0x2e80, 12 },
2884 [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
2885 [SFAB_CE3_S_RESET] = { 0x36c8, 0 },
2886 [CE3_SLEEP_RESET] = { 0x36d0, 7 },
2887 [PCIE_1_M_RESET] = { 0x3a98, 1 },
2888 [PCIE_1_S_RESET] = { 0x3a98, 0 },
2889 [PCIE_1_EXT_RESET] = { 0x3a9c, 6 },
2890 [PCIE_1_PHY_RESET] = { 0x3a9c, 5 },
2891 [PCIE_1_PCI_RESET] = { 0x3a9c, 4 },
2892 [PCIE_1_POR_RESET] = { 0x3a9c, 3 },
2893 [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 },
2894 [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 },
2895 [PCIE_2_M_RESET] = { 0x3ad8, 1 },
2896 [PCIE_2_S_RESET] = { 0x3ad8, 0 },
2897 [PCIE_2_EXT_RESET] = { 0x3adc, 6 },
2898 [PCIE_2_PHY_RESET] = { 0x3adc, 5 },
2899 [PCIE_2_PCI_RESET] = { 0x3adc, 4 },
2900 [PCIE_2_POR_RESET] = { 0x3adc, 3 },
2901 [PCIE_2_HCLK_RESET] = { 0x3adc, 2 },
2902 [PCIE_2_ACLK_RESET] = { 0x3adc, 0 },
2903 [SFAB_USB30_S_RESET] = { 0x3b54, 1 },
2904 [SFAB_USB30_M_RESET] = { 0x3b54, 0 },
2905 [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 },
2906 [USB30_0_MASTER_RESET] = { 0x3b50, 4 },
2907 [USB30_0_SLEEP_RESET] = { 0x3b50, 3 },
2908 [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 },
2909 [USB30_0_POWERON_RESET] = { 0x3b50, 1 },
2910 [USB30_0_PHY_RESET] = { 0x3b50, 0 },
2911 [USB30_1_MASTER_RESET] = { 0x3b58, 4 },
2912 [USB30_1_SLEEP_RESET] = { 0x3b58, 3 },
2913 [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 },
2914 [USB30_1_POWERON_RESET] = { 0x3b58, 1 },
2915 [USB30_1_PHY_RESET] = { 0x3b58, 0 },
2916 [NSSFB0_RESET] = { 0x3b60, 6 },
2917 [NSSFB1_RESET] = { 0x3b60, 7 },
2918 [UBI32_CORE1_CLKRST_CLAMP_RESET] = { 0x3d3c, 3},
2919 [UBI32_CORE1_CLAMP_RESET] = { 0x3d3c, 2 },
2920 [UBI32_CORE1_AHB_RESET] = { 0x3d3c, 1 },
2921 [UBI32_CORE1_AXI_RESET] = { 0x3d3c, 0 },
2922 [UBI32_CORE2_CLKRST_CLAMP_RESET] = { 0x3d5c, 3 },
2923 [UBI32_CORE2_CLAMP_RESET] = { 0x3d5c, 2 },
2924 [UBI32_CORE2_AHB_RESET] = { 0x3d5c, 1 },
2925 [UBI32_CORE2_AXI_RESET] = { 0x3d5c, 0 },
2926 [GMAC_CORE1_RESET] = { 0x3cbc, 0 },
2927 [GMAC_CORE2_RESET] = { 0x3cdc, 0 },
2928 [GMAC_CORE3_RESET] = { 0x3cfc, 0 },
2929 [GMAC_CORE4_RESET] = { 0x3d1c, 0 },
2930 [GMAC_AHB_RESET] = { 0x3e24, 0 },
2931 [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
2932 [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
2933 [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
2934 [NSS_CH0_HW_RST_RX_125M_N_RESET] = { 0x3b60, 3 },
2935 [NSS_CH0_RST_TX_125M_N_RESET] = { 0x3b60, 4 },
2936 [NSS_CH1_RST_RX_CLK_N_RESET] = { 0x3b60, 5 },
2937 [NSS_CH1_RST_TX_CLK_N_RESET] = { 0x3b60, 6 },
2938 [NSS_CH1_RST_RX_125M_N_RESET] = { 0x3b60, 7 },
2939 [NSS_CH1_HW_RST_RX_125M_N_RESET] = { 0x3b60, 8 },
2940 [NSS_CH1_RST_TX_125M_N_RESET] = { 0x3b60, 9 },
2941 [NSS_CH2_RST_RX_CLK_N_RESET] = { 0x3b60, 10 },
2942 [NSS_CH2_RST_TX_CLK_N_RESET] = { 0x3b60, 11 },
2943 [NSS_CH2_RST_RX_125M_N_RESET] = { 0x3b60, 12 },
2944 [NSS_CH2_HW_RST_RX_125M_N_RESET] = { 0x3b60, 13 },
2945 [NSS_CH2_RST_TX_125M_N_RESET] = { 0x3b60, 14 },
2946 [NSS_CH3_RST_RX_CLK_N_RESET] = { 0x3b60, 15 },
2947 [NSS_CH3_RST_TX_CLK_N_RESET] = { 0x3b60, 16 },
2948 [NSS_CH3_RST_RX_125M_N_RESET] = { 0x3b60, 17 },
2949 [NSS_CH3_HW_RST_RX_125M_N_RESET] = { 0x3b60, 18 },
2950 [NSS_CH3_RST_TX_125M_N_RESET] = { 0x3b60, 19 },
2951 [NSS_RST_RX_250M_125M_N_RESET] = { 0x3b60, 20 },
2952 [NSS_RST_TX_250M_125M_N_RESET] = { 0x3b60, 21 },
2953 [NSS_QSGMII_TXPI_RST_N_RESET] = { 0x3b60, 22 },
2954 [NSS_QSGMII_CDR_RST_N_RESET] = { 0x3b60, 23 },
2955 [NSS_SGMII2_CDR_RST_N_RESET] = { 0x3b60, 24 },
2956 [NSS_SGMII3_CDR_RST_N_RESET] = { 0x3b60, 25 },
2957 [NSS_CAL_PRBS_RST_N_RESET] = { 0x3b60, 26 },
2958 [NSS_LCKDT_RST_N_RESET] = { 0x3b60, 27 },
2959 [NSS_SRDS_N_RESET] = { 0x3b60, 28 },
2960 };
2961
2962 static const struct regmap_config gcc_ipq806x_regmap_config = {
2963 .reg_bits = 32,
2964 .reg_stride = 4,
2965 .val_bits = 32,
2966 .max_register = 0x3e40,
2967 .fast_io = true,
2968 };
2969
2970 static const struct qcom_cc_desc gcc_ipq806x_desc = {
2971 .config = &gcc_ipq806x_regmap_config,
2972 .clks = gcc_ipq806x_clks,
2973 .num_clks = ARRAY_SIZE(gcc_ipq806x_clks),
2974 .resets = gcc_ipq806x_resets,
2975 .num_resets = ARRAY_SIZE(gcc_ipq806x_resets),
2976 };
2977
2978 static const struct of_device_id gcc_ipq806x_match_table[] = {
2979 { .compatible = "qcom,gcc-ipq8064" },
2980 { }
2981 };
2982 MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table);
2983
gcc_ipq806x_probe(struct platform_device * pdev)2984 static int gcc_ipq806x_probe(struct platform_device *pdev)
2985 {
2986 struct device *dev = &pdev->dev;
2987 struct regmap *regmap;
2988 int ret;
2989
2990 ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000);
2991 if (ret)
2992 return ret;
2993
2994 ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000);
2995 if (ret)
2996 return ret;
2997
2998 ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc);
2999 if (ret)
3000 return ret;
3001
3002 regmap = dev_get_regmap(dev, NULL);
3003 if (!regmap)
3004 return -ENODEV;
3005
3006 /* Setup PLL18 static bits */
3007 regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400);
3008 regmap_write(regmap, 0x31b0, 0x3080);
3009
3010 /* Set GMAC footswitch sleep/wakeup values */
3011 regmap_write(regmap, 0x3cb8, 8);
3012 regmap_write(regmap, 0x3cd8, 8);
3013 regmap_write(regmap, 0x3cf8, 8);
3014 regmap_write(regmap, 0x3d18, 8);
3015
3016 return 0;
3017 }
3018
3019 static struct platform_driver gcc_ipq806x_driver = {
3020 .probe = gcc_ipq806x_probe,
3021 .driver = {
3022 .name = "gcc-ipq806x",
3023 .of_match_table = gcc_ipq806x_match_table,
3024 },
3025 };
3026
gcc_ipq806x_init(void)3027 static int __init gcc_ipq806x_init(void)
3028 {
3029 return platform_driver_register(&gcc_ipq806x_driver);
3030 }
3031 core_initcall(gcc_ipq806x_init);
3032
gcc_ipq806x_exit(void)3033 static void __exit gcc_ipq806x_exit(void)
3034 {
3035 platform_driver_unregister(&gcc_ipq806x_driver);
3036 }
3037 module_exit(gcc_ipq806x_exit);
3038
3039 MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver");
3040 MODULE_LICENSE("GPL v2");
3041 MODULE_ALIAS("platform:gcc-ipq806x");
3042