1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * r8a77965 Clock Pulse Generator / Module Standby and Software Reset
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 *
7 * Based on r8a7795-cpg-mssr.c
8 *
9 * Copyright (C) 2015 Glider bvba
10 * Copyright (C) 2015 Renesas Electronics Corp.
11 */
12
13 #include <linux/device.h>
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/soc/renesas/rcar-rst.h>
17
18 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
19
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
22
23 enum clk_ids {
24 /* Core Clock Outputs exported to DT */
25 LAST_DT_CORE_CLK = R8A77965_CLK_OSC,
26
27 /* External Input Clocks */
28 CLK_EXTAL,
29 CLK_EXTALR,
30
31 /* Internal Core Clocks */
32 CLK_MAIN,
33 CLK_PLL0,
34 CLK_PLL1,
35 CLK_PLL3,
36 CLK_PLL4,
37 CLK_PLL1_DIV2,
38 CLK_PLL1_DIV4,
39 CLK_S0,
40 CLK_S1,
41 CLK_S2,
42 CLK_S3,
43 CLK_SDSRC,
44 CLK_SSPSRC,
45 CLK_RINT,
46
47 /* Module Clocks */
48 MOD_CLK_BASE
49 };
50
51 static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
52 /* External Clock Inputs */
53 DEF_INPUT("extal", CLK_EXTAL),
54 DEF_INPUT("extalr", CLK_EXTALR),
55
56 /* Internal Core Clocks */
57 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
58 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
59 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
60 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
61 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
62
63 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
64 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
65 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
66 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
67 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
68 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
69 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
70
71 /* Core Clock Outputs */
72 DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
73 DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
74 DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
75 DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
76 DEF_FIXED("zx", R8A77965_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
77 DEF_FIXED("s0d1", R8A77965_CLK_S0D1, CLK_S0, 1, 1),
78 DEF_FIXED("s0d2", R8A77965_CLK_S0D2, CLK_S0, 2, 1),
79 DEF_FIXED("s0d3", R8A77965_CLK_S0D3, CLK_S0, 3, 1),
80 DEF_FIXED("s0d4", R8A77965_CLK_S0D4, CLK_S0, 4, 1),
81 DEF_FIXED("s0d6", R8A77965_CLK_S0D6, CLK_S0, 6, 1),
82 DEF_FIXED("s0d8", R8A77965_CLK_S0D8, CLK_S0, 8, 1),
83 DEF_FIXED("s0d12", R8A77965_CLK_S0D12, CLK_S0, 12, 1),
84 DEF_FIXED("s1d1", R8A77965_CLK_S1D1, CLK_S1, 1, 1),
85 DEF_FIXED("s1d2", R8A77965_CLK_S1D2, CLK_S1, 2, 1),
86 DEF_FIXED("s1d4", R8A77965_CLK_S1D4, CLK_S1, 4, 1),
87 DEF_FIXED("s2d1", R8A77965_CLK_S2D1, CLK_S2, 1, 1),
88 DEF_FIXED("s2d2", R8A77965_CLK_S2D2, CLK_S2, 2, 1),
89 DEF_FIXED("s2d4", R8A77965_CLK_S2D4, CLK_S2, 4, 1),
90 DEF_FIXED("s3d1", R8A77965_CLK_S3D1, CLK_S3, 1, 1),
91 DEF_FIXED("s3d2", R8A77965_CLK_S3D2, CLK_S3, 2, 1),
92 DEF_FIXED("s3d4", R8A77965_CLK_S3D4, CLK_S3, 4, 1),
93
94 DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, CLK_SDSRC, 0x074),
95 DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, CLK_SDSRC, 0x078),
96 DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268),
97 DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c),
98
99 DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),
100 DEF_FIXED("cp", R8A77965_CLK_CP, CLK_EXTAL, 2, 1),
101
102 DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
103 DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
104 DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014),
105 DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
106
107 DEF_DIV6_RO("osc", R8A77965_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
108 DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
109
110 DEF_BASE("r", R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
111 };
112
113 static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
114 DEF_MOD("scif5", 202, R8A77965_CLK_S3D4),
115 DEF_MOD("scif4", 203, R8A77965_CLK_S3D4),
116 DEF_MOD("scif3", 204, R8A77965_CLK_S3D4),
117 DEF_MOD("scif1", 206, R8A77965_CLK_S3D4),
118 DEF_MOD("scif0", 207, R8A77965_CLK_S3D4),
119 DEF_MOD("msiof3", 208, R8A77965_CLK_MSO),
120 DEF_MOD("msiof2", 209, R8A77965_CLK_MSO),
121 DEF_MOD("msiof1", 210, R8A77965_CLK_MSO),
122 DEF_MOD("msiof0", 211, R8A77965_CLK_MSO),
123 DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S0D3),
124 DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3),
125 DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),
126
127 DEF_MOD("cmt3", 300, R8A77965_CLK_R),
128 DEF_MOD("cmt2", 301, R8A77965_CLK_R),
129 DEF_MOD("cmt1", 302, R8A77965_CLK_R),
130 DEF_MOD("cmt0", 303, R8A77965_CLK_R),
131 DEF_MOD("scif2", 310, R8A77965_CLK_S3D4),
132 DEF_MOD("sdif3", 311, R8A77965_CLK_SD3),
133 DEF_MOD("sdif2", 312, R8A77965_CLK_SD2),
134 DEF_MOD("sdif1", 313, R8A77965_CLK_SD1),
135 DEF_MOD("sdif0", 314, R8A77965_CLK_SD0),
136 DEF_MOD("pcie1", 318, R8A77965_CLK_S3D1),
137 DEF_MOD("pcie0", 319, R8A77965_CLK_S3D1),
138 DEF_MOD("usb3-if0", 328, R8A77965_CLK_S3D1),
139 DEF_MOD("usb-dmac0", 330, R8A77965_CLK_S3D1),
140 DEF_MOD("usb-dmac1", 331, R8A77965_CLK_S3D1),
141
142 DEF_MOD("rwdt", 402, R8A77965_CLK_R),
143 DEF_MOD("intc-ex", 407, R8A77965_CLK_CP),
144 DEF_MOD("intc-ap", 408, R8A77965_CLK_S0D3),
145
146 DEF_MOD("audmac1", 501, R8A77965_CLK_S0D3),
147 DEF_MOD("audmac0", 502, R8A77965_CLK_S0D3),
148 DEF_MOD("drif7", 508, R8A77965_CLK_S3D2),
149 DEF_MOD("drif6", 509, R8A77965_CLK_S3D2),
150 DEF_MOD("drif5", 510, R8A77965_CLK_S3D2),
151 DEF_MOD("drif4", 511, R8A77965_CLK_S3D2),
152 DEF_MOD("drif3", 512, R8A77965_CLK_S3D2),
153 DEF_MOD("drif2", 513, R8A77965_CLK_S3D2),
154 DEF_MOD("drif1", 514, R8A77965_CLK_S3D2),
155 DEF_MOD("drif0", 515, R8A77965_CLK_S3D2),
156 DEF_MOD("hscif4", 516, R8A77965_CLK_S3D1),
157 DEF_MOD("hscif3", 517, R8A77965_CLK_S3D1),
158 DEF_MOD("hscif2", 518, R8A77965_CLK_S3D1),
159 DEF_MOD("hscif1", 519, R8A77965_CLK_S3D1),
160 DEF_MOD("hscif0", 520, R8A77965_CLK_S3D1),
161 DEF_MOD("thermal", 522, R8A77965_CLK_CP),
162 DEF_MOD("pwm", 523, R8A77965_CLK_S0D12),
163
164 DEF_MOD("fcpvd1", 602, R8A77965_CLK_S0D2),
165 DEF_MOD("fcpvd0", 603, R8A77965_CLK_S0D2),
166 DEF_MOD("fcpvb0", 607, R8A77965_CLK_S0D1),
167 DEF_MOD("fcpvi0", 611, R8A77965_CLK_S0D1),
168 DEF_MOD("fcpf0", 615, R8A77965_CLK_S0D1),
169 DEF_MOD("fcpcs", 619, R8A77965_CLK_S0D2),
170 DEF_MOD("vspd1", 622, R8A77965_CLK_S0D2),
171 DEF_MOD("vspd0", 623, R8A77965_CLK_S0D2),
172 DEF_MOD("vspb", 626, R8A77965_CLK_S0D1),
173 DEF_MOD("vspi0", 631, R8A77965_CLK_S0D1),
174
175 DEF_MOD("ehci1", 702, R8A77965_CLK_S3D4),
176 DEF_MOD("ehci0", 703, R8A77965_CLK_S3D4),
177 DEF_MOD("hsusb", 704, R8A77965_CLK_S3D4),
178 DEF_MOD("csi20", 714, R8A77965_CLK_CSI0),
179 DEF_MOD("csi40", 716, R8A77965_CLK_CSI0),
180 DEF_MOD("du3", 721, R8A77965_CLK_S2D1),
181 DEF_MOD("du1", 723, R8A77965_CLK_S2D1),
182 DEF_MOD("du0", 724, R8A77965_CLK_S2D1),
183 DEF_MOD("lvds", 727, R8A77965_CLK_S2D1),
184 DEF_MOD("hdmi0", 729, R8A77965_CLK_HDMI),
185
186 DEF_MOD("vin7", 804, R8A77965_CLK_S0D2),
187 DEF_MOD("vin6", 805, R8A77965_CLK_S0D2),
188 DEF_MOD("vin5", 806, R8A77965_CLK_S0D2),
189 DEF_MOD("vin4", 807, R8A77965_CLK_S0D2),
190 DEF_MOD("vin3", 808, R8A77965_CLK_S0D2),
191 DEF_MOD("vin2", 809, R8A77965_CLK_S0D2),
192 DEF_MOD("vin1", 810, R8A77965_CLK_S0D2),
193 DEF_MOD("vin0", 811, R8A77965_CLK_S0D2),
194 DEF_MOD("etheravb", 812, R8A77965_CLK_S0D6),
195 DEF_MOD("imr1", 822, R8A77965_CLK_S0D2),
196 DEF_MOD("imr0", 823, R8A77965_CLK_S0D2),
197
198 DEF_MOD("gpio7", 905, R8A77965_CLK_S3D4),
199 DEF_MOD("gpio6", 906, R8A77965_CLK_S3D4),
200 DEF_MOD("gpio5", 907, R8A77965_CLK_S3D4),
201 DEF_MOD("gpio4", 908, R8A77965_CLK_S3D4),
202 DEF_MOD("gpio3", 909, R8A77965_CLK_S3D4),
203 DEF_MOD("gpio2", 910, R8A77965_CLK_S3D4),
204 DEF_MOD("gpio1", 911, R8A77965_CLK_S3D4),
205 DEF_MOD("gpio0", 912, R8A77965_CLK_S3D4),
206 DEF_MOD("can-fd", 914, R8A77965_CLK_S3D2),
207 DEF_MOD("can-if1", 915, R8A77965_CLK_S3D4),
208 DEF_MOD("can-if0", 916, R8A77965_CLK_S3D4),
209 DEF_MOD("i2c6", 918, R8A77965_CLK_S0D6),
210 DEF_MOD("i2c5", 919, R8A77965_CLK_S0D6),
211 DEF_MOD("i2c-dvfs", 926, R8A77965_CLK_CP),
212 DEF_MOD("i2c4", 927, R8A77965_CLK_S0D6),
213 DEF_MOD("i2c3", 928, R8A77965_CLK_S0D6),
214 DEF_MOD("i2c2", 929, R8A77965_CLK_S3D2),
215 DEF_MOD("i2c1", 930, R8A77965_CLK_S3D2),
216 DEF_MOD("i2c0", 931, R8A77965_CLK_S3D2),
217
218 DEF_MOD("ssi-all", 1005, R8A77965_CLK_S3D4),
219 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
220 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
221 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
222 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
223 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
224 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
225 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
226 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
227 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
228 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
229 DEF_MOD("scu-all", 1017, R8A77965_CLK_S3D4),
230 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
231 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
232 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
233 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
234 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
235 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
236 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
237 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
238 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
239 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
240 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
241 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
242 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
243 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
244 };
245
246 static const unsigned int r8a77965_crit_mod_clks[] __initconst = {
247 MOD_CLK_ID(408), /* INTC-AP (GIC) */
248 };
249
250 /*
251 * CPG Clock Data
252 */
253
254 /*
255 * MD EXTAL PLL0 PLL1 PLL3 PLL4
256 * 14 13 19 17 (MHz)
257 *-----------------------------------------------------------
258 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144
259 * 0 0 0 1 16.66 x 1 x180 x192 x128 x144
260 * 0 0 1 0 Prohibited setting
261 * 0 0 1 1 16.66 x 1 x180 x192 x192 x144
262 * 0 1 0 0 20 x 1 x150 x160 x160 x120
263 * 0 1 0 1 20 x 1 x150 x160 x106 x120
264 * 0 1 1 0 Prohibited setting
265 * 0 1 1 1 20 x 1 x150 x160 x160 x120
266 * 1 0 0 0 25 x 1 x120 x128 x128 x96
267 * 1 0 0 1 25 x 1 x120 x128 x84 x96
268 * 1 0 1 0 Prohibited setting
269 * 1 0 1 1 25 x 1 x120 x128 x128 x96
270 * 1 1 0 0 33.33 / 2 x180 x192 x192 x144
271 * 1 1 0 1 33.33 / 2 x180 x192 x128 x144
272 * 1 1 1 0 Prohibited setting
273 * 1 1 1 1 33.33 / 2 x180 x192 x192 x144
274 */
275 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
276 (((md) & BIT(13)) >> 11) | \
277 (((md) & BIT(19)) >> 18) | \
278 (((md) & BIT(17)) >> 17))
279
280 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
281 /* EXTAL div PLL1 mult/div PLL3 mult/div */
282 { 1, 192, 1, 192, 1, },
283 { 1, 192, 1, 128, 1, },
284 { 0, /* Prohibited setting */ },
285 { 1, 192, 1, 192, 1, },
286 { 1, 160, 1, 160, 1, },
287 { 1, 160, 1, 106, 1, },
288 { 0, /* Prohibited setting */ },
289 { 1, 160, 1, 160, 1, },
290 { 1, 128, 1, 128, 1, },
291 { 1, 128, 1, 84, 1, },
292 { 0, /* Prohibited setting */ },
293 { 1, 128, 1, 128, 1, },
294 { 2, 192, 1, 192, 1, },
295 { 2, 192, 1, 128, 1, },
296 { 0, /* Prohibited setting */ },
297 { 2, 192, 1, 192, 1, },
298 };
299
r8a77965_cpg_mssr_init(struct device * dev)300 static int __init r8a77965_cpg_mssr_init(struct device *dev)
301 {
302 const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
303 u32 cpg_mode;
304 int error;
305
306 error = rcar_rst_read_mode_pins(&cpg_mode);
307 if (error)
308 return error;
309
310 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
311 if (!cpg_pll_config->extal_div) {
312 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
313 return -EINVAL;
314 }
315
316 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
317 };
318
319 const struct cpg_mssr_info r8a77965_cpg_mssr_info __initconst = {
320 /* Core Clocks */
321 .core_clks = r8a77965_core_clks,
322 .num_core_clks = ARRAY_SIZE(r8a77965_core_clks),
323 .last_dt_core_clk = LAST_DT_CORE_CLK,
324 .num_total_core_clks = MOD_CLK_BASE,
325
326 /* Module Clocks */
327 .mod_clks = r8a77965_mod_clks,
328 .num_mod_clks = ARRAY_SIZE(r8a77965_mod_clks),
329 .num_hw_mod_clks = 12 * 32,
330
331 /* Critical Module Clocks */
332 .crit_mod_clks = r8a77965_crit_mod_clks,
333 .num_crit_mod_clks = ARRAY_SIZE(r8a77965_crit_mod_clks),
334
335 /* Callbacks */
336 .init = r8a77965_cpg_mssr_init,
337 .cpg_clk_register = rcar_gen3_cpg_clk_register,
338 };
339