1 /*
2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Lin Huang <hl@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/arm-smccc.h>
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/io.h>
20 #include <linux/slab.h>
21 #include <soc/rockchip/rockchip_sip.h>
22 #include "clk.h"
23
24 struct rockchip_ddrclk {
25 struct clk_hw hw;
26 void __iomem *reg_base;
27 int mux_offset;
28 int mux_shift;
29 int mux_width;
30 int div_shift;
31 int div_width;
32 int ddr_flag;
33 spinlock_t *lock;
34 };
35
36 #define to_rockchip_ddrclk_hw(hw) container_of(hw, struct rockchip_ddrclk, hw)
37
rockchip_ddrclk_sip_set_rate(struct clk_hw * hw,unsigned long drate,unsigned long prate)38 static int rockchip_ddrclk_sip_set_rate(struct clk_hw *hw, unsigned long drate,
39 unsigned long prate)
40 {
41 struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);
42 unsigned long flags;
43 struct arm_smccc_res res;
44
45 spin_lock_irqsave(ddrclk->lock, flags);
46 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, drate, 0,
47 ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE,
48 0, 0, 0, 0, &res);
49 spin_unlock_irqrestore(ddrclk->lock, flags);
50
51 return res.a0;
52 }
53
54 static unsigned long
rockchip_ddrclk_sip_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)55 rockchip_ddrclk_sip_recalc_rate(struct clk_hw *hw,
56 unsigned long parent_rate)
57 {
58 struct arm_smccc_res res;
59
60 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
61 ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE,
62 0, 0, 0, 0, &res);
63
64 return res.a0;
65 }
66
rockchip_ddrclk_sip_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)67 static long rockchip_ddrclk_sip_round_rate(struct clk_hw *hw,
68 unsigned long rate,
69 unsigned long *prate)
70 {
71 struct arm_smccc_res res;
72
73 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, rate, 0,
74 ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE,
75 0, 0, 0, 0, &res);
76
77 return res.a0;
78 }
79
rockchip_ddrclk_get_parent(struct clk_hw * hw)80 static u8 rockchip_ddrclk_get_parent(struct clk_hw *hw)
81 {
82 struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);
83 u32 val;
84
85 val = clk_readl(ddrclk->reg_base +
86 ddrclk->mux_offset) >> ddrclk->mux_shift;
87 val &= GENMASK(ddrclk->mux_width - 1, 0);
88
89 return val;
90 }
91
92 static const struct clk_ops rockchip_ddrclk_sip_ops = {
93 .recalc_rate = rockchip_ddrclk_sip_recalc_rate,
94 .set_rate = rockchip_ddrclk_sip_set_rate,
95 .round_rate = rockchip_ddrclk_sip_round_rate,
96 .get_parent = rockchip_ddrclk_get_parent,
97 };
98
rockchip_clk_register_ddrclk(const char * name,int flags,const char * const * parent_names,u8 num_parents,int mux_offset,int mux_shift,int mux_width,int div_shift,int div_width,int ddr_flag,void __iomem * reg_base,spinlock_t * lock)99 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
100 const char *const *parent_names,
101 u8 num_parents, int mux_offset,
102 int mux_shift, int mux_width,
103 int div_shift, int div_width,
104 int ddr_flag, void __iomem *reg_base,
105 spinlock_t *lock)
106 {
107 struct rockchip_ddrclk *ddrclk;
108 struct clk_init_data init;
109 struct clk *clk;
110
111 ddrclk = kzalloc(sizeof(*ddrclk), GFP_KERNEL);
112 if (!ddrclk)
113 return ERR_PTR(-ENOMEM);
114
115 init.name = name;
116 init.parent_names = parent_names;
117 init.num_parents = num_parents;
118
119 init.flags = flags;
120 init.flags |= CLK_SET_RATE_NO_REPARENT;
121
122 switch (ddr_flag) {
123 case ROCKCHIP_DDRCLK_SIP:
124 init.ops = &rockchip_ddrclk_sip_ops;
125 break;
126 default:
127 pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
128 kfree(ddrclk);
129 return ERR_PTR(-EINVAL);
130 }
131
132 ddrclk->reg_base = reg_base;
133 ddrclk->lock = lock;
134 ddrclk->hw.init = &init;
135 ddrclk->mux_offset = mux_offset;
136 ddrclk->mux_shift = mux_shift;
137 ddrclk->mux_width = mux_width;
138 ddrclk->div_shift = div_shift;
139 ddrclk->div_width = div_width;
140 ddrclk->ddr_flag = ddr_flag;
141
142 clk = clk_register(NULL, &ddrclk->hw);
143 if (IS_ERR(clk))
144 kfree(ddrclk);
145
146 return clk;
147 }
148