1 /* 2 * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> 3 * 4 * Based on ccu-sun8i-h3.h, which is: 5 * Copyright (c) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #ifndef _CCU_SUN8I_H3_H_ 19 #define _CCU_SUN8I_H3_H_ 20 21 #include <dt-bindings/clock/sun8i-v3s-ccu.h> 22 #include <dt-bindings/reset/sun8i-v3s-ccu.h> 23 24 #define CLK_PLL_CPU 0 25 #define CLK_PLL_AUDIO_BASE 1 26 #define CLK_PLL_AUDIO 2 27 #define CLK_PLL_AUDIO_2X 3 28 #define CLK_PLL_AUDIO_4X 4 29 #define CLK_PLL_AUDIO_8X 5 30 #define CLK_PLL_VIDEO 6 31 #define CLK_PLL_VE 7 32 #define CLK_PLL_DDR0 8 33 #define CLK_PLL_PERIPH0 9 34 #define CLK_PLL_PERIPH0_2X 10 35 #define CLK_PLL_ISP 11 36 #define CLK_PLL_PERIPH1 12 37 /* Reserve one number for not implemented and not used PLL_DDR1 */ 38 39 /* The CPU clock is exported */ 40 41 #define CLK_AXI 15 42 #define CLK_AHB1 16 43 #define CLK_APB1 17 44 #define CLK_APB2 18 45 #define CLK_AHB2 19 46 47 /* All the bus gates are exported */ 48 49 /* The first bunch of module clocks are exported */ 50 51 #define CLK_DRAM 58 52 53 /* All the DRAM gates are exported */ 54 55 /* Some more module clocks are exported */ 56 57 #define CLK_MBUS 72 58 59 /* And the GPU module clock is exported */ 60 61 #define CLK_PLL_DDR1 74 62 63 #define CLK_NUMBER (CLK_PLL_DDR1 + 1) 64 65 #endif /* _CCU_SUN8I_H3_H_ */ 66