1 /*
2  * Copyright 2015 Linaro Ltd.
3  * Copyright (C) 2014 ZTE Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  */
9 
10 #ifndef __ZTE_CLK_H
11 #define __ZTE_CLK_H
12 #include <linux/clk-provider.h>
13 #include <linux/spinlock.h>
14 
15 #define PNAME(x) static const char *x[]
16 
17 struct zx_pll_config {
18 	unsigned long rate;
19 	u32 cfg0;
20 	u32 cfg1;
21 };
22 
23 struct clk_zx_pll {
24 	struct clk_hw hw;
25 	void __iomem *reg_base;
26 	const struct zx_pll_config *lookup_table; /* order by rate asc */
27 	int count;
28 	spinlock_t *lock;
29 	u8 pd_bit;		/* power down bit */
30 	u8 lock_bit;		/* pll lock flag bit */
31 };
32 
33 #define PLL_RATE(_rate, _cfg0, _cfg1)	\
34 {					\
35 	.rate = _rate,			\
36 	.cfg0 = _cfg0,			\
37 	.cfg1 = _cfg1,			\
38 }
39 
40 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock)		\
41 {									\
42 	.reg_base	= (void __iomem *) _reg,			\
43 	.lookup_table	= _table,					\
44 	.count		= ARRAY_SIZE(_table),				\
45 	.pd_bit		= _pd,						\
46 	.lock_bit	= _lock,					\
47 	.hw.init	 = CLK_HW_INIT(_name, _parent, &zx_pll_ops,	\
48 				CLK_GET_RATE_NOCACHE),			\
49 }
50 
51 /*
52  * The pd_bit is not available on ZX296718, so let's pass something
53  * bigger than 31, e.g. 0xff, to indicate that.
54  */
55 #define ZX296718_PLL(_name, _parent, _reg, _table)			\
56 ZX_PLL(_name, _parent, _reg, _table, 0xff, 30)
57 
58 struct zx_clk_gate {
59 	struct clk_gate gate;
60 	u16		id;
61 };
62 
63 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags)		\
64 {									\
65 	.gate = {							\
66 		.reg = (void __iomem *) _reg,				\
67 		.bit_idx = (_bit),					\
68 		.flags = _gflags,					\
69 		.lock = &clk_lock,					\
70 		.hw.init = CLK_HW_INIT(_name,				\
71 					_parent,			\
72 					&clk_gate_ops,			\
73 					_flag | CLK_IGNORE_UNUSED),	\
74 	},								\
75 	.id	= _id,							\
76 }
77 
78 struct zx_clk_fixed_factor {
79 	struct clk_fixed_factor factor;
80 	u16	id;
81 };
82 
83 #define FFACTOR(_id, _name, _parent, _mult, _div, _flag)		\
84 {									\
85 	.factor = {							\
86 		.div		= _div,					\
87 		.mult		= _mult,				\
88 		.hw.init	= CLK_HW_INIT(_name,			\
89 					      _parent,			\
90 					      &clk_fixed_factor_ops,	\
91 					      _flag),			\
92 	},								\
93 	.id = _id,							\
94 }
95 
96 struct zx_clk_mux {
97 	struct clk_mux mux;
98 	u16	id;
99 };
100 
101 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag)	\
102 {									\
103 	.mux = {							\
104 		.reg		= (void __iomem *) _reg,		\
105 		.mask		= BIT(_width) - 1,			\
106 		.shift		= _shift,				\
107 		.flags		= _mflag,				\
108 		.lock		= &clk_lock,				\
109 		.hw.init	= CLK_HW_INIT_PARENTS(_name,		\
110 						      _parent,		\
111 						      &clk_mux_ops,	\
112 						      _flag),		\
113 	},								\
114 	.id = _id,							\
115 }
116 
117 #define MUX(_id, _name, _parent, _reg, _shift, _width)			\
118 MUX_F(_id, _name, _parent, _reg, _shift, _width, 0, 0)
119 
120 struct zx_clk_div {
121 	struct clk_divider div;
122 	u16	id;
123 };
124 
125 #define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table)	\
126 {									\
127 	.div = {							\
128 		.reg		= (void __iomem *) _reg,		\
129 		.shift		= _shift,				\
130 		.width		= _width,				\
131 		.flags		= 0,					\
132 		.table		= _table,				\
133 		.lock		= &clk_lock,				\
134 		.hw.init	= CLK_HW_INIT(_name,			\
135 					      _parent,			\
136 					      &clk_divider_ops,		\
137 					      _flag),			\
138 	},								\
139 	.id = _id,							\
140 }
141 
142 struct clk_zx_audio_divider {
143 	struct clk_hw				hw;
144 	void __iomem				*reg_base;
145 	unsigned int				rate_count;
146 	spinlock_t				*lock;
147 	u16					id;
148 };
149 
150 #define AUDIO_DIV(_id, _name, _parent, _reg)				\
151 {									\
152 	.reg_base	= (void __iomem *) _reg,			\
153 	.lock		= &clk_lock,					\
154 	.hw.init	= CLK_HW_INIT(_name,				\
155 				      _parent,				\
156 				      &zx_audio_div_ops,		\
157 				      0),				\
158 	.id = _id,							\
159 }
160 
161 struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
162 	unsigned long flags, void __iomem *reg_base,
163 	const struct zx_pll_config *lookup_table, int count, spinlock_t *lock);
164 
165 struct clk_zx_audio {
166 	struct clk_hw hw;
167 	void __iomem *reg_base;
168 };
169 
170 struct clk *clk_register_zx_audio(const char *name,
171 				  const char * const parent_name,
172 				  unsigned long flags, void __iomem *reg_base);
173 
174 extern const struct clk_ops zx_pll_ops;
175 extern const struct clk_ops zx_audio_div_ops;
176 
177 #endif
178