1 /*
2  * Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel
3  * module (C) 2006 Tim Small
4  *
5  * This file may be distributed under the terms of the GNU General
6  * Public License.
7  *
8  * Written by Tim Small <tim@buttersideup.com>, based on work by Linux
9  * Networx, Thayne Harbaugh, Dan Hollis <goemon at anime dot net> and
10  * others.
11  *
12  * 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>.
13  *
14  * Written with reference to 82443BX Host Bridge Datasheet:
15  * http://download.intel.com/design/chipsets/datashts/29063301.pdf
16  * references to this document given in [].
17  *
18  * This module doesn't support the 440LX, but it may be possible to
19  * make it do so (the 440LX's register definitions are different, but
20  * not completely so - I haven't studied them in enough detail to know
21  * how easy this would be).
22  */
23 
24 #include <linux/module.h>
25 #include <linux/init.h>
26 
27 #include <linux/pci.h>
28 #include <linux/pci_ids.h>
29 
30 
31 #include <linux/edac.h>
32 #include "edac_module.h"
33 
34 #define EDAC_MOD_STR    "i82443bxgx_edac"
35 
36 /* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory
37  * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory
38  * rows" "The 82443BX supports multiple-bit error detection and
39  * single-bit error correction when ECC mode is enabled and
40  * single/multi-bit error detection when correction is disabled.
41  * During writes to the DRAM, the 82443BX generates ECC for the data
42  * on a QWord basis. Partial QWord writes require a read-modify-write
43  * cycle when ECC is enabled."
44 */
45 
46 /* "Additionally, the 82443BX ensures that the data is corrected in
47  * main memory so that accumulation of errors is prevented. Another
48  * error within the same QWord would result in a double-bit error
49  * which is unrecoverable. This is known as hardware scrubbing since
50  * it requires no software intervention to correct the data in memory."
51  */
52 
53 /* [Also see page 100 (section 4.3), "DRAM Interface"]
54  * [Also see page 112 (section 4.6.1.4), ECC]
55  */
56 
57 #define I82443BXGX_NR_CSROWS 8
58 #define I82443BXGX_NR_CHANS  1
59 #define I82443BXGX_NR_DIMMS  4
60 
61 /* 82443 PCI Device 0 */
62 #define I82443BXGX_NBXCFG 0x50	/* 32bit register starting at this PCI
63 				 * config space offset */
64 #define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24	/* Array of bits, zero if
65 						 * row is non-ECC */
66 #define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12	/* 2 bits,00=100MHz,10=66 MHz */
67 
68 #define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7	/* 2 bits:       */
69 #define I82443BXGX_NBXCFG_INTEGRITY_NONE   0x0	/* 00 = Non-ECC */
70 #define I82443BXGX_NBXCFG_INTEGRITY_EC     0x1	/* 01 = EC (only) */
71 #define I82443BXGX_NBXCFG_INTEGRITY_ECC    0x2	/* 10 = ECC */
72 #define I82443BXGX_NBXCFG_INTEGRITY_SCRUB  0x3	/* 11 = ECC + HW Scrub */
73 
74 #define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE  6
75 
76 /* 82443 PCI Device 0 */
77 #define I82443BXGX_EAP   0x80	/* 32bit register starting at this PCI
78 				 * config space offset, Error Address
79 				 * Pointer Register */
80 #define I82443BXGX_EAP_OFFSET_EAP  12	/* High 20 bits of error address */
81 #define I82443BXGX_EAP_OFFSET_MBE  BIT(1)	/* Err at EAP was multi-bit (W1TC) */
82 #define I82443BXGX_EAP_OFFSET_SBE  BIT(0)	/* Err at EAP was single-bit (W1TC) */
83 
84 #define I82443BXGX_ERRCMD  0x90	/* 8bit register starting at this PCI
85 				 * config space offset. */
86 #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1)	/* 1 = enable */
87 #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0)	/* 1 = enable */
88 
89 #define I82443BXGX_ERRSTS  0x91	/* 16bit register starting at this PCI
90 				 * config space offset. */
91 #define I82443BXGX_ERRSTS_OFFSET_MBFRE 5	/* 3 bits - first err row multibit */
92 #define I82443BXGX_ERRSTS_OFFSET_MEF   BIT(4)	/* 1 = MBE occurred */
93 #define I82443BXGX_ERRSTS_OFFSET_SBFRE 1	/* 3 bits - first err row singlebit */
94 #define I82443BXGX_ERRSTS_OFFSET_SEF   BIT(0)	/* 1 = SBE occurred */
95 
96 #define I82443BXGX_DRAMC 0x57	/* 8bit register starting at this PCI
97 				 * config space offset. */
98 #define I82443BXGX_DRAMC_OFFSET_DT 3	/* 2 bits, DRAM Type */
99 #define I82443BXGX_DRAMC_DRAM_IS_EDO 0	/* 00 = EDO */
100 #define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1	/* 01 = SDRAM */
101 #define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2	/* 10 = Registered SDRAM */
102 
103 #define I82443BXGX_DRB 0x60	/* 8x 8bit registers starting at this PCI
104 				 * config space offset. */
105 
106 /* FIXME - don't poll when ECC disabled? */
107 
108 struct i82443bxgx_edacmc_error_info {
109 	u32 eap;
110 };
111 
112 static struct edac_pci_ctl_info *i82443bxgx_pci;
113 
114 static struct pci_dev *mci_pdev;	/* init dev: in case that AGP code has
115 					 * already registered driver
116 					 */
117 
118 static int i82443bxgx_registered = 1;
119 
i82443bxgx_edacmc_get_error_info(struct mem_ctl_info * mci,struct i82443bxgx_edacmc_error_info * info)120 static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci,
121 				struct i82443bxgx_edacmc_error_info
122 				*info)
123 {
124 	struct pci_dev *pdev;
125 	pdev = to_pci_dev(mci->pdev);
126 	pci_read_config_dword(pdev, I82443BXGX_EAP, &info->eap);
127 	if (info->eap & I82443BXGX_EAP_OFFSET_SBE)
128 		/* Clear error to allow next error to be reported [p.61] */
129 		pci_write_bits32(pdev, I82443BXGX_EAP,
130 				 I82443BXGX_EAP_OFFSET_SBE,
131 				 I82443BXGX_EAP_OFFSET_SBE);
132 
133 	if (info->eap & I82443BXGX_EAP_OFFSET_MBE)
134 		/* Clear error to allow next error to be reported [p.61] */
135 		pci_write_bits32(pdev, I82443BXGX_EAP,
136 				 I82443BXGX_EAP_OFFSET_MBE,
137 				 I82443BXGX_EAP_OFFSET_MBE);
138 }
139 
i82443bxgx_edacmc_process_error_info(struct mem_ctl_info * mci,struct i82443bxgx_edacmc_error_info * info,int handle_errors)140 static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci,
141 						struct
142 						i82443bxgx_edacmc_error_info
143 						*info, int handle_errors)
144 {
145 	int error_found = 0;
146 	u32 eapaddr, page, pageoffset;
147 
148 	/* bits 30:12 hold the 4kb block in which the error occurred
149 	 * [p.61] */
150 	eapaddr = (info->eap & 0xfffff000);
151 	page = eapaddr >> PAGE_SHIFT;
152 	pageoffset = eapaddr - (page << PAGE_SHIFT);
153 
154 	if (info->eap & I82443BXGX_EAP_OFFSET_SBE) {
155 		error_found = 1;
156 		if (handle_errors)
157 			edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
158 					     page, pageoffset, 0,
159 					     edac_mc_find_csrow_by_page(mci, page),
160 					     0, -1, mci->ctl_name, "");
161 	}
162 
163 	if (info->eap & I82443BXGX_EAP_OFFSET_MBE) {
164 		error_found = 1;
165 		if (handle_errors)
166 			edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
167 					     page, pageoffset, 0,
168 					     edac_mc_find_csrow_by_page(mci, page),
169 					     0, -1, mci->ctl_name, "");
170 	}
171 
172 	return error_found;
173 }
174 
i82443bxgx_edacmc_check(struct mem_ctl_info * mci)175 static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci)
176 {
177 	struct i82443bxgx_edacmc_error_info info;
178 
179 	edac_dbg(1, "MC%d\n", mci->mc_idx);
180 	i82443bxgx_edacmc_get_error_info(mci, &info);
181 	i82443bxgx_edacmc_process_error_info(mci, &info, 1);
182 }
183 
i82443bxgx_init_csrows(struct mem_ctl_info * mci,struct pci_dev * pdev,enum edac_type edac_mode,enum mem_type mtype)184 static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
185 				struct pci_dev *pdev,
186 				enum edac_type edac_mode,
187 				enum mem_type mtype)
188 {
189 	struct csrow_info *csrow;
190 	struct dimm_info *dimm;
191 	int index;
192 	u8 drbar, dramc;
193 	u32 row_base, row_high_limit, row_high_limit_last;
194 
195 	pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
196 	row_high_limit_last = 0;
197 	for (index = 0; index < mci->nr_csrows; index++) {
198 		csrow = mci->csrows[index];
199 		dimm = csrow->channels[0]->dimm;
200 
201 		pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar);
202 		edac_dbg(1, "MC%d: Row=%d DRB = %#0x\n",
203 			 mci->mc_idx, index, drbar);
204 		row_high_limit = ((u32) drbar << 23);
205 		/* find the DRAM Chip Select Base address and mask */
206 		edac_dbg(1, "MC%d: Row=%d, Boundary Address=%#0x, Last = %#0x\n",
207 			 mci->mc_idx, index, row_high_limit,
208 			 row_high_limit_last);
209 
210 		/* 440GX goes to 2GB, represented with a DRB of 0. */
211 		if (row_high_limit_last && !row_high_limit)
212 			row_high_limit = 1UL << 31;
213 
214 		/* This row is empty [p.49] */
215 		if (row_high_limit == row_high_limit_last)
216 			continue;
217 		row_base = row_high_limit_last;
218 		csrow->first_page = row_base >> PAGE_SHIFT;
219 		csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
220 		dimm->nr_pages = csrow->last_page - csrow->first_page + 1;
221 		/* EAP reports in 4kilobyte granularity [61] */
222 		dimm->grain = 1 << 12;
223 		dimm->mtype = mtype;
224 		/* I don't think 440BX can tell you device type? FIXME? */
225 		dimm->dtype = DEV_UNKNOWN;
226 		/* Mode is global to all rows on 440BX */
227 		dimm->edac_mode = edac_mode;
228 		row_high_limit_last = row_high_limit;
229 	}
230 }
231 
i82443bxgx_edacmc_probe1(struct pci_dev * pdev,int dev_idx)232 static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
233 {
234 	struct mem_ctl_info *mci;
235 	struct edac_mc_layer layers[2];
236 	u8 dramc;
237 	u32 nbxcfg, ecc_mode;
238 	enum mem_type mtype;
239 	enum edac_type edac_mode;
240 
241 	edac_dbg(0, "MC:\n");
242 
243 	/* Something is really hosed if PCI config space reads from
244 	 * the MC aren't working.
245 	 */
246 	if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg))
247 		return -EIO;
248 
249 	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
250 	layers[0].size = I82443BXGX_NR_CSROWS;
251 	layers[0].is_virt_csrow = true;
252 	layers[1].type = EDAC_MC_LAYER_CHANNEL;
253 	layers[1].size = I82443BXGX_NR_CHANS;
254 	layers[1].is_virt_csrow = false;
255 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
256 	if (mci == NULL)
257 		return -ENOMEM;
258 
259 	edac_dbg(0, "MC: mci = %p\n", mci);
260 	mci->pdev = &pdev->dev;
261 	mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR;
262 	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
263 	pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
264 	switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) | BIT(1))) {
265 	case I82443BXGX_DRAMC_DRAM_IS_EDO:
266 		mtype = MEM_EDO;
267 		break;
268 	case I82443BXGX_DRAMC_DRAM_IS_SDRAM:
269 		mtype = MEM_SDR;
270 		break;
271 	case I82443BXGX_DRAMC_DRAM_IS_RSDRAM:
272 		mtype = MEM_RDR;
273 		break;
274 	default:
275 		edac_dbg(0, "Unknown/reserved DRAM type value in DRAMC register!\n");
276 		mtype = -MEM_UNKNOWN;
277 	}
278 
279 	if ((mtype == MEM_SDR) || (mtype == MEM_RDR))
280 		mci->edac_cap = mci->edac_ctl_cap;
281 	else
282 		mci->edac_cap = EDAC_FLAG_NONE;
283 
284 	mci->scrub_cap = SCRUB_FLAG_HW_SRC;
285 	pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg);
286 	ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) &
287 		(BIT(0) | BIT(1)));
288 
289 	mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB)
290 		? SCRUB_HW_SRC : SCRUB_NONE;
291 
292 	switch (ecc_mode) {
293 	case I82443BXGX_NBXCFG_INTEGRITY_NONE:
294 		edac_mode = EDAC_NONE;
295 		break;
296 	case I82443BXGX_NBXCFG_INTEGRITY_EC:
297 		edac_mode = EDAC_EC;
298 		break;
299 	case I82443BXGX_NBXCFG_INTEGRITY_ECC:
300 	case I82443BXGX_NBXCFG_INTEGRITY_SCRUB:
301 		edac_mode = EDAC_SECDED;
302 		break;
303 	default:
304 		edac_dbg(0, "Unknown/reserved ECC state in NBXCFG register!\n");
305 		edac_mode = EDAC_UNKNOWN;
306 		break;
307 	}
308 
309 	i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype);
310 
311 	/* Many BIOSes don't clear error flags on boot, so do this
312 	 * here, or we get "phantom" errors occurring at module-load
313 	 * time. */
314 	pci_write_bits32(pdev, I82443BXGX_EAP,
315 			(I82443BXGX_EAP_OFFSET_SBE |
316 				I82443BXGX_EAP_OFFSET_MBE),
317 			(I82443BXGX_EAP_OFFSET_SBE |
318 				I82443BXGX_EAP_OFFSET_MBE));
319 
320 	mci->mod_name = EDAC_MOD_STR;
321 	mci->ctl_name = "I82443BXGX";
322 	mci->dev_name = pci_name(pdev);
323 	mci->edac_check = i82443bxgx_edacmc_check;
324 	mci->ctl_page_to_phys = NULL;
325 
326 	if (edac_mc_add_mc(mci)) {
327 		edac_dbg(3, "failed edac_mc_add_mc()\n");
328 		goto fail;
329 	}
330 
331 	/* allocating generic PCI control info */
332 	i82443bxgx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
333 	if (!i82443bxgx_pci) {
334 		printk(KERN_WARNING
335 			"%s(): Unable to create PCI control\n",
336 			__func__);
337 		printk(KERN_WARNING
338 			"%s(): PCI error report via EDAC not setup\n",
339 			__func__);
340 	}
341 
342 	edac_dbg(3, "MC: success\n");
343 	return 0;
344 
345 fail:
346 	edac_mc_free(mci);
347 	return -ENODEV;
348 }
349 
350 /* returns count (>= 0), or negative on error */
i82443bxgx_edacmc_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)351 static int i82443bxgx_edacmc_init_one(struct pci_dev *pdev,
352 				      const struct pci_device_id *ent)
353 {
354 	int rc;
355 
356 	edac_dbg(0, "MC:\n");
357 
358 	/* don't need to call pci_enable_device() */
359 	rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data);
360 
361 	if (mci_pdev == NULL)
362 		mci_pdev = pci_dev_get(pdev);
363 
364 	return rc;
365 }
366 
i82443bxgx_edacmc_remove_one(struct pci_dev * pdev)367 static void i82443bxgx_edacmc_remove_one(struct pci_dev *pdev)
368 {
369 	struct mem_ctl_info *mci;
370 
371 	edac_dbg(0, "\n");
372 
373 	if (i82443bxgx_pci)
374 		edac_pci_release_generic_ctl(i82443bxgx_pci);
375 
376 	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
377 		return;
378 
379 	edac_mc_free(mci);
380 }
381 
382 static const struct pci_device_id i82443bxgx_pci_tbl[] = {
383 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)},
384 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)},
385 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)},
386 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2)},
387 	{0,}			/* 0 terminated list. */
388 };
389 
390 MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl);
391 
392 static struct pci_driver i82443bxgx_edacmc_driver = {
393 	.name = EDAC_MOD_STR,
394 	.probe = i82443bxgx_edacmc_init_one,
395 	.remove = i82443bxgx_edacmc_remove_one,
396 	.id_table = i82443bxgx_pci_tbl,
397 };
398 
i82443bxgx_edacmc_init(void)399 static int __init i82443bxgx_edacmc_init(void)
400 {
401 	int pci_rc;
402        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
403        opstate_init();
404 
405 	pci_rc = pci_register_driver(&i82443bxgx_edacmc_driver);
406 	if (pci_rc < 0)
407 		goto fail0;
408 
409 	if (mci_pdev == NULL) {
410 		const struct pci_device_id *id = &i82443bxgx_pci_tbl[0];
411 		int i = 0;
412 		i82443bxgx_registered = 0;
413 
414 		while (mci_pdev == NULL && id->vendor != 0) {
415 			mci_pdev = pci_get_device(id->vendor,
416 					id->device, NULL);
417 			i++;
418 			id = &i82443bxgx_pci_tbl[i];
419 		}
420 		if (!mci_pdev) {
421 			edac_dbg(0, "i82443bxgx pci_get_device fail\n");
422 			pci_rc = -ENODEV;
423 			goto fail1;
424 		}
425 
426 		pci_rc = i82443bxgx_edacmc_init_one(mci_pdev, i82443bxgx_pci_tbl);
427 
428 		if (pci_rc < 0) {
429 			edac_dbg(0, "i82443bxgx init fail\n");
430 			pci_rc = -ENODEV;
431 			goto fail1;
432 		}
433 	}
434 
435 	return 0;
436 
437 fail1:
438 	pci_unregister_driver(&i82443bxgx_edacmc_driver);
439 
440 fail0:
441 	pci_dev_put(mci_pdev);
442 	return pci_rc;
443 }
444 
i82443bxgx_edacmc_exit(void)445 static void __exit i82443bxgx_edacmc_exit(void)
446 {
447 	pci_unregister_driver(&i82443bxgx_edacmc_driver);
448 
449 	if (!i82443bxgx_registered)
450 		i82443bxgx_edacmc_remove_one(mci_pdev);
451 
452 	pci_dev_put(mci_pdev);
453 }
454 
455 module_init(i82443bxgx_edacmc_init);
456 module_exit(i82443bxgx_edacmc_exit);
457 
458 MODULE_LICENSE("GPL");
459 MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD");
460 MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers");
461 
462 module_param(edac_op_state, int, 0444);
463 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
464