1 /*
2 * Copyright (c) 2011 Jamie Iles
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * All enquiries to support@picochip.com
9 */
10 #include <linux/acpi.h>
11 #include <linux/clk.h>
12 #include <linux/err.h>
13 #include <linux/gpio/driver.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/ioport.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/of_irq.h>
25 #include <linux/platform_device.h>
26 #include <linux/property.h>
27 #include <linux/reset.h>
28 #include <linux/spinlock.h>
29 #include <linux/platform_data/gpio-dwapb.h>
30 #include <linux/slab.h>
31
32 #include "gpiolib.h"
33
34 #define GPIO_SWPORTA_DR 0x00
35 #define GPIO_SWPORTA_DDR 0x04
36 #define GPIO_SWPORTB_DR 0x0c
37 #define GPIO_SWPORTB_DDR 0x10
38 #define GPIO_SWPORTC_DR 0x18
39 #define GPIO_SWPORTC_DDR 0x1c
40 #define GPIO_SWPORTD_DR 0x24
41 #define GPIO_SWPORTD_DDR 0x28
42 #define GPIO_INTEN 0x30
43 #define GPIO_INTMASK 0x34
44 #define GPIO_INTTYPE_LEVEL 0x38
45 #define GPIO_INT_POLARITY 0x3c
46 #define GPIO_INTSTATUS 0x40
47 #define GPIO_PORTA_DEBOUNCE 0x48
48 #define GPIO_PORTA_EOI 0x4c
49 #define GPIO_EXT_PORTA 0x50
50 #define GPIO_EXT_PORTB 0x54
51 #define GPIO_EXT_PORTC 0x58
52 #define GPIO_EXT_PORTD 0x5c
53
54 #define DWAPB_DRIVER_NAME "gpio-dwapb"
55 #define DWAPB_MAX_PORTS 4
56
57 #define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */
58 #define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */
59 #define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */
60
61 #define GPIO_REG_OFFSET_V2 1
62
63 #define GPIO_INTMASK_V2 0x44
64 #define GPIO_INTTYPE_LEVEL_V2 0x34
65 #define GPIO_INT_POLARITY_V2 0x38
66 #define GPIO_INTSTATUS_V2 0x3c
67 #define GPIO_PORTA_EOI_V2 0x40
68
69 struct dwapb_gpio;
70
71 #ifdef CONFIG_PM_SLEEP
72 /* Store GPIO context across system-wide suspend/resume transitions */
73 struct dwapb_context {
74 u32 data;
75 u32 dir;
76 u32 ext;
77 u32 int_en;
78 u32 int_mask;
79 u32 int_type;
80 u32 int_pol;
81 u32 int_deb;
82 u32 wake_en;
83 };
84 #endif
85
86 struct dwapb_gpio_port {
87 struct gpio_chip gc;
88 bool is_registered;
89 struct dwapb_gpio *gpio;
90 #ifdef CONFIG_PM_SLEEP
91 struct dwapb_context *ctx;
92 #endif
93 unsigned int idx;
94 };
95
96 struct dwapb_gpio {
97 struct device *dev;
98 void __iomem *regs;
99 struct dwapb_gpio_port *ports;
100 unsigned int nr_ports;
101 struct irq_domain *domain;
102 unsigned int flags;
103 struct reset_control *rst;
104 struct clk *clk;
105 };
106
gpio_reg_v2_convert(unsigned int offset)107 static inline u32 gpio_reg_v2_convert(unsigned int offset)
108 {
109 switch (offset) {
110 case GPIO_INTMASK:
111 return GPIO_INTMASK_V2;
112 case GPIO_INTTYPE_LEVEL:
113 return GPIO_INTTYPE_LEVEL_V2;
114 case GPIO_INT_POLARITY:
115 return GPIO_INT_POLARITY_V2;
116 case GPIO_INTSTATUS:
117 return GPIO_INTSTATUS_V2;
118 case GPIO_PORTA_EOI:
119 return GPIO_PORTA_EOI_V2;
120 }
121
122 return offset;
123 }
124
gpio_reg_convert(struct dwapb_gpio * gpio,unsigned int offset)125 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
126 {
127 if (gpio->flags & GPIO_REG_OFFSET_V2)
128 return gpio_reg_v2_convert(offset);
129
130 return offset;
131 }
132
dwapb_read(struct dwapb_gpio * gpio,unsigned int offset)133 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
134 {
135 struct gpio_chip *gc = &gpio->ports[0].gc;
136 void __iomem *reg_base = gpio->regs;
137
138 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
139 }
140
dwapb_write(struct dwapb_gpio * gpio,unsigned int offset,u32 val)141 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
142 u32 val)
143 {
144 struct gpio_chip *gc = &gpio->ports[0].gc;
145 void __iomem *reg_base = gpio->regs;
146
147 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
148 }
149
dwapb_gpio_to_irq(struct gpio_chip * gc,unsigned offset)150 static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
151 {
152 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
153 struct dwapb_gpio *gpio = port->gpio;
154
155 return irq_find_mapping(gpio->domain, offset);
156 }
157
dwapb_offs_to_port(struct dwapb_gpio * gpio,unsigned int offs)158 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
159 {
160 struct dwapb_gpio_port *port;
161 int i;
162
163 for (i = 0; i < gpio->nr_ports; i++) {
164 port = &gpio->ports[i];
165 if (port->idx == offs / 32)
166 return port;
167 }
168
169 return NULL;
170 }
171
dwapb_toggle_trigger(struct dwapb_gpio * gpio,unsigned int offs)172 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
173 {
174 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
175 struct gpio_chip *gc;
176 u32 pol;
177 int val;
178
179 if (!port)
180 return;
181 gc = &port->gc;
182
183 pol = dwapb_read(gpio, GPIO_INT_POLARITY);
184 /* Just read the current value right out of the data register */
185 val = gc->get(gc, offs % 32);
186 if (val)
187 pol &= ~BIT(offs);
188 else
189 pol |= BIT(offs);
190
191 dwapb_write(gpio, GPIO_INT_POLARITY, pol);
192 }
193
dwapb_do_irq(struct dwapb_gpio * gpio)194 static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
195 {
196 u32 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
197 u32 ret = irq_status;
198
199 while (irq_status) {
200 int hwirq = fls(irq_status) - 1;
201 int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
202
203 generic_handle_irq(gpio_irq);
204 irq_status &= ~BIT(hwirq);
205
206 if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
207 == IRQ_TYPE_EDGE_BOTH)
208 dwapb_toggle_trigger(gpio, hwirq);
209 }
210
211 return ret;
212 }
213
dwapb_irq_handler(struct irq_desc * desc)214 static void dwapb_irq_handler(struct irq_desc *desc)
215 {
216 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
217 struct irq_chip *chip = irq_desc_get_chip(desc);
218
219 dwapb_do_irq(gpio);
220
221 if (chip->irq_eoi)
222 chip->irq_eoi(irq_desc_get_irq_data(desc));
223 }
224
dwapb_irq_enable(struct irq_data * d)225 static void dwapb_irq_enable(struct irq_data *d)
226 {
227 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
228 struct dwapb_gpio *gpio = igc->private;
229 struct gpio_chip *gc = &gpio->ports[0].gc;
230 unsigned long flags;
231 u32 val;
232
233 spin_lock_irqsave(&gc->bgpio_lock, flags);
234 val = dwapb_read(gpio, GPIO_INTEN);
235 val |= BIT(d->hwirq);
236 dwapb_write(gpio, GPIO_INTEN, val);
237 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
238 }
239
dwapb_irq_disable(struct irq_data * d)240 static void dwapb_irq_disable(struct irq_data *d)
241 {
242 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
243 struct dwapb_gpio *gpio = igc->private;
244 struct gpio_chip *gc = &gpio->ports[0].gc;
245 unsigned long flags;
246 u32 val;
247
248 spin_lock_irqsave(&gc->bgpio_lock, flags);
249 val = dwapb_read(gpio, GPIO_INTEN);
250 val &= ~BIT(d->hwirq);
251 dwapb_write(gpio, GPIO_INTEN, val);
252 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
253 }
254
dwapb_irq_reqres(struct irq_data * d)255 static int dwapb_irq_reqres(struct irq_data *d)
256 {
257 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
258 struct dwapb_gpio *gpio = igc->private;
259 struct gpio_chip *gc = &gpio->ports[0].gc;
260 int ret;
261
262 ret = gpiochip_lock_as_irq(gc, irqd_to_hwirq(d));
263 if (ret) {
264 dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
265 irqd_to_hwirq(d));
266 return ret;
267 }
268 return 0;
269 }
270
dwapb_irq_relres(struct irq_data * d)271 static void dwapb_irq_relres(struct irq_data *d)
272 {
273 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
274 struct dwapb_gpio *gpio = igc->private;
275 struct gpio_chip *gc = &gpio->ports[0].gc;
276
277 gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d));
278 }
279
dwapb_irq_set_type(struct irq_data * d,u32 type)280 static int dwapb_irq_set_type(struct irq_data *d, u32 type)
281 {
282 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
283 struct dwapb_gpio *gpio = igc->private;
284 struct gpio_chip *gc = &gpio->ports[0].gc;
285 int bit = d->hwirq;
286 unsigned long level, polarity, flags;
287
288 if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
289 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
290 return -EINVAL;
291
292 spin_lock_irqsave(&gc->bgpio_lock, flags);
293 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
294 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
295
296 switch (type) {
297 case IRQ_TYPE_EDGE_BOTH:
298 level |= BIT(bit);
299 dwapb_toggle_trigger(gpio, bit);
300 break;
301 case IRQ_TYPE_EDGE_RISING:
302 level |= BIT(bit);
303 polarity |= BIT(bit);
304 break;
305 case IRQ_TYPE_EDGE_FALLING:
306 level |= BIT(bit);
307 polarity &= ~BIT(bit);
308 break;
309 case IRQ_TYPE_LEVEL_HIGH:
310 level &= ~BIT(bit);
311 polarity |= BIT(bit);
312 break;
313 case IRQ_TYPE_LEVEL_LOW:
314 level &= ~BIT(bit);
315 polarity &= ~BIT(bit);
316 break;
317 }
318
319 irq_setup_alt_chip(d, type);
320
321 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
322 if (type != IRQ_TYPE_EDGE_BOTH)
323 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
324 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
325
326 return 0;
327 }
328
329 #ifdef CONFIG_PM_SLEEP
dwapb_irq_set_wake(struct irq_data * d,unsigned int enable)330 static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
331 {
332 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
333 struct dwapb_gpio *gpio = igc->private;
334 struct dwapb_context *ctx = gpio->ports[0].ctx;
335
336 if (enable)
337 ctx->wake_en |= BIT(d->hwirq);
338 else
339 ctx->wake_en &= ~BIT(d->hwirq);
340
341 return 0;
342 }
343 #endif
344
dwapb_gpio_set_debounce(struct gpio_chip * gc,unsigned offset,unsigned debounce)345 static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
346 unsigned offset, unsigned debounce)
347 {
348 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
349 struct dwapb_gpio *gpio = port->gpio;
350 unsigned long flags, val_deb;
351 unsigned long mask = BIT(offset);
352
353 spin_lock_irqsave(&gc->bgpio_lock, flags);
354
355 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
356 if (debounce)
357 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask);
358 else
359 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);
360
361 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
362
363 return 0;
364 }
365
dwapb_gpio_set_config(struct gpio_chip * gc,unsigned offset,unsigned long config)366 static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
367 unsigned long config)
368 {
369 u32 debounce;
370
371 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
372 return -ENOTSUPP;
373
374 debounce = pinconf_to_config_argument(config);
375 return dwapb_gpio_set_debounce(gc, offset, debounce);
376 }
377
dwapb_irq_handler_mfd(int irq,void * dev_id)378 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
379 {
380 u32 worked;
381 struct dwapb_gpio *gpio = dev_id;
382
383 worked = dwapb_do_irq(gpio);
384
385 return worked ? IRQ_HANDLED : IRQ_NONE;
386 }
387
dwapb_configure_irqs(struct dwapb_gpio * gpio,struct dwapb_gpio_port * port,struct dwapb_port_property * pp)388 static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
389 struct dwapb_gpio_port *port,
390 struct dwapb_port_property *pp)
391 {
392 struct gpio_chip *gc = &port->gc;
393 struct fwnode_handle *fwnode = pp->fwnode;
394 struct irq_chip_generic *irq_gc = NULL;
395 unsigned int hwirq, ngpio = gc->ngpio;
396 struct irq_chip_type *ct;
397 int err, i;
398
399 gpio->domain = irq_domain_create_linear(fwnode, ngpio,
400 &irq_generic_chip_ops, gpio);
401 if (!gpio->domain)
402 return;
403
404 err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
405 DWAPB_DRIVER_NAME, handle_level_irq,
406 IRQ_NOREQUEST, 0,
407 IRQ_GC_INIT_NESTED_LOCK);
408 if (err) {
409 dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
410 irq_domain_remove(gpio->domain);
411 gpio->domain = NULL;
412 return;
413 }
414
415 irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
416 if (!irq_gc) {
417 irq_domain_remove(gpio->domain);
418 gpio->domain = NULL;
419 return;
420 }
421
422 irq_gc->reg_base = gpio->regs;
423 irq_gc->private = gpio;
424
425 for (i = 0; i < 2; i++) {
426 ct = &irq_gc->chip_types[i];
427 ct->chip.irq_ack = irq_gc_ack_set_bit;
428 ct->chip.irq_mask = irq_gc_mask_set_bit;
429 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
430 ct->chip.irq_set_type = dwapb_irq_set_type;
431 ct->chip.irq_enable = dwapb_irq_enable;
432 ct->chip.irq_disable = dwapb_irq_disable;
433 ct->chip.irq_request_resources = dwapb_irq_reqres;
434 ct->chip.irq_release_resources = dwapb_irq_relres;
435 #ifdef CONFIG_PM_SLEEP
436 ct->chip.irq_set_wake = dwapb_irq_set_wake;
437 #endif
438 ct->regs.ack = gpio_reg_convert(gpio, GPIO_PORTA_EOI);
439 ct->regs.mask = gpio_reg_convert(gpio, GPIO_INTMASK);
440 ct->type = IRQ_TYPE_LEVEL_MASK;
441 }
442
443 irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
444 irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
445 irq_gc->chip_types[1].handler = handle_edge_irq;
446
447 if (!pp->irq_shared) {
448 int i;
449
450 for (i = 0; i < pp->ngpio; i++) {
451 if (pp->irq[i] >= 0)
452 irq_set_chained_handler_and_data(pp->irq[i],
453 dwapb_irq_handler, gpio);
454 }
455 } else {
456 /*
457 * Request a shared IRQ since where MFD would have devices
458 * using the same irq pin
459 */
460 err = devm_request_irq(gpio->dev, pp->irq[0],
461 dwapb_irq_handler_mfd,
462 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
463 if (err) {
464 dev_err(gpio->dev, "error requesting IRQ\n");
465 irq_domain_remove(gpio->domain);
466 gpio->domain = NULL;
467 return;
468 }
469 }
470
471 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
472 irq_create_mapping(gpio->domain, hwirq);
473
474 port->gc.to_irq = dwapb_gpio_to_irq;
475 }
476
dwapb_irq_teardown(struct dwapb_gpio * gpio)477 static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
478 {
479 struct dwapb_gpio_port *port = &gpio->ports[0];
480 struct gpio_chip *gc = &port->gc;
481 unsigned int ngpio = gc->ngpio;
482 irq_hw_number_t hwirq;
483
484 if (!gpio->domain)
485 return;
486
487 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
488 irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
489
490 irq_domain_remove(gpio->domain);
491 gpio->domain = NULL;
492 }
493
dwapb_gpio_add_port(struct dwapb_gpio * gpio,struct dwapb_port_property * pp,unsigned int offs)494 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
495 struct dwapb_port_property *pp,
496 unsigned int offs)
497 {
498 struct dwapb_gpio_port *port;
499 void __iomem *dat, *set, *dirout;
500 int err;
501
502 port = &gpio->ports[offs];
503 port->gpio = gpio;
504 port->idx = pp->idx;
505
506 #ifdef CONFIG_PM_SLEEP
507 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
508 if (!port->ctx)
509 return -ENOMEM;
510 #endif
511
512 dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_STRIDE);
513 set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_STRIDE);
514 dirout = gpio->regs + GPIO_SWPORTA_DDR +
515 (pp->idx * GPIO_SWPORT_DDR_STRIDE);
516
517 /* This registers 32 GPIO lines per port */
518 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
519 NULL, 0);
520 if (err) {
521 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
522 port->idx);
523 return err;
524 }
525
526 #ifdef CONFIG_OF_GPIO
527 port->gc.of_node = to_of_node(pp->fwnode);
528 #endif
529 port->gc.ngpio = pp->ngpio;
530 port->gc.base = pp->gpio_base;
531
532 /* Only port A support debounce */
533 if (pp->idx == 0)
534 port->gc.set_config = dwapb_gpio_set_config;
535
536 if (pp->has_irq)
537 dwapb_configure_irqs(gpio, port, pp);
538
539 err = gpiochip_add_data(&port->gc, port);
540 if (err) {
541 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
542 port->idx);
543 return err;
544 }
545
546 /* Add GPIO-signaled ACPI event support */
547 acpi_gpiochip_request_interrupts(&port->gc);
548
549 port->is_registered = true;
550
551 return 0;
552 }
553
dwapb_gpio_unregister(struct dwapb_gpio * gpio)554 static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
555 {
556 unsigned int m;
557
558 for (m = 0; m < gpio->nr_ports; ++m) {
559 struct dwapb_gpio_port *port = &gpio->ports[m];
560
561 if (!port->is_registered)
562 continue;
563
564 acpi_gpiochip_free_interrupts(&port->gc);
565 gpiochip_remove(&port->gc);
566 }
567 }
568
569 static struct dwapb_platform_data *
dwapb_gpio_get_pdata(struct device * dev)570 dwapb_gpio_get_pdata(struct device *dev)
571 {
572 struct fwnode_handle *fwnode;
573 struct dwapb_platform_data *pdata;
574 struct dwapb_port_property *pp;
575 int nports;
576 int i, j;
577
578 nports = device_get_child_node_count(dev);
579 if (nports == 0)
580 return ERR_PTR(-ENODEV);
581
582 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
583 if (!pdata)
584 return ERR_PTR(-ENOMEM);
585
586 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
587 if (!pdata->properties)
588 return ERR_PTR(-ENOMEM);
589
590 pdata->nports = nports;
591
592 i = 0;
593 device_for_each_child_node(dev, fwnode) {
594 struct device_node *np = NULL;
595
596 pp = &pdata->properties[i++];
597 pp->fwnode = fwnode;
598
599 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
600 pp->idx >= DWAPB_MAX_PORTS) {
601 dev_err(dev,
602 "missing/invalid port index for port%d\n", i);
603 fwnode_handle_put(fwnode);
604 return ERR_PTR(-EINVAL);
605 }
606
607 if (fwnode_property_read_u32(fwnode, "snps,nr-gpios",
608 &pp->ngpio)) {
609 dev_info(dev,
610 "failed to get number of gpios for port%d\n",
611 i);
612 pp->ngpio = 32;
613 }
614
615 pp->irq_shared = false;
616 pp->gpio_base = -1;
617
618 /*
619 * Only port A can provide interrupts in all configurations of
620 * the IP.
621 */
622 if (pp->idx != 0)
623 continue;
624
625 if (dev->of_node && fwnode_property_read_bool(fwnode,
626 "interrupt-controller")) {
627 np = to_of_node(fwnode);
628 }
629
630 for (j = 0; j < pp->ngpio; j++) {
631 pp->irq[j] = -ENXIO;
632
633 if (np)
634 pp->irq[j] = of_irq_get(np, j);
635 else if (has_acpi_companion(dev))
636 pp->irq[j] = platform_get_irq(to_platform_device(dev), j);
637
638 if (pp->irq[j] >= 0)
639 pp->has_irq = true;
640 }
641
642 if (!pp->has_irq)
643 dev_warn(dev, "no irq for port%d\n", pp->idx);
644 }
645
646 return pdata;
647 }
648
649 static const struct of_device_id dwapb_of_match[] = {
650 { .compatible = "snps,dw-apb-gpio", .data = (void *)0},
651 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
652 { /* Sentinel */ }
653 };
654 MODULE_DEVICE_TABLE(of, dwapb_of_match);
655
656 static const struct acpi_device_id dwapb_acpi_match[] = {
657 {"HISI0181", 0},
658 {"APMC0D07", 0},
659 {"APMC0D81", GPIO_REG_OFFSET_V2},
660 { }
661 };
662 MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
663
dwapb_gpio_probe(struct platform_device * pdev)664 static int dwapb_gpio_probe(struct platform_device *pdev)
665 {
666 unsigned int i;
667 struct resource *res;
668 struct dwapb_gpio *gpio;
669 int err;
670 struct device *dev = &pdev->dev;
671 struct dwapb_platform_data *pdata = dev_get_platdata(dev);
672
673 if (!pdata) {
674 pdata = dwapb_gpio_get_pdata(dev);
675 if (IS_ERR(pdata))
676 return PTR_ERR(pdata);
677 }
678
679 if (!pdata->nports)
680 return -ENODEV;
681
682 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
683 if (!gpio)
684 return -ENOMEM;
685
686 gpio->dev = &pdev->dev;
687 gpio->nr_ports = pdata->nports;
688
689 gpio->rst = devm_reset_control_get_optional_shared(dev, NULL);
690 if (IS_ERR(gpio->rst))
691 return PTR_ERR(gpio->rst);
692
693 reset_control_deassert(gpio->rst);
694
695 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
696 sizeof(*gpio->ports), GFP_KERNEL);
697 if (!gpio->ports)
698 return -ENOMEM;
699
700 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
701 gpio->regs = devm_ioremap_resource(&pdev->dev, res);
702 if (IS_ERR(gpio->regs))
703 return PTR_ERR(gpio->regs);
704
705 /* Optional bus clock */
706 gpio->clk = devm_clk_get(&pdev->dev, "bus");
707 if (!IS_ERR(gpio->clk)) {
708 err = clk_prepare_enable(gpio->clk);
709 if (err) {
710 dev_info(&pdev->dev, "Cannot enable clock\n");
711 return err;
712 }
713 }
714
715 gpio->flags = 0;
716 if (dev->of_node) {
717 gpio->flags = (uintptr_t)of_device_get_match_data(dev);
718 } else if (has_acpi_companion(dev)) {
719 const struct acpi_device_id *acpi_id;
720
721 acpi_id = acpi_match_device(dwapb_acpi_match, dev);
722 if (acpi_id) {
723 if (acpi_id->driver_data)
724 gpio->flags = acpi_id->driver_data;
725 }
726 }
727
728 for (i = 0; i < gpio->nr_ports; i++) {
729 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
730 if (err)
731 goto out_unregister;
732 }
733 platform_set_drvdata(pdev, gpio);
734
735 return 0;
736
737 out_unregister:
738 dwapb_gpio_unregister(gpio);
739 dwapb_irq_teardown(gpio);
740 clk_disable_unprepare(gpio->clk);
741
742 return err;
743 }
744
dwapb_gpio_remove(struct platform_device * pdev)745 static int dwapb_gpio_remove(struct platform_device *pdev)
746 {
747 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
748
749 dwapb_gpio_unregister(gpio);
750 dwapb_irq_teardown(gpio);
751 reset_control_assert(gpio->rst);
752 clk_disable_unprepare(gpio->clk);
753
754 return 0;
755 }
756
757 #ifdef CONFIG_PM_SLEEP
dwapb_gpio_suspend(struct device * dev)758 static int dwapb_gpio_suspend(struct device *dev)
759 {
760 struct platform_device *pdev = to_platform_device(dev);
761 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
762 struct gpio_chip *gc = &gpio->ports[0].gc;
763 unsigned long flags;
764 int i;
765
766 spin_lock_irqsave(&gc->bgpio_lock, flags);
767 for (i = 0; i < gpio->nr_ports; i++) {
768 unsigned int offset;
769 unsigned int idx = gpio->ports[i].idx;
770 struct dwapb_context *ctx = gpio->ports[i].ctx;
771
772 BUG_ON(!ctx);
773
774 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
775 ctx->dir = dwapb_read(gpio, offset);
776
777 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
778 ctx->data = dwapb_read(gpio, offset);
779
780 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
781 ctx->ext = dwapb_read(gpio, offset);
782
783 /* Only port A can provide interrupts */
784 if (idx == 0) {
785 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
786 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
787 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
788 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
789 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
790
791 /* Mask out interrupts */
792 dwapb_write(gpio, GPIO_INTMASK,
793 0xffffffff & ~ctx->wake_en);
794 }
795 }
796 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
797
798 clk_disable_unprepare(gpio->clk);
799
800 return 0;
801 }
802
dwapb_gpio_resume(struct device * dev)803 static int dwapb_gpio_resume(struct device *dev)
804 {
805 struct platform_device *pdev = to_platform_device(dev);
806 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
807 struct gpio_chip *gc = &gpio->ports[0].gc;
808 unsigned long flags;
809 int i;
810
811 if (!IS_ERR(gpio->clk))
812 clk_prepare_enable(gpio->clk);
813
814 spin_lock_irqsave(&gc->bgpio_lock, flags);
815 for (i = 0; i < gpio->nr_ports; i++) {
816 unsigned int offset;
817 unsigned int idx = gpio->ports[i].idx;
818 struct dwapb_context *ctx = gpio->ports[i].ctx;
819
820 BUG_ON(!ctx);
821
822 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
823 dwapb_write(gpio, offset, ctx->data);
824
825 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
826 dwapb_write(gpio, offset, ctx->dir);
827
828 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
829 dwapb_write(gpio, offset, ctx->ext);
830
831 /* Only port A can provide interrupts */
832 if (idx == 0) {
833 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
834 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
835 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
836 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
837 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
838
839 /* Clear out spurious interrupts */
840 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
841 }
842 }
843 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
844
845 return 0;
846 }
847 #endif
848
849 static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
850 dwapb_gpio_resume);
851
852 static struct platform_driver dwapb_gpio_driver = {
853 .driver = {
854 .name = DWAPB_DRIVER_NAME,
855 .pm = &dwapb_gpio_pm_ops,
856 .of_match_table = of_match_ptr(dwapb_of_match),
857 .acpi_match_table = ACPI_PTR(dwapb_acpi_match),
858 },
859 .probe = dwapb_gpio_probe,
860 .remove = dwapb_gpio_remove,
861 };
862
863 module_platform_driver(dwapb_gpio_driver);
864
865 MODULE_LICENSE("GPL");
866 MODULE_AUTHOR("Jamie Iles");
867 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
868 MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME);
869