1 /*
2  * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
3  *
4  * Copyright (C) 2010 Extreme Engineering Solutions.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19  */
20 
21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22 
23 #include <linux/ioport.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/gpio/driver.h>
27 #include <linux/platform_device.h>
28 #include <linux/mfd/lpc_ich.h>
29 #include <linux/bitops.h>
30 
31 #define DRV_NAME "gpio_ich"
32 
33 /*
34  * GPIO register offsets in GPIO I/O space.
35  * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
36  * LVLx registers.  Logic in the read/write functions takes a register and
37  * an absolute bit number and determines the proper register offset and bit
38  * number in that register.  For example, to read the value of GPIO bit 50
39  * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
40  * bit 18 (50%32).
41  */
42 enum GPIO_REG {
43 	GPIO_USE_SEL = 0,
44 	GPIO_IO_SEL,
45 	GPIO_LVL,
46 	GPO_BLINK
47 };
48 
49 static const u8 ichx_regs[4][3] = {
50 	{0x00, 0x30, 0x40},	/* USE_SEL[1-3] offsets */
51 	{0x04, 0x34, 0x44},	/* IO_SEL[1-3] offsets */
52 	{0x0c, 0x38, 0x48},	/* LVL[1-3] offsets */
53 	{0x18, 0x18, 0x18},	/* BLINK offset */
54 };
55 
56 static const u8 ichx_reglen[3] = {
57 	0x30, 0x10, 0x10,
58 };
59 
60 static const u8 avoton_regs[4][3] = {
61 	{0x00, 0x80, 0x00},
62 	{0x04, 0x84, 0x00},
63 	{0x08, 0x88, 0x00},
64 };
65 
66 static const u8 avoton_reglen[3] = {
67 	0x10, 0x10, 0x00,
68 };
69 
70 #define ICHX_WRITE(val, reg, base_res)	outl(val, (reg) + (base_res)->start)
71 #define ICHX_READ(reg, base_res)	inl((reg) + (base_res)->start)
72 
73 struct ichx_desc {
74 	/* Max GPIO pins the chipset can have */
75 	uint ngpio;
76 
77 	/* chipset registers */
78 	const u8 (*regs)[3];
79 	const u8 *reglen;
80 
81 	/* GPO_BLINK is available on this chipset */
82 	bool have_blink;
83 
84 	/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
85 	bool uses_gpe0;
86 
87 	/* USE_SEL is bogus on some chipsets, eg 3100 */
88 	u32 use_sel_ignore[3];
89 
90 	/* Some chipsets have quirks, let these use their own request/get */
91 	int (*request)(struct gpio_chip *chip, unsigned offset);
92 	int (*get)(struct gpio_chip *chip, unsigned offset);
93 
94 	/*
95 	 * Some chipsets don't let reading output values on GPIO_LVL register
96 	 * this option allows driver caching written output values
97 	 */
98 	bool use_outlvl_cache;
99 };
100 
101 static struct {
102 	spinlock_t lock;
103 	struct platform_device *dev;
104 	struct gpio_chip chip;
105 	struct resource *gpio_base;	/* GPIO IO base */
106 	struct resource *pm_base;	/* Power Mangagment IO base */
107 	struct ichx_desc *desc;	/* Pointer to chipset-specific description */
108 	u32 orig_gpio_ctrl;	/* Orig CTRL value, used to restore on exit */
109 	u8 use_gpio;		/* Which GPIO groups are usable */
110 	int outlvl_cache[3];	/* cached output values */
111 } ichx_priv;
112 
113 static int modparam_gpiobase = -1;	/* dynamic */
114 module_param_named(gpiobase, modparam_gpiobase, int, 0444);
115 MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
116 			   "which is the default.");
117 
ichx_write_bit(int reg,unsigned nr,int val,int verify)118 static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
119 {
120 	unsigned long flags;
121 	u32 data, tmp;
122 	int reg_nr = nr / 32;
123 	int bit = nr & 0x1f;
124 	int ret = 0;
125 
126 	spin_lock_irqsave(&ichx_priv.lock, flags);
127 
128 	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
129 		data = ichx_priv.outlvl_cache[reg_nr];
130 	else
131 		data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
132 				 ichx_priv.gpio_base);
133 
134 	if (val)
135 		data |= BIT(bit);
136 	else
137 		data &= ~BIT(bit);
138 	ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
139 			 ichx_priv.gpio_base);
140 	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
141 		ichx_priv.outlvl_cache[reg_nr] = data;
142 
143 	tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
144 			ichx_priv.gpio_base);
145 	if (verify && data != tmp)
146 		ret = -EPERM;
147 
148 	spin_unlock_irqrestore(&ichx_priv.lock, flags);
149 
150 	return ret;
151 }
152 
ichx_read_bit(int reg,unsigned nr)153 static int ichx_read_bit(int reg, unsigned nr)
154 {
155 	unsigned long flags;
156 	u32 data;
157 	int reg_nr = nr / 32;
158 	int bit = nr & 0x1f;
159 
160 	spin_lock_irqsave(&ichx_priv.lock, flags);
161 
162 	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
163 			 ichx_priv.gpio_base);
164 
165 	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
166 		data = ichx_priv.outlvl_cache[reg_nr] | data;
167 
168 	spin_unlock_irqrestore(&ichx_priv.lock, flags);
169 
170 	return !!(data & BIT(bit));
171 }
172 
ichx_gpio_check_available(struct gpio_chip * gpio,unsigned nr)173 static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
174 {
175 	return !!(ichx_priv.use_gpio & BIT(nr / 32));
176 }
177 
ichx_gpio_get_direction(struct gpio_chip * gpio,unsigned nr)178 static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned nr)
179 {
180 	return ichx_read_bit(GPIO_IO_SEL, nr);
181 }
182 
ichx_gpio_direction_input(struct gpio_chip * gpio,unsigned nr)183 static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
184 {
185 	/*
186 	 * Try setting pin as an input and verify it worked since many pins
187 	 * are output-only.
188 	 */
189 	if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
190 		return -EINVAL;
191 
192 	return 0;
193 }
194 
ichx_gpio_direction_output(struct gpio_chip * gpio,unsigned nr,int val)195 static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
196 					int val)
197 {
198 	/* Disable blink hardware which is available for GPIOs from 0 to 31. */
199 	if (nr < 32 && ichx_priv.desc->have_blink)
200 		ichx_write_bit(GPO_BLINK, nr, 0, 0);
201 
202 	/* Set GPIO output value. */
203 	ichx_write_bit(GPIO_LVL, nr, val, 0);
204 
205 	/*
206 	 * Try setting pin as an output and verify it worked since many pins
207 	 * are input-only.
208 	 */
209 	if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
210 		return -EINVAL;
211 
212 	return 0;
213 }
214 
ichx_gpio_get(struct gpio_chip * chip,unsigned nr)215 static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
216 {
217 	return ichx_read_bit(GPIO_LVL, nr);
218 }
219 
ich6_gpio_get(struct gpio_chip * chip,unsigned nr)220 static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
221 {
222 	unsigned long flags;
223 	u32 data;
224 
225 	/*
226 	 * GPI 0 - 15 need to be read from the power management registers on
227 	 * a ICH6/3100 bridge.
228 	 */
229 	if (nr < 16) {
230 		if (!ichx_priv.pm_base)
231 			return -ENXIO;
232 
233 		spin_lock_irqsave(&ichx_priv.lock, flags);
234 
235 		/* GPI 0 - 15 are latched, write 1 to clear*/
236 		ICHX_WRITE(BIT(16 + nr), 0, ichx_priv.pm_base);
237 		data = ICHX_READ(0, ichx_priv.pm_base);
238 
239 		spin_unlock_irqrestore(&ichx_priv.lock, flags);
240 
241 		return !!((data >> 16) & BIT(nr));
242 	} else {
243 		return ichx_gpio_get(chip, nr);
244 	}
245 }
246 
ichx_gpio_request(struct gpio_chip * chip,unsigned nr)247 static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
248 {
249 	if (!ichx_gpio_check_available(chip, nr))
250 		return -ENXIO;
251 
252 	/*
253 	 * Note we assume the BIOS properly set a bridge's USE value.  Some
254 	 * chips (eg Intel 3100) have bogus USE values though, so first see if
255 	 * the chipset's USE value can be trusted for this specific bit.
256 	 * If it can't be trusted, assume that the pin can be used as a GPIO.
257 	 */
258 	if (ichx_priv.desc->use_sel_ignore[nr / 32] & BIT(nr & 0x1f))
259 		return 0;
260 
261 	return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
262 }
263 
ich6_gpio_request(struct gpio_chip * chip,unsigned nr)264 static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
265 {
266 	/*
267 	 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
268 	 * bridge as they are controlled by USE register bits 0 and 1.  See
269 	 * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
270 	 * additional info.
271 	 */
272 	if (nr == 16 || nr == 17)
273 		nr -= 16;
274 
275 	return ichx_gpio_request(chip, nr);
276 }
277 
ichx_gpio_set(struct gpio_chip * chip,unsigned nr,int val)278 static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
279 {
280 	ichx_write_bit(GPIO_LVL, nr, val, 0);
281 }
282 
ichx_gpiolib_setup(struct gpio_chip * chip)283 static void ichx_gpiolib_setup(struct gpio_chip *chip)
284 {
285 	chip->owner = THIS_MODULE;
286 	chip->label = DRV_NAME;
287 	chip->parent = &ichx_priv.dev->dev;
288 
289 	/* Allow chip-specific overrides of request()/get() */
290 	chip->request = ichx_priv.desc->request ?
291 		ichx_priv.desc->request : ichx_gpio_request;
292 	chip->get = ichx_priv.desc->get ?
293 		ichx_priv.desc->get : ichx_gpio_get;
294 
295 	chip->set = ichx_gpio_set;
296 	chip->get_direction = ichx_gpio_get_direction;
297 	chip->direction_input = ichx_gpio_direction_input;
298 	chip->direction_output = ichx_gpio_direction_output;
299 	chip->base = modparam_gpiobase;
300 	chip->ngpio = ichx_priv.desc->ngpio;
301 	chip->can_sleep = false;
302 	chip->dbg_show = NULL;
303 }
304 
305 /* ICH6-based, 631xesb-based */
306 static struct ichx_desc ich6_desc = {
307 	/* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
308 	.request = ich6_gpio_request,
309 	.get = ich6_gpio_get,
310 
311 	/* GPIO 0-15 are read in the GPE0_STS PM register */
312 	.uses_gpe0 = true,
313 
314 	.ngpio = 50,
315 	.have_blink = true,
316 	.regs = ichx_regs,
317 	.reglen = ichx_reglen,
318 };
319 
320 /* Intel 3100 */
321 static struct ichx_desc i3100_desc = {
322 	/*
323 	 * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
324 	 * the Intel 3100.  See "Table 712. GPIO Summary Table" of 3100
325 	 * Datasheet for more info.
326 	 */
327 	.use_sel_ignore = {0x00130000, 0x00010000, 0x0},
328 
329 	/* The 3100 needs fixups for GPIO 0 - 17 */
330 	.request = ich6_gpio_request,
331 	.get = ich6_gpio_get,
332 
333 	/* GPIO 0-15 are read in the GPE0_STS PM register */
334 	.uses_gpe0 = true,
335 
336 	.ngpio = 50,
337 	.regs = ichx_regs,
338 	.reglen = ichx_reglen,
339 };
340 
341 /* ICH7 and ICH8-based */
342 static struct ichx_desc ich7_desc = {
343 	.ngpio = 50,
344 	.have_blink = true,
345 	.regs = ichx_regs,
346 	.reglen = ichx_reglen,
347 };
348 
349 /* ICH9-based */
350 static struct ichx_desc ich9_desc = {
351 	.ngpio = 61,
352 	.have_blink = true,
353 	.regs = ichx_regs,
354 	.reglen = ichx_reglen,
355 };
356 
357 /* ICH10-based - Consumer/corporate versions have different amount of GPIO */
358 static struct ichx_desc ich10_cons_desc = {
359 	.ngpio = 61,
360 	.have_blink = true,
361 	.regs = ichx_regs,
362 	.reglen = ichx_reglen,
363 };
364 static struct ichx_desc ich10_corp_desc = {
365 	.ngpio = 72,
366 	.have_blink = true,
367 	.regs = ichx_regs,
368 	.reglen = ichx_reglen,
369 };
370 
371 /* Intel 5 series, 6 series, 3400 series, and C200 series */
372 static struct ichx_desc intel5_desc = {
373 	.ngpio = 76,
374 	.regs = ichx_regs,
375 	.reglen = ichx_reglen,
376 };
377 
378 /* Avoton */
379 static struct ichx_desc avoton_desc = {
380 	/* Avoton has only 59 GPIOs, but we assume the first set of register
381 	 * (Core) has 32 instead of 31 to keep gpio-ich compliance
382 	 */
383 	.ngpio = 60,
384 	.regs = avoton_regs,
385 	.reglen = avoton_reglen,
386 	.use_outlvl_cache = true,
387 };
388 
ichx_gpio_request_regions(struct device * dev,struct resource * res_base,const char * name,u8 use_gpio)389 static int ichx_gpio_request_regions(struct device *dev,
390 	struct resource *res_base, const char *name, u8 use_gpio)
391 {
392 	int i;
393 
394 	if (!res_base || !res_base->start || !res_base->end)
395 		return -ENODEV;
396 
397 	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
398 		if (!(use_gpio & BIT(i)))
399 			continue;
400 		if (!devm_request_region(dev,
401 				res_base->start + ichx_priv.desc->regs[0][i],
402 				ichx_priv.desc->reglen[i], name))
403 			return -EBUSY;
404 	}
405 	return 0;
406 }
407 
ichx_gpio_probe(struct platform_device * pdev)408 static int ichx_gpio_probe(struct platform_device *pdev)
409 {
410 	struct resource *res_base, *res_pm;
411 	int err;
412 	struct lpc_ich_info *ich_info = dev_get_platdata(&pdev->dev);
413 
414 	if (!ich_info)
415 		return -ENODEV;
416 
417 	ichx_priv.dev = pdev;
418 
419 	switch (ich_info->gpio_version) {
420 	case ICH_I3100_GPIO:
421 		ichx_priv.desc = &i3100_desc;
422 		break;
423 	case ICH_V5_GPIO:
424 		ichx_priv.desc = &intel5_desc;
425 		break;
426 	case ICH_V6_GPIO:
427 		ichx_priv.desc = &ich6_desc;
428 		break;
429 	case ICH_V7_GPIO:
430 		ichx_priv.desc = &ich7_desc;
431 		break;
432 	case ICH_V9_GPIO:
433 		ichx_priv.desc = &ich9_desc;
434 		break;
435 	case ICH_V10CORP_GPIO:
436 		ichx_priv.desc = &ich10_corp_desc;
437 		break;
438 	case ICH_V10CONS_GPIO:
439 		ichx_priv.desc = &ich10_cons_desc;
440 		break;
441 	case AVOTON_GPIO:
442 		ichx_priv.desc = &avoton_desc;
443 		break;
444 	default:
445 		return -ENODEV;
446 	}
447 
448 	spin_lock_init(&ichx_priv.lock);
449 	res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
450 	ichx_priv.use_gpio = ich_info->use_gpio;
451 	err = ichx_gpio_request_regions(&pdev->dev, res_base, pdev->name,
452 					ichx_priv.use_gpio);
453 	if (err)
454 		return err;
455 
456 	ichx_priv.gpio_base = res_base;
457 
458 	/*
459 	 * If necessary, determine the I/O address of ACPI/power management
460 	 * registers which are needed to read the the GPE0 register for GPI pins
461 	 * 0 - 15 on some chipsets.
462 	 */
463 	if (!ichx_priv.desc->uses_gpe0)
464 		goto init;
465 
466 	res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
467 	if (!res_pm) {
468 		pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
469 		goto init;
470 	}
471 
472 	if (!devm_request_region(&pdev->dev, res_pm->start,
473 			resource_size(res_pm), pdev->name)) {
474 		pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
475 		goto init;
476 	}
477 
478 	ichx_priv.pm_base = res_pm;
479 
480 init:
481 	ichx_gpiolib_setup(&ichx_priv.chip);
482 	err = gpiochip_add_data(&ichx_priv.chip, NULL);
483 	if (err) {
484 		pr_err("Failed to register GPIOs\n");
485 		return err;
486 	}
487 
488 	pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
489 	       ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);
490 
491 	return 0;
492 }
493 
ichx_gpio_remove(struct platform_device * pdev)494 static int ichx_gpio_remove(struct platform_device *pdev)
495 {
496 	gpiochip_remove(&ichx_priv.chip);
497 
498 	return 0;
499 }
500 
501 static struct platform_driver ichx_gpio_driver = {
502 	.driver		= {
503 		.name	= DRV_NAME,
504 	},
505 	.probe		= ichx_gpio_probe,
506 	.remove		= ichx_gpio_remove,
507 };
508 
509 module_platform_driver(ichx_gpio_driver);
510 
511 MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
512 MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
513 MODULE_LICENSE("GPL");
514 MODULE_ALIAS("platform:"DRV_NAME);
515