1 /*
2 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
3 *
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
5 * Copyright (C) 2016 Freescale Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/spinlock.h>
15 #include <linux/io.h>
16 #include <linux/of.h>
17 #include <linux/of_gpio.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_platform.h>
21 #include <linux/slab.h>
22 #include <linux/irq.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/bitops.h>
25
26 #define MPC8XXX_GPIO_PINS 32
27
28 #define GPIO_DIR 0x00
29 #define GPIO_ODR 0x04
30 #define GPIO_DAT 0x08
31 #define GPIO_IER 0x0c
32 #define GPIO_IMR 0x10
33 #define GPIO_ICR 0x14
34 #define GPIO_ICR2 0x18
35
36 struct mpc8xxx_gpio_chip {
37 struct gpio_chip gc;
38 void __iomem *regs;
39 raw_spinlock_t lock;
40
41 int (*direction_output)(struct gpio_chip *chip,
42 unsigned offset, int value);
43
44 struct irq_domain *irq;
45 unsigned int irqn;
46 };
47
48 /*
49 * This hardware has a big endian bit assignment such that GPIO line 0 is
50 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
51 * This inline helper give the right bitmask for a certain line.
52 */
mpc_pin2mask(unsigned int offset)53 static inline u32 mpc_pin2mask(unsigned int offset)
54 {
55 return BIT(31 - offset);
56 }
57
58 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
59 * defined as output cannot be determined by reading GPDAT register,
60 * so we use shadow data register instead. The status of input pins
61 * is determined by reading GPDAT register.
62 */
mpc8572_gpio_get(struct gpio_chip * gc,unsigned int gpio)63 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
64 {
65 u32 val;
66 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
67 u32 out_mask, out_shadow;
68
69 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
70 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
71 out_shadow = gc->bgpio_data & out_mask;
72
73 return !!((val | out_shadow) & mpc_pin2mask(gpio));
74 }
75
mpc5121_gpio_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)76 static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
77 unsigned int gpio, int val)
78 {
79 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
80 /* GPIO 28..31 are input only on MPC5121 */
81 if (gpio >= 28)
82 return -EINVAL;
83
84 return mpc8xxx_gc->direction_output(gc, gpio, val);
85 }
86
mpc5125_gpio_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)87 static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
88 unsigned int gpio, int val)
89 {
90 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
91 /* GPIO 0..3 are input only on MPC5125 */
92 if (gpio <= 3)
93 return -EINVAL;
94
95 return mpc8xxx_gc->direction_output(gc, gpio, val);
96 }
97
mpc8xxx_gpio_to_irq(struct gpio_chip * gc,unsigned offset)98 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
99 {
100 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
101
102 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
103 return irq_create_mapping(mpc8xxx_gc->irq, offset);
104 else
105 return -ENXIO;
106 }
107
mpc8xxx_gpio_irq_cascade(struct irq_desc * desc)108 static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc)
109 {
110 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
111 struct irq_chip *chip = irq_desc_get_chip(desc);
112 struct gpio_chip *gc = &mpc8xxx_gc->gc;
113 unsigned int mask;
114
115 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
116 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
117 if (mask)
118 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
119 32 - ffs(mask)));
120 if (chip->irq_eoi)
121 chip->irq_eoi(&desc->irq_data);
122 }
123
mpc8xxx_irq_unmask(struct irq_data * d)124 static void mpc8xxx_irq_unmask(struct irq_data *d)
125 {
126 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
127 struct gpio_chip *gc = &mpc8xxx_gc->gc;
128 unsigned long flags;
129
130 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
131
132 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
133 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
134 | mpc_pin2mask(irqd_to_hwirq(d)));
135
136 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
137 }
138
mpc8xxx_irq_mask(struct irq_data * d)139 static void mpc8xxx_irq_mask(struct irq_data *d)
140 {
141 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
142 struct gpio_chip *gc = &mpc8xxx_gc->gc;
143 unsigned long flags;
144
145 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
146
147 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
148 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
149 & ~mpc_pin2mask(irqd_to_hwirq(d)));
150
151 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
152 }
153
mpc8xxx_irq_ack(struct irq_data * d)154 static void mpc8xxx_irq_ack(struct irq_data *d)
155 {
156 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
157 struct gpio_chip *gc = &mpc8xxx_gc->gc;
158
159 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
160 mpc_pin2mask(irqd_to_hwirq(d)));
161 }
162
mpc8xxx_irq_set_type(struct irq_data * d,unsigned int flow_type)163 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
164 {
165 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
166 struct gpio_chip *gc = &mpc8xxx_gc->gc;
167 unsigned long flags;
168
169 switch (flow_type) {
170 case IRQ_TYPE_EDGE_FALLING:
171 case IRQ_TYPE_LEVEL_LOW:
172 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
173 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
174 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
175 | mpc_pin2mask(irqd_to_hwirq(d)));
176 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
177 break;
178
179 case IRQ_TYPE_EDGE_BOTH:
180 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
181 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
182 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
183 & ~mpc_pin2mask(irqd_to_hwirq(d)));
184 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
185 break;
186
187 default:
188 return -EINVAL;
189 }
190
191 return 0;
192 }
193
mpc512x_irq_set_type(struct irq_data * d,unsigned int flow_type)194 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
195 {
196 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
197 struct gpio_chip *gc = &mpc8xxx_gc->gc;
198 unsigned long gpio = irqd_to_hwirq(d);
199 void __iomem *reg;
200 unsigned int shift;
201 unsigned long flags;
202
203 if (gpio < 16) {
204 reg = mpc8xxx_gc->regs + GPIO_ICR;
205 shift = (15 - gpio) * 2;
206 } else {
207 reg = mpc8xxx_gc->regs + GPIO_ICR2;
208 shift = (15 - (gpio % 16)) * 2;
209 }
210
211 switch (flow_type) {
212 case IRQ_TYPE_EDGE_FALLING:
213 case IRQ_TYPE_LEVEL_LOW:
214 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
215 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
216 | (2 << shift));
217 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
218 break;
219
220 case IRQ_TYPE_EDGE_RISING:
221 case IRQ_TYPE_LEVEL_HIGH:
222 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
223 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
224 | (1 << shift));
225 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
226 break;
227
228 case IRQ_TYPE_EDGE_BOTH:
229 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
230 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
231 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
232 break;
233
234 default:
235 return -EINVAL;
236 }
237
238 return 0;
239 }
240
241 static struct irq_chip mpc8xxx_irq_chip = {
242 .name = "mpc8xxx-gpio",
243 .irq_unmask = mpc8xxx_irq_unmask,
244 .irq_mask = mpc8xxx_irq_mask,
245 .irq_ack = mpc8xxx_irq_ack,
246 /* this might get overwritten in mpc8xxx_probe() */
247 .irq_set_type = mpc8xxx_irq_set_type,
248 };
249
mpc8xxx_gpio_irq_map(struct irq_domain * h,unsigned int irq,irq_hw_number_t hwirq)250 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
251 irq_hw_number_t hwirq)
252 {
253 irq_set_chip_data(irq, h->host_data);
254 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
255
256 return 0;
257 }
258
259 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
260 .map = mpc8xxx_gpio_irq_map,
261 .xlate = irq_domain_xlate_twocell,
262 };
263
264 struct mpc8xxx_gpio_devtype {
265 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
266 int (*gpio_get)(struct gpio_chip *, unsigned int);
267 int (*irq_set_type)(struct irq_data *, unsigned int);
268 };
269
270 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
271 .gpio_dir_out = mpc5121_gpio_dir_out,
272 .irq_set_type = mpc512x_irq_set_type,
273 };
274
275 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
276 .gpio_dir_out = mpc5125_gpio_dir_out,
277 .irq_set_type = mpc512x_irq_set_type,
278 };
279
280 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
281 .gpio_get = mpc8572_gpio_get,
282 };
283
284 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
285 .irq_set_type = mpc8xxx_irq_set_type,
286 };
287
288 static const struct of_device_id mpc8xxx_gpio_ids[] = {
289 { .compatible = "fsl,mpc8349-gpio", },
290 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
291 { .compatible = "fsl,mpc8610-gpio", },
292 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
293 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
294 { .compatible = "fsl,pq3-gpio", },
295 { .compatible = "fsl,qoriq-gpio", },
296 {}
297 };
298
mpc8xxx_probe(struct platform_device * pdev)299 static int mpc8xxx_probe(struct platform_device *pdev)
300 {
301 struct device_node *np = pdev->dev.of_node;
302 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
303 struct gpio_chip *gc;
304 const struct mpc8xxx_gpio_devtype *devtype =
305 of_device_get_match_data(&pdev->dev);
306 int ret;
307
308 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
309 if (!mpc8xxx_gc)
310 return -ENOMEM;
311
312 platform_set_drvdata(pdev, mpc8xxx_gc);
313
314 raw_spin_lock_init(&mpc8xxx_gc->lock);
315
316 mpc8xxx_gc->regs = of_iomap(np, 0);
317 if (!mpc8xxx_gc->regs)
318 return -ENOMEM;
319
320 gc = &mpc8xxx_gc->gc;
321 gc->parent = &pdev->dev;
322
323 if (of_property_read_bool(np, "little-endian")) {
324 ret = bgpio_init(gc, &pdev->dev, 4,
325 mpc8xxx_gc->regs + GPIO_DAT,
326 NULL, NULL,
327 mpc8xxx_gc->regs + GPIO_DIR, NULL,
328 BGPIOF_BIG_ENDIAN);
329 if (ret)
330 goto err;
331 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
332 } else {
333 ret = bgpio_init(gc, &pdev->dev, 4,
334 mpc8xxx_gc->regs + GPIO_DAT,
335 NULL, NULL,
336 mpc8xxx_gc->regs + GPIO_DIR, NULL,
337 BGPIOF_BIG_ENDIAN
338 | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
339 if (ret)
340 goto err;
341 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
342 }
343
344 mpc8xxx_gc->direction_output = gc->direction_output;
345
346 if (!devtype)
347 devtype = &mpc8xxx_gpio_devtype_default;
348
349 /*
350 * It's assumed that only a single type of gpio controller is available
351 * on the current machine, so overwriting global data is fine.
352 */
353 if (devtype->irq_set_type)
354 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
355
356 if (devtype->gpio_dir_out)
357 gc->direction_output = devtype->gpio_dir_out;
358 if (devtype->gpio_get)
359 gc->get = devtype->gpio_get;
360
361 gc->to_irq = mpc8xxx_gpio_to_irq;
362
363 ret = gpiochip_add_data(gc, mpc8xxx_gc);
364 if (ret) {
365 pr_err("%pOF: GPIO chip registration failed with status %d\n",
366 np, ret);
367 goto err;
368 }
369
370 mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
371 if (!mpc8xxx_gc->irqn)
372 return 0;
373
374 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
375 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
376 if (!mpc8xxx_gc->irq)
377 return 0;
378
379 /* ack and mask all irqs */
380 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
381 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
382
383 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
384 mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
385 return 0;
386 err:
387 iounmap(mpc8xxx_gc->regs);
388 return ret;
389 }
390
mpc8xxx_remove(struct platform_device * pdev)391 static int mpc8xxx_remove(struct platform_device *pdev)
392 {
393 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
394
395 if (mpc8xxx_gc->irq) {
396 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
397 irq_domain_remove(mpc8xxx_gc->irq);
398 }
399
400 gpiochip_remove(&mpc8xxx_gc->gc);
401 iounmap(mpc8xxx_gc->regs);
402
403 return 0;
404 }
405
406 static struct platform_driver mpc8xxx_plat_driver = {
407 .probe = mpc8xxx_probe,
408 .remove = mpc8xxx_remove,
409 .driver = {
410 .name = "gpio-mpc8xxx",
411 .of_match_table = mpc8xxx_gpio_ids,
412 },
413 };
414
mpc8xxx_init(void)415 static int __init mpc8xxx_init(void)
416 {
417 return platform_driver_register(&mpc8xxx_plat_driver);
418 }
419
420 arch_initcall(mpc8xxx_init);
421