1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2018 Spreadtrum Communications Inc.
4 * Copyright (C) 2018 Linaro Ltd.
5 */
6
7 #include <linux/bitops.h>
8 #include <linux/gpio/driver.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <linux/spinlock.h>
14
15 /* GPIO registers definition */
16 #define SPRD_GPIO_DATA 0x0
17 #define SPRD_GPIO_DMSK 0x4
18 #define SPRD_GPIO_DIR 0x8
19 #define SPRD_GPIO_IS 0xc
20 #define SPRD_GPIO_IBE 0x10
21 #define SPRD_GPIO_IEV 0x14
22 #define SPRD_GPIO_IE 0x18
23 #define SPRD_GPIO_RIS 0x1c
24 #define SPRD_GPIO_MIS 0x20
25 #define SPRD_GPIO_IC 0x24
26 #define SPRD_GPIO_INEN 0x28
27
28 /* We have 16 banks GPIOs and each bank contain 16 GPIOs */
29 #define SPRD_GPIO_BANK_NR 16
30 #define SPRD_GPIO_NR 256
31 #define SPRD_GPIO_BANK_SIZE 0x80
32 #define SPRD_GPIO_BANK_MASK GENMASK(15, 0)
33 #define SPRD_GPIO_BIT(x) ((x) & (SPRD_GPIO_BANK_NR - 1))
34
35 struct sprd_gpio {
36 struct gpio_chip chip;
37 void __iomem *base;
38 spinlock_t lock;
39 int irq;
40 };
41
sprd_gpio_bank_base(struct sprd_gpio * sprd_gpio,unsigned int bank)42 static inline void __iomem *sprd_gpio_bank_base(struct sprd_gpio *sprd_gpio,
43 unsigned int bank)
44 {
45 return sprd_gpio->base + SPRD_GPIO_BANK_SIZE * bank;
46 }
47
sprd_gpio_update(struct gpio_chip * chip,unsigned int offset,u16 reg,int val)48 static void sprd_gpio_update(struct gpio_chip *chip, unsigned int offset,
49 u16 reg, int val)
50 {
51 struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip);
52 void __iomem *base = sprd_gpio_bank_base(sprd_gpio,
53 offset / SPRD_GPIO_BANK_NR);
54 unsigned long flags;
55 u32 tmp;
56
57 spin_lock_irqsave(&sprd_gpio->lock, flags);
58 tmp = readl_relaxed(base + reg);
59
60 if (val)
61 tmp |= BIT(SPRD_GPIO_BIT(offset));
62 else
63 tmp &= ~BIT(SPRD_GPIO_BIT(offset));
64
65 writel_relaxed(tmp, base + reg);
66 spin_unlock_irqrestore(&sprd_gpio->lock, flags);
67 }
68
sprd_gpio_read(struct gpio_chip * chip,unsigned int offset,u16 reg)69 static int sprd_gpio_read(struct gpio_chip *chip, unsigned int offset, u16 reg)
70 {
71 struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip);
72 void __iomem *base = sprd_gpio_bank_base(sprd_gpio,
73 offset / SPRD_GPIO_BANK_NR);
74
75 return !!(readl_relaxed(base + reg) & BIT(SPRD_GPIO_BIT(offset)));
76 }
77
sprd_gpio_request(struct gpio_chip * chip,unsigned int offset)78 static int sprd_gpio_request(struct gpio_chip *chip, unsigned int offset)
79 {
80 sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, 1);
81 return 0;
82 }
83
sprd_gpio_free(struct gpio_chip * chip,unsigned int offset)84 static void sprd_gpio_free(struct gpio_chip *chip, unsigned int offset)
85 {
86 sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, 0);
87 }
88
sprd_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)89 static int sprd_gpio_direction_input(struct gpio_chip *chip,
90 unsigned int offset)
91 {
92 sprd_gpio_update(chip, offset, SPRD_GPIO_DIR, 0);
93 sprd_gpio_update(chip, offset, SPRD_GPIO_INEN, 1);
94 return 0;
95 }
96
sprd_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)97 static int sprd_gpio_direction_output(struct gpio_chip *chip,
98 unsigned int offset, int value)
99 {
100 sprd_gpio_update(chip, offset, SPRD_GPIO_DIR, 1);
101 sprd_gpio_update(chip, offset, SPRD_GPIO_INEN, 0);
102 sprd_gpio_update(chip, offset, SPRD_GPIO_DATA, value);
103 return 0;
104 }
105
sprd_gpio_get(struct gpio_chip * chip,unsigned int offset)106 static int sprd_gpio_get(struct gpio_chip *chip, unsigned int offset)
107 {
108 return sprd_gpio_read(chip, offset, SPRD_GPIO_DATA);
109 }
110
sprd_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)111 static void sprd_gpio_set(struct gpio_chip *chip, unsigned int offset,
112 int value)
113 {
114 sprd_gpio_update(chip, offset, SPRD_GPIO_DATA, value);
115 }
116
sprd_gpio_irq_mask(struct irq_data * data)117 static void sprd_gpio_irq_mask(struct irq_data *data)
118 {
119 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
120 u32 offset = irqd_to_hwirq(data);
121
122 sprd_gpio_update(chip, offset, SPRD_GPIO_IE, 0);
123 }
124
sprd_gpio_irq_ack(struct irq_data * data)125 static void sprd_gpio_irq_ack(struct irq_data *data)
126 {
127 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
128 u32 offset = irqd_to_hwirq(data);
129
130 sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
131 }
132
sprd_gpio_irq_unmask(struct irq_data * data)133 static void sprd_gpio_irq_unmask(struct irq_data *data)
134 {
135 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
136 u32 offset = irqd_to_hwirq(data);
137
138 sprd_gpio_update(chip, offset, SPRD_GPIO_IE, 1);
139 }
140
sprd_gpio_irq_set_type(struct irq_data * data,unsigned int flow_type)141 static int sprd_gpio_irq_set_type(struct irq_data *data,
142 unsigned int flow_type)
143 {
144 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
145 u32 offset = irqd_to_hwirq(data);
146
147 switch (flow_type) {
148 case IRQ_TYPE_EDGE_RISING:
149 sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0);
150 sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
151 sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 1);
152 sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
153 irq_set_handler_locked(data, handle_edge_irq);
154 break;
155 case IRQ_TYPE_EDGE_FALLING:
156 sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0);
157 sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
158 sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 0);
159 sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
160 irq_set_handler_locked(data, handle_edge_irq);
161 break;
162 case IRQ_TYPE_EDGE_BOTH:
163 sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0);
164 sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 1);
165 sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
166 irq_set_handler_locked(data, handle_edge_irq);
167 break;
168 case IRQ_TYPE_LEVEL_HIGH:
169 sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 1);
170 sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
171 sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 1);
172 irq_set_handler_locked(data, handle_level_irq);
173 break;
174 case IRQ_TYPE_LEVEL_LOW:
175 sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 1);
176 sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
177 sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 0);
178 irq_set_handler_locked(data, handle_level_irq);
179 break;
180 default:
181 return -EINVAL;
182 }
183
184 return 0;
185 }
186
sprd_gpio_irq_handler(struct irq_desc * desc)187 static void sprd_gpio_irq_handler(struct irq_desc *desc)
188 {
189 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
190 struct irq_chip *ic = irq_desc_get_chip(desc);
191 struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip);
192 u32 bank, n, girq;
193
194 chained_irq_enter(ic, desc);
195
196 for (bank = 0; bank * SPRD_GPIO_BANK_NR < chip->ngpio; bank++) {
197 void __iomem *base = sprd_gpio_bank_base(sprd_gpio, bank);
198 unsigned long reg = readl_relaxed(base + SPRD_GPIO_MIS) &
199 SPRD_GPIO_BANK_MASK;
200
201 for_each_set_bit(n, ®, SPRD_GPIO_BANK_NR) {
202 girq = irq_find_mapping(chip->irq.domain,
203 bank * SPRD_GPIO_BANK_NR + n);
204
205 generic_handle_irq(girq);
206 }
207
208 }
209 chained_irq_exit(ic, desc);
210 }
211
212 static struct irq_chip sprd_gpio_irqchip = {
213 .name = "sprd-gpio",
214 .irq_ack = sprd_gpio_irq_ack,
215 .irq_mask = sprd_gpio_irq_mask,
216 .irq_unmask = sprd_gpio_irq_unmask,
217 .irq_set_type = sprd_gpio_irq_set_type,
218 .flags = IRQCHIP_SKIP_SET_WAKE,
219 };
220
sprd_gpio_probe(struct platform_device * pdev)221 static int sprd_gpio_probe(struct platform_device *pdev)
222 {
223 struct gpio_irq_chip *irq;
224 struct sprd_gpio *sprd_gpio;
225 struct resource *res;
226 int ret;
227
228 sprd_gpio = devm_kzalloc(&pdev->dev, sizeof(*sprd_gpio), GFP_KERNEL);
229 if (!sprd_gpio)
230 return -ENOMEM;
231
232 sprd_gpio->irq = platform_get_irq(pdev, 0);
233 if (sprd_gpio->irq < 0) {
234 dev_err(&pdev->dev, "Failed to get GPIO interrupt.\n");
235 return sprd_gpio->irq;
236 }
237
238 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
239 sprd_gpio->base = devm_ioremap_resource(&pdev->dev, res);
240 if (IS_ERR(sprd_gpio->base))
241 return PTR_ERR(sprd_gpio->base);
242
243 spin_lock_init(&sprd_gpio->lock);
244
245 sprd_gpio->chip.label = dev_name(&pdev->dev);
246 sprd_gpio->chip.ngpio = SPRD_GPIO_NR;
247 sprd_gpio->chip.base = -1;
248 sprd_gpio->chip.parent = &pdev->dev;
249 sprd_gpio->chip.of_node = pdev->dev.of_node;
250 sprd_gpio->chip.request = sprd_gpio_request;
251 sprd_gpio->chip.free = sprd_gpio_free;
252 sprd_gpio->chip.get = sprd_gpio_get;
253 sprd_gpio->chip.set = sprd_gpio_set;
254 sprd_gpio->chip.direction_input = sprd_gpio_direction_input;
255 sprd_gpio->chip.direction_output = sprd_gpio_direction_output;
256
257 irq = &sprd_gpio->chip.irq;
258 irq->chip = &sprd_gpio_irqchip;
259 irq->handler = handle_bad_irq;
260 irq->default_type = IRQ_TYPE_NONE;
261 irq->parent_handler = sprd_gpio_irq_handler;
262 irq->parent_handler_data = sprd_gpio;
263 irq->num_parents = 1;
264 irq->parents = &sprd_gpio->irq;
265
266 ret = devm_gpiochip_add_data(&pdev->dev, &sprd_gpio->chip, sprd_gpio);
267 if (ret < 0) {
268 dev_err(&pdev->dev, "Could not register gpiochip %d\n", ret);
269 return ret;
270 }
271
272 platform_set_drvdata(pdev, sprd_gpio);
273 return 0;
274 }
275
276 static const struct of_device_id sprd_gpio_of_match[] = {
277 { .compatible = "sprd,sc9860-gpio", },
278 { /* end of list */ }
279 };
280 MODULE_DEVICE_TABLE(of, sprd_gpio_of_match);
281
282 static struct platform_driver sprd_gpio_driver = {
283 .probe = sprd_gpio_probe,
284 .driver = {
285 .name = "sprd-gpio",
286 .of_match_table = sprd_gpio_of_match,
287 },
288 };
289
290 module_platform_driver_probe(sprd_gpio_driver, sprd_gpio_probe);
291
292 MODULE_DESCRIPTION("Spreadtrum GPIO driver");
293 MODULE_LICENSE("GPL v2");
294