1 /*
2 * Copyright (c) 2016-2017 NVIDIA Corporation
3 *
4 * Author: Thierry Reding <treding@nvidia.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 */
10
11 #include <linux/gpio/driver.h>
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
17
18 #include <dt-bindings/gpio/tegra186-gpio.h>
19 #include <dt-bindings/gpio/tegra194-gpio.h>
20
21 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00
22 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
23 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
24 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
25 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
26 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
27 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
28 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
29 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
30 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
31
32 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
33 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
34
35 #define TEGRA186_GPIO_INPUT 0x08
36 #define TEGRA186_GPIO_INPUT_HIGH BIT(0)
37
38 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
39 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
40
41 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10
42 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
43
44 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
45
46 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
47
48 struct tegra_gpio_port {
49 const char *name;
50 unsigned int offset;
51 unsigned int pins;
52 unsigned int irq;
53 };
54
55 struct tegra_gpio_soc {
56 const struct tegra_gpio_port *ports;
57 unsigned int num_ports;
58 const char *name;
59 };
60
61 struct tegra_gpio {
62 struct gpio_chip gpio;
63 struct irq_chip intc;
64 unsigned int num_irq;
65 unsigned int *irq;
66
67 const struct tegra_gpio_soc *soc;
68
69 void __iomem *base;
70 };
71
72 static const struct tegra_gpio_port *
tegra186_gpio_get_port(struct tegra_gpio * gpio,unsigned int * pin)73 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
74 {
75 unsigned int start = 0, i;
76
77 for (i = 0; i < gpio->soc->num_ports; i++) {
78 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
79
80 if (*pin >= start && *pin < start + port->pins) {
81 *pin -= start;
82 return port;
83 }
84
85 start += port->pins;
86 }
87
88 return NULL;
89 }
90
tegra186_gpio_get_base(struct tegra_gpio * gpio,unsigned int pin)91 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
92 unsigned int pin)
93 {
94 const struct tegra_gpio_port *port;
95
96 port = tegra186_gpio_get_port(gpio, &pin);
97 if (!port)
98 return NULL;
99
100 return gpio->base + port->offset + pin * 0x20;
101 }
102
tegra186_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)103 static int tegra186_gpio_get_direction(struct gpio_chip *chip,
104 unsigned int offset)
105 {
106 struct tegra_gpio *gpio = gpiochip_get_data(chip);
107 void __iomem *base;
108 u32 value;
109
110 base = tegra186_gpio_get_base(gpio, offset);
111 if (WARN_ON(base == NULL))
112 return -ENODEV;
113
114 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
115 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
116 return 0;
117
118 return 1;
119 }
120
tegra186_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)121 static int tegra186_gpio_direction_input(struct gpio_chip *chip,
122 unsigned int offset)
123 {
124 struct tegra_gpio *gpio = gpiochip_get_data(chip);
125 void __iomem *base;
126 u32 value;
127
128 base = tegra186_gpio_get_base(gpio, offset);
129 if (WARN_ON(base == NULL))
130 return -ENODEV;
131
132 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
133 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
134 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
135
136 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
137 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
138 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
139 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
140
141 return 0;
142 }
143
tegra186_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int level)144 static int tegra186_gpio_direction_output(struct gpio_chip *chip,
145 unsigned int offset, int level)
146 {
147 struct tegra_gpio *gpio = gpiochip_get_data(chip);
148 void __iomem *base;
149 u32 value;
150
151 /* configure output level first */
152 chip->set(chip, offset, level);
153
154 base = tegra186_gpio_get_base(gpio, offset);
155 if (WARN_ON(base == NULL))
156 return -EINVAL;
157
158 /* set the direction */
159 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
160 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
161 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
162
163 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
164 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
165 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
166 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
167
168 return 0;
169 }
170
tegra186_gpio_get(struct gpio_chip * chip,unsigned int offset)171 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
172 {
173 struct tegra_gpio *gpio = gpiochip_get_data(chip);
174 void __iomem *base;
175 u32 value;
176
177 base = tegra186_gpio_get_base(gpio, offset);
178 if (WARN_ON(base == NULL))
179 return -ENODEV;
180
181 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
182 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
183 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
184 else
185 value = readl(base + TEGRA186_GPIO_INPUT);
186
187 return value & BIT(0);
188 }
189
tegra186_gpio_set(struct gpio_chip * chip,unsigned int offset,int level)190 static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
191 int level)
192 {
193 struct tegra_gpio *gpio = gpiochip_get_data(chip);
194 void __iomem *base;
195 u32 value;
196
197 base = tegra186_gpio_get_base(gpio, offset);
198 if (WARN_ON(base == NULL))
199 return;
200
201 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
202 if (level == 0)
203 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
204 else
205 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
206
207 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
208 }
209
tegra186_gpio_of_xlate(struct gpio_chip * chip,const struct of_phandle_args * spec,u32 * flags)210 static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
211 const struct of_phandle_args *spec,
212 u32 *flags)
213 {
214 struct tegra_gpio *gpio = gpiochip_get_data(chip);
215 unsigned int port, pin, i, offset = 0;
216
217 if (WARN_ON(chip->of_gpio_n_cells < 2))
218 return -EINVAL;
219
220 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
221 return -EINVAL;
222
223 port = spec->args[0] / 8;
224 pin = spec->args[0] % 8;
225
226 if (port >= gpio->soc->num_ports) {
227 dev_err(chip->parent, "invalid port number: %u\n", port);
228 return -EINVAL;
229 }
230
231 for (i = 0; i < port; i++)
232 offset += gpio->soc->ports[i].pins;
233
234 if (flags)
235 *flags = spec->args[1];
236
237 return offset + pin;
238 }
239
240 #define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio)
241
tegra186_irq_ack(struct irq_data * data)242 static void tegra186_irq_ack(struct irq_data *data)
243 {
244 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
245 struct tegra_gpio *gpio = to_tegra_gpio(gc);
246 void __iomem *base;
247
248 base = tegra186_gpio_get_base(gpio, data->hwirq);
249 if (WARN_ON(base == NULL))
250 return;
251
252 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
253 }
254
tegra186_irq_mask(struct irq_data * data)255 static void tegra186_irq_mask(struct irq_data *data)
256 {
257 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
258 struct tegra_gpio *gpio = to_tegra_gpio(gc);
259 void __iomem *base;
260 u32 value;
261
262 base = tegra186_gpio_get_base(gpio, data->hwirq);
263 if (WARN_ON(base == NULL))
264 return;
265
266 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
267 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
268 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
269 }
270
tegra186_irq_unmask(struct irq_data * data)271 static void tegra186_irq_unmask(struct irq_data *data)
272 {
273 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
274 struct tegra_gpio *gpio = to_tegra_gpio(gc);
275 void __iomem *base;
276 u32 value;
277
278 base = tegra186_gpio_get_base(gpio, data->hwirq);
279 if (WARN_ON(base == NULL))
280 return;
281
282 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
283 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
284 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
285 }
286
tegra186_irq_set_type(struct irq_data * data,unsigned int flow)287 static int tegra186_irq_set_type(struct irq_data *data, unsigned int flow)
288 {
289 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
290 struct tegra_gpio *gpio = to_tegra_gpio(gc);
291 void __iomem *base;
292 u32 value;
293
294 base = tegra186_gpio_get_base(gpio, data->hwirq);
295 if (WARN_ON(base == NULL))
296 return -ENODEV;
297
298 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
299 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
300 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
301
302 switch (flow & IRQ_TYPE_SENSE_MASK) {
303 case IRQ_TYPE_NONE:
304 break;
305
306 case IRQ_TYPE_EDGE_RISING:
307 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
308 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
309 break;
310
311 case IRQ_TYPE_EDGE_FALLING:
312 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
313 break;
314
315 case IRQ_TYPE_EDGE_BOTH:
316 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
317 break;
318
319 case IRQ_TYPE_LEVEL_HIGH:
320 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
321 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
322 break;
323
324 case IRQ_TYPE_LEVEL_LOW:
325 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
326 break;
327
328 default:
329 return -EINVAL;
330 }
331
332 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
333
334 if ((flow & IRQ_TYPE_EDGE_BOTH) == 0)
335 irq_set_handler_locked(data, handle_level_irq);
336 else
337 irq_set_handler_locked(data, handle_edge_irq);
338
339 return 0;
340 }
341
tegra186_gpio_irq(struct irq_desc * desc)342 static void tegra186_gpio_irq(struct irq_desc *desc)
343 {
344 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
345 struct irq_domain *domain = gpio->gpio.irq.domain;
346 struct irq_chip *chip = irq_desc_get_chip(desc);
347 unsigned int parent = irq_desc_get_irq(desc);
348 unsigned int i, offset = 0;
349
350 chained_irq_enter(chip, desc);
351
352 for (i = 0; i < gpio->soc->num_ports; i++) {
353 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
354 void __iomem *base = gpio->base + port->offset;
355 unsigned int pin, irq;
356 unsigned long value;
357
358 /* skip ports that are not associated with this controller */
359 if (parent != gpio->irq[port->irq])
360 goto skip;
361
362 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
363
364 for_each_set_bit(pin, &value, port->pins) {
365 irq = irq_find_mapping(domain, offset + pin);
366 if (WARN_ON(irq == 0))
367 continue;
368
369 generic_handle_irq(irq);
370 }
371
372 skip:
373 offset += port->pins;
374 }
375
376 chained_irq_exit(chip, desc);
377 }
378
tegra186_gpio_irq_domain_xlate(struct irq_domain * domain,struct device_node * np,const u32 * spec,unsigned int size,unsigned long * hwirq,unsigned int * type)379 static int tegra186_gpio_irq_domain_xlate(struct irq_domain *domain,
380 struct device_node *np,
381 const u32 *spec, unsigned int size,
382 unsigned long *hwirq,
383 unsigned int *type)
384 {
385 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
386 unsigned int port, pin, i, offset = 0;
387
388 if (size < 2)
389 return -EINVAL;
390
391 port = spec[0] / 8;
392 pin = spec[0] % 8;
393
394 if (port >= gpio->soc->num_ports) {
395 dev_err(gpio->gpio.parent, "invalid port number: %u\n", port);
396 return -EINVAL;
397 }
398
399 for (i = 0; i < port; i++)
400 offset += gpio->soc->ports[i].pins;
401
402 *type = spec[1] & IRQ_TYPE_SENSE_MASK;
403 *hwirq = offset + pin;
404
405 return 0;
406 }
407
408 static const struct irq_domain_ops tegra186_gpio_irq_domain_ops = {
409 .map = gpiochip_irq_map,
410 .unmap = gpiochip_irq_unmap,
411 .xlate = tegra186_gpio_irq_domain_xlate,
412 };
413
tegra186_gpio_probe(struct platform_device * pdev)414 static int tegra186_gpio_probe(struct platform_device *pdev)
415 {
416 unsigned int i, j, offset;
417 struct gpio_irq_chip *irq;
418 struct tegra_gpio *gpio;
419 struct resource *res;
420 char **names;
421 int err;
422
423 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
424 if (!gpio)
425 return -ENOMEM;
426
427 gpio->soc = of_device_get_match_data(&pdev->dev);
428
429 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gpio");
430 gpio->base = devm_ioremap_resource(&pdev->dev, res);
431 if (IS_ERR(gpio->base))
432 return PTR_ERR(gpio->base);
433
434 err = platform_irq_count(pdev);
435 if (err < 0)
436 return err;
437
438 gpio->num_irq = err;
439
440 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
441 GFP_KERNEL);
442 if (!gpio->irq)
443 return -ENOMEM;
444
445 for (i = 0; i < gpio->num_irq; i++) {
446 err = platform_get_irq(pdev, i);
447 if (err < 0)
448 return err;
449
450 gpio->irq[i] = err;
451 }
452
453 gpio->gpio.label = gpio->soc->name;
454 gpio->gpio.parent = &pdev->dev;
455
456 gpio->gpio.get_direction = tegra186_gpio_get_direction;
457 gpio->gpio.direction_input = tegra186_gpio_direction_input;
458 gpio->gpio.direction_output = tegra186_gpio_direction_output;
459 gpio->gpio.get = tegra186_gpio_get,
460 gpio->gpio.set = tegra186_gpio_set;
461
462 gpio->gpio.base = -1;
463
464 for (i = 0; i < gpio->soc->num_ports; i++)
465 gpio->gpio.ngpio += gpio->soc->ports[i].pins;
466
467 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
468 sizeof(*names), GFP_KERNEL);
469 if (!names)
470 return -ENOMEM;
471
472 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
473 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
474 char *name;
475
476 for (j = 0; j < port->pins; j++) {
477 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
478 "P%s.%02x", port->name, j);
479 if (!name)
480 return -ENOMEM;
481
482 names[offset + j] = name;
483 }
484
485 offset += port->pins;
486 }
487
488 gpio->gpio.names = (const char * const *)names;
489
490 gpio->gpio.of_node = pdev->dev.of_node;
491 gpio->gpio.of_gpio_n_cells = 2;
492 gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
493
494 gpio->intc.name = pdev->dev.of_node->name;
495 gpio->intc.irq_ack = tegra186_irq_ack;
496 gpio->intc.irq_mask = tegra186_irq_mask;
497 gpio->intc.irq_unmask = tegra186_irq_unmask;
498 gpio->intc.irq_set_type = tegra186_irq_set_type;
499
500 irq = &gpio->gpio.irq;
501 irq->chip = &gpio->intc;
502 irq->domain_ops = &tegra186_gpio_irq_domain_ops;
503 irq->handler = handle_simple_irq;
504 irq->default_type = IRQ_TYPE_NONE;
505 irq->parent_handler = tegra186_gpio_irq;
506 irq->parent_handler_data = gpio;
507 irq->num_parents = gpio->num_irq;
508 irq->parents = gpio->irq;
509
510 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
511 sizeof(*irq->map), GFP_KERNEL);
512 if (!irq->map)
513 return -ENOMEM;
514
515 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
516 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
517
518 for (j = 0; j < port->pins; j++)
519 irq->map[offset + j] = irq->parents[port->irq];
520
521 offset += port->pins;
522 }
523
524 platform_set_drvdata(pdev, gpio);
525
526 err = devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
527 if (err < 0)
528 return err;
529
530 return 0;
531 }
532
tegra186_gpio_remove(struct platform_device * pdev)533 static int tegra186_gpio_remove(struct platform_device *pdev)
534 {
535 return 0;
536 }
537
538 #define TEGRA_MAIN_GPIO_PORT(port, base, count, controller) \
539 [TEGRA_MAIN_GPIO_PORT_##port] = { \
540 .name = #port, \
541 .offset = base, \
542 .pins = count, \
543 .irq = controller, \
544 }
545
546 static const struct tegra_gpio_port tegra186_main_ports[] = {
547 TEGRA_MAIN_GPIO_PORT( A, 0x2000, 7, 2),
548 TEGRA_MAIN_GPIO_PORT( B, 0x3000, 7, 3),
549 TEGRA_MAIN_GPIO_PORT( C, 0x3200, 7, 3),
550 TEGRA_MAIN_GPIO_PORT( D, 0x3400, 6, 3),
551 TEGRA_MAIN_GPIO_PORT( E, 0x2200, 8, 2),
552 TEGRA_MAIN_GPIO_PORT( F, 0x2400, 6, 2),
553 TEGRA_MAIN_GPIO_PORT( G, 0x4200, 6, 4),
554 TEGRA_MAIN_GPIO_PORT( H, 0x1000, 7, 1),
555 TEGRA_MAIN_GPIO_PORT( I, 0x0800, 8, 0),
556 TEGRA_MAIN_GPIO_PORT( J, 0x5000, 8, 5),
557 TEGRA_MAIN_GPIO_PORT( K, 0x5200, 1, 5),
558 TEGRA_MAIN_GPIO_PORT( L, 0x1200, 8, 1),
559 TEGRA_MAIN_GPIO_PORT( M, 0x5600, 6, 5),
560 TEGRA_MAIN_GPIO_PORT( N, 0x0000, 7, 0),
561 TEGRA_MAIN_GPIO_PORT( O, 0x0200, 4, 0),
562 TEGRA_MAIN_GPIO_PORT( P, 0x4000, 7, 4),
563 TEGRA_MAIN_GPIO_PORT( Q, 0x0400, 6, 0),
564 TEGRA_MAIN_GPIO_PORT( R, 0x0a00, 6, 0),
565 TEGRA_MAIN_GPIO_PORT( T, 0x0600, 4, 0),
566 TEGRA_MAIN_GPIO_PORT( X, 0x1400, 8, 1),
567 TEGRA_MAIN_GPIO_PORT( Y, 0x1600, 7, 1),
568 TEGRA_MAIN_GPIO_PORT(BB, 0x2600, 2, 2),
569 TEGRA_MAIN_GPIO_PORT(CC, 0x5400, 4, 5),
570 };
571
572 static const struct tegra_gpio_soc tegra186_main_soc = {
573 .num_ports = ARRAY_SIZE(tegra186_main_ports),
574 .ports = tegra186_main_ports,
575 .name = "tegra186-gpio",
576 };
577
578 #define TEGRA_AON_GPIO_PORT(port, base, count, controller) \
579 [TEGRA_AON_GPIO_PORT_##port] = { \
580 .name = #port, \
581 .offset = base, \
582 .pins = count, \
583 .irq = controller, \
584 }
585
586 static const struct tegra_gpio_port tegra186_aon_ports[] = {
587 TEGRA_AON_GPIO_PORT( S, 0x0200, 5, 0),
588 TEGRA_AON_GPIO_PORT( U, 0x0400, 6, 0),
589 TEGRA_AON_GPIO_PORT( V, 0x0800, 8, 0),
590 TEGRA_AON_GPIO_PORT( W, 0x0a00, 8, 0),
591 TEGRA_AON_GPIO_PORT( Z, 0x0e00, 4, 0),
592 TEGRA_AON_GPIO_PORT(AA, 0x0c00, 8, 0),
593 TEGRA_AON_GPIO_PORT(EE, 0x0600, 3, 0),
594 TEGRA_AON_GPIO_PORT(FF, 0x0000, 5, 0),
595 };
596
597 static const struct tegra_gpio_soc tegra186_aon_soc = {
598 .num_ports = ARRAY_SIZE(tegra186_aon_ports),
599 .ports = tegra186_aon_ports,
600 .name = "tegra186-gpio-aon",
601 };
602
603 #define TEGRA194_MAIN_GPIO_PORT(port, base, count, controller) \
604 [TEGRA194_MAIN_GPIO_PORT_##port] = { \
605 .name = #port, \
606 .offset = base, \
607 .pins = count, \
608 .irq = controller, \
609 }
610
611 static const struct tegra_gpio_port tegra194_main_ports[] = {
612 TEGRA194_MAIN_GPIO_PORT( A, 0x1400, 8, 1),
613 TEGRA194_MAIN_GPIO_PORT( B, 0x4e00, 2, 4),
614 TEGRA194_MAIN_GPIO_PORT( C, 0x4600, 8, 4),
615 TEGRA194_MAIN_GPIO_PORT( D, 0x4800, 4, 4),
616 TEGRA194_MAIN_GPIO_PORT( E, 0x4a00, 8, 4),
617 TEGRA194_MAIN_GPIO_PORT( F, 0x4c00, 6, 4),
618 TEGRA194_MAIN_GPIO_PORT( G, 0x4000, 8, 4),
619 TEGRA194_MAIN_GPIO_PORT( H, 0x4200, 8, 4),
620 TEGRA194_MAIN_GPIO_PORT( I, 0x4400, 5, 4),
621 TEGRA194_MAIN_GPIO_PORT( J, 0x5200, 6, 5),
622 TEGRA194_MAIN_GPIO_PORT( K, 0x3000, 8, 3),
623 TEGRA194_MAIN_GPIO_PORT( L, 0x3200, 4, 3),
624 TEGRA194_MAIN_GPIO_PORT( M, 0x2600, 8, 2),
625 TEGRA194_MAIN_GPIO_PORT( N, 0x2800, 3, 2),
626 TEGRA194_MAIN_GPIO_PORT( O, 0x5000, 6, 5),
627 TEGRA194_MAIN_GPIO_PORT( P, 0x2a00, 8, 2),
628 TEGRA194_MAIN_GPIO_PORT( Q, 0x2c00, 8, 2),
629 TEGRA194_MAIN_GPIO_PORT( R, 0x2e00, 6, 2),
630 TEGRA194_MAIN_GPIO_PORT( S, 0x3600, 8, 3),
631 TEGRA194_MAIN_GPIO_PORT( T, 0x3800, 8, 3),
632 TEGRA194_MAIN_GPIO_PORT( U, 0x3a00, 1, 3),
633 TEGRA194_MAIN_GPIO_PORT( V, 0x1000, 8, 1),
634 TEGRA194_MAIN_GPIO_PORT( W, 0x1200, 2, 1),
635 TEGRA194_MAIN_GPIO_PORT( X, 0x2000, 8, 2),
636 TEGRA194_MAIN_GPIO_PORT( Y, 0x2200, 8, 2),
637 TEGRA194_MAIN_GPIO_PORT( Z, 0x2400, 8, 2),
638 TEGRA194_MAIN_GPIO_PORT(FF, 0x3400, 2, 3),
639 TEGRA194_MAIN_GPIO_PORT(GG, 0x0000, 2, 0)
640 };
641
642 static const struct tegra_gpio_soc tegra194_main_soc = {
643 .num_ports = ARRAY_SIZE(tegra194_main_ports),
644 .ports = tegra194_main_ports,
645 .name = "tegra194-gpio",
646 };
647
648 #define TEGRA194_AON_GPIO_PORT(port, base, count, controller) \
649 [TEGRA194_AON_GPIO_PORT_##port] = { \
650 .name = #port, \
651 .offset = base, \
652 .pins = count, \
653 .irq = controller, \
654 }
655
656 static const struct tegra_gpio_port tegra194_aon_ports[] = {
657 TEGRA194_AON_GPIO_PORT(AA, 0x0600, 8, 0),
658 TEGRA194_AON_GPIO_PORT(BB, 0x0800, 4, 0),
659 TEGRA194_AON_GPIO_PORT(CC, 0x0200, 8, 0),
660 TEGRA194_AON_GPIO_PORT(DD, 0x0400, 3, 0),
661 TEGRA194_AON_GPIO_PORT(EE, 0x0000, 7, 0)
662 };
663
664 static const struct tegra_gpio_soc tegra194_aon_soc = {
665 .num_ports = ARRAY_SIZE(tegra194_aon_ports),
666 .ports = tegra194_aon_ports,
667 .name = "tegra194-gpio-aon",
668 };
669
670 static const struct of_device_id tegra186_gpio_of_match[] = {
671 {
672 .compatible = "nvidia,tegra186-gpio",
673 .data = &tegra186_main_soc
674 }, {
675 .compatible = "nvidia,tegra186-gpio-aon",
676 .data = &tegra186_aon_soc
677 }, {
678 .compatible = "nvidia,tegra194-gpio",
679 .data = &tegra194_main_soc
680 }, {
681 .compatible = "nvidia,tegra194-gpio-aon",
682 .data = &tegra194_aon_soc
683 }, {
684 /* sentinel */
685 }
686 };
687
688 static struct platform_driver tegra186_gpio_driver = {
689 .driver = {
690 .name = "tegra186-gpio",
691 .of_match_table = tegra186_gpio_of_match,
692 },
693 .probe = tegra186_gpio_probe,
694 .remove = tegra186_gpio_remove,
695 };
696 module_platform_driver(tegra186_gpio_driver);
697
698 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
699 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
700 MODULE_LICENSE("GPL v2");
701