1 /*
2 * Driver for NEC VR4100 series General-purpose I/O Unit.
3 *
4 * Copyright (C) 2002 MontaVista Software Inc.
5 * Author: Yoichi Yuasa <source@mvista.com>
6 * Copyright (C) 2003-2009 Yoichi Yuasa <yuasa@linux-mips.org>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22 #include <linux/errno.h>
23 #include <linux/fs.h>
24 #include <linux/gpio.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/irq.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/platform_device.h>
32 #include <linux/spinlock.h>
33 #include <linux/types.h>
34
35 #include <asm/vr41xx/giu.h>
36 #include <asm/vr41xx/irq.h>
37 #include <asm/vr41xx/vr41xx.h>
38
39 MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
40 MODULE_DESCRIPTION("NEC VR4100 series General-purpose I/O Unit driver");
41 MODULE_LICENSE("GPL");
42
43 #define GIUIOSELL 0x00
44 #define GIUIOSELH 0x02
45 #define GIUPIODL 0x04
46 #define GIUPIODH 0x06
47 #define GIUINTSTATL 0x08
48 #define GIUINTSTATH 0x0a
49 #define GIUINTENL 0x0c
50 #define GIUINTENH 0x0e
51 #define GIUINTTYPL 0x10
52 #define GIUINTTYPH 0x12
53 #define GIUINTALSELL 0x14
54 #define GIUINTALSELH 0x16
55 #define GIUINTHTSELL 0x18
56 #define GIUINTHTSELH 0x1a
57 #define GIUPODATL 0x1c
58 #define GIUPODATEN 0x1c
59 #define GIUPODATH 0x1e
60 #define PIOEN0 0x0100
61 #define PIOEN1 0x0200
62 #define GIUPODAT 0x1e
63 #define GIUFEDGEINHL 0x20
64 #define GIUFEDGEINHH 0x22
65 #define GIUREDGEINHL 0x24
66 #define GIUREDGEINHH 0x26
67
68 #define GIUUSEUPDN 0x1e0
69 #define GIUTERMUPDN 0x1e2
70
71 #define GPIO_HAS_PULLUPDOWN_IO 0x0001
72 #define GPIO_HAS_OUTPUT_ENABLE 0x0002
73 #define GPIO_HAS_INTERRUPT_EDGE_SELECT 0x0100
74
75 enum {
76 GPIO_INPUT,
77 GPIO_OUTPUT,
78 };
79
80 static DEFINE_SPINLOCK(giu_lock);
81 static unsigned long giu_flags;
82
83 static void __iomem *giu_base;
84 static struct gpio_chip vr41xx_gpio_chip;
85
86 #define giu_read(offset) readw(giu_base + (offset))
87 #define giu_write(offset, value) writew((value), giu_base + (offset))
88
89 #define GPIO_PIN_OF_IRQ(irq) ((irq) - GIU_IRQ_BASE)
90 #define GIUINT_HIGH_OFFSET 16
91 #define GIUINT_HIGH_MAX 32
92
giu_set(u16 offset,u16 set)93 static inline u16 giu_set(u16 offset, u16 set)
94 {
95 u16 data;
96
97 data = giu_read(offset);
98 data |= set;
99 giu_write(offset, data);
100
101 return data;
102 }
103
giu_clear(u16 offset,u16 clear)104 static inline u16 giu_clear(u16 offset, u16 clear)
105 {
106 u16 data;
107
108 data = giu_read(offset);
109 data &= ~clear;
110 giu_write(offset, data);
111
112 return data;
113 }
114
ack_giuint_low(struct irq_data * d)115 static void ack_giuint_low(struct irq_data *d)
116 {
117 giu_write(GIUINTSTATL, 1 << GPIO_PIN_OF_IRQ(d->irq));
118 }
119
mask_giuint_low(struct irq_data * d)120 static void mask_giuint_low(struct irq_data *d)
121 {
122 giu_clear(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq));
123 }
124
mask_ack_giuint_low(struct irq_data * d)125 static void mask_ack_giuint_low(struct irq_data *d)
126 {
127 unsigned int pin;
128
129 pin = GPIO_PIN_OF_IRQ(d->irq);
130 giu_clear(GIUINTENL, 1 << pin);
131 giu_write(GIUINTSTATL, 1 << pin);
132 }
133
unmask_giuint_low(struct irq_data * d)134 static void unmask_giuint_low(struct irq_data *d)
135 {
136 giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq));
137 }
138
startup_giuint(struct irq_data * data)139 static unsigned int startup_giuint(struct irq_data *data)
140 {
141 int ret;
142
143 ret = gpiochip_lock_as_irq(&vr41xx_gpio_chip, irqd_to_hwirq(data));
144 if (ret) {
145 dev_err(vr41xx_gpio_chip.parent,
146 "unable to lock HW IRQ %lu for IRQ\n",
147 data->hwirq);
148 return ret;
149 }
150
151 /* Satisfy the .enable semantics by unmasking the line */
152 unmask_giuint_low(data);
153 return 0;
154 }
155
shutdown_giuint(struct irq_data * data)156 static void shutdown_giuint(struct irq_data *data)
157 {
158 mask_giuint_low(data);
159 gpiochip_unlock_as_irq(&vr41xx_gpio_chip, data->hwirq);
160 }
161
162 static struct irq_chip giuint_low_irq_chip = {
163 .name = "GIUINTL",
164 .irq_ack = ack_giuint_low,
165 .irq_mask = mask_giuint_low,
166 .irq_mask_ack = mask_ack_giuint_low,
167 .irq_unmask = unmask_giuint_low,
168 .irq_startup = startup_giuint,
169 .irq_shutdown = shutdown_giuint,
170 };
171
ack_giuint_high(struct irq_data * d)172 static void ack_giuint_high(struct irq_data *d)
173 {
174 giu_write(GIUINTSTATH,
175 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET));
176 }
177
mask_giuint_high(struct irq_data * d)178 static void mask_giuint_high(struct irq_data *d)
179 {
180 giu_clear(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET));
181 }
182
mask_ack_giuint_high(struct irq_data * d)183 static void mask_ack_giuint_high(struct irq_data *d)
184 {
185 unsigned int pin;
186
187 pin = GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET;
188 giu_clear(GIUINTENH, 1 << pin);
189 giu_write(GIUINTSTATH, 1 << pin);
190 }
191
unmask_giuint_high(struct irq_data * d)192 static void unmask_giuint_high(struct irq_data *d)
193 {
194 giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET));
195 }
196
197 static struct irq_chip giuint_high_irq_chip = {
198 .name = "GIUINTH",
199 .irq_ack = ack_giuint_high,
200 .irq_mask = mask_giuint_high,
201 .irq_mask_ack = mask_ack_giuint_high,
202 .irq_unmask = unmask_giuint_high,
203 };
204
giu_get_irq(unsigned int irq)205 static int giu_get_irq(unsigned int irq)
206 {
207 u16 pendl, pendh, maskl, maskh;
208 int i;
209
210 pendl = giu_read(GIUINTSTATL);
211 pendh = giu_read(GIUINTSTATH);
212 maskl = giu_read(GIUINTENL);
213 maskh = giu_read(GIUINTENH);
214
215 maskl &= pendl;
216 maskh &= pendh;
217
218 if (maskl) {
219 for (i = 0; i < 16; i++) {
220 if (maskl & (1 << i))
221 return GIU_IRQ(i);
222 }
223 } else if (maskh) {
224 for (i = 0; i < 16; i++) {
225 if (maskh & (1 << i))
226 return GIU_IRQ(i + GIUINT_HIGH_OFFSET);
227 }
228 }
229
230 printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n",
231 maskl, pendl, maskh, pendh);
232
233 return -EINVAL;
234 }
235
vr41xx_set_irq_trigger(unsigned int pin,irq_trigger_t trigger,irq_signal_t signal)236 void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger,
237 irq_signal_t signal)
238 {
239 u16 mask;
240
241 if (pin < GIUINT_HIGH_OFFSET) {
242 mask = 1 << pin;
243 if (trigger != IRQ_TRIGGER_LEVEL) {
244 giu_set(GIUINTTYPL, mask);
245 if (signal == IRQ_SIGNAL_HOLD)
246 giu_set(GIUINTHTSELL, mask);
247 else
248 giu_clear(GIUINTHTSELL, mask);
249 if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
250 switch (trigger) {
251 case IRQ_TRIGGER_EDGE_FALLING:
252 giu_set(GIUFEDGEINHL, mask);
253 giu_clear(GIUREDGEINHL, mask);
254 break;
255 case IRQ_TRIGGER_EDGE_RISING:
256 giu_clear(GIUFEDGEINHL, mask);
257 giu_set(GIUREDGEINHL, mask);
258 break;
259 default:
260 giu_set(GIUFEDGEINHL, mask);
261 giu_set(GIUREDGEINHL, mask);
262 break;
263 }
264 }
265 irq_set_chip_and_handler(GIU_IRQ(pin),
266 &giuint_low_irq_chip,
267 handle_edge_irq);
268 } else {
269 giu_clear(GIUINTTYPL, mask);
270 giu_clear(GIUINTHTSELL, mask);
271 irq_set_chip_and_handler(GIU_IRQ(pin),
272 &giuint_low_irq_chip,
273 handle_level_irq);
274 }
275 giu_write(GIUINTSTATL, mask);
276 } else if (pin < GIUINT_HIGH_MAX) {
277 mask = 1 << (pin - GIUINT_HIGH_OFFSET);
278 if (trigger != IRQ_TRIGGER_LEVEL) {
279 giu_set(GIUINTTYPH, mask);
280 if (signal == IRQ_SIGNAL_HOLD)
281 giu_set(GIUINTHTSELH, mask);
282 else
283 giu_clear(GIUINTHTSELH, mask);
284 if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
285 switch (trigger) {
286 case IRQ_TRIGGER_EDGE_FALLING:
287 giu_set(GIUFEDGEINHH, mask);
288 giu_clear(GIUREDGEINHH, mask);
289 break;
290 case IRQ_TRIGGER_EDGE_RISING:
291 giu_clear(GIUFEDGEINHH, mask);
292 giu_set(GIUREDGEINHH, mask);
293 break;
294 default:
295 giu_set(GIUFEDGEINHH, mask);
296 giu_set(GIUREDGEINHH, mask);
297 break;
298 }
299 }
300 irq_set_chip_and_handler(GIU_IRQ(pin),
301 &giuint_high_irq_chip,
302 handle_edge_irq);
303 } else {
304 giu_clear(GIUINTTYPH, mask);
305 giu_clear(GIUINTHTSELH, mask);
306 irq_set_chip_and_handler(GIU_IRQ(pin),
307 &giuint_high_irq_chip,
308 handle_level_irq);
309 }
310 giu_write(GIUINTSTATH, mask);
311 }
312 }
313 EXPORT_SYMBOL_GPL(vr41xx_set_irq_trigger);
314
vr41xx_set_irq_level(unsigned int pin,irq_level_t level)315 void vr41xx_set_irq_level(unsigned int pin, irq_level_t level)
316 {
317 u16 mask;
318
319 if (pin < GIUINT_HIGH_OFFSET) {
320 mask = 1 << pin;
321 if (level == IRQ_LEVEL_HIGH)
322 giu_set(GIUINTALSELL, mask);
323 else
324 giu_clear(GIUINTALSELL, mask);
325 giu_write(GIUINTSTATL, mask);
326 } else if (pin < GIUINT_HIGH_MAX) {
327 mask = 1 << (pin - GIUINT_HIGH_OFFSET);
328 if (level == IRQ_LEVEL_HIGH)
329 giu_set(GIUINTALSELH, mask);
330 else
331 giu_clear(GIUINTALSELH, mask);
332 giu_write(GIUINTSTATH, mask);
333 }
334 }
335 EXPORT_SYMBOL_GPL(vr41xx_set_irq_level);
336
giu_set_direction(struct gpio_chip * chip,unsigned pin,int dir)337 static int giu_set_direction(struct gpio_chip *chip, unsigned pin, int dir)
338 {
339 u16 offset, mask, reg;
340 unsigned long flags;
341
342 if (pin >= chip->ngpio)
343 return -EINVAL;
344
345 if (pin < 16) {
346 offset = GIUIOSELL;
347 mask = 1 << pin;
348 } else if (pin < 32) {
349 offset = GIUIOSELH;
350 mask = 1 << (pin - 16);
351 } else {
352 if (giu_flags & GPIO_HAS_OUTPUT_ENABLE) {
353 offset = GIUPODATEN;
354 mask = 1 << (pin - 32);
355 } else {
356 switch (pin) {
357 case 48:
358 offset = GIUPODATH;
359 mask = PIOEN0;
360 break;
361 case 49:
362 offset = GIUPODATH;
363 mask = PIOEN1;
364 break;
365 default:
366 return -EINVAL;
367 }
368 }
369 }
370
371 spin_lock_irqsave(&giu_lock, flags);
372
373 reg = giu_read(offset);
374 if (dir == GPIO_OUTPUT)
375 reg |= mask;
376 else
377 reg &= ~mask;
378 giu_write(offset, reg);
379
380 spin_unlock_irqrestore(&giu_lock, flags);
381
382 return 0;
383 }
384
vr41xx_gpio_pullupdown(unsigned int pin,gpio_pull_t pull)385 int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull)
386 {
387 u16 reg, mask;
388 unsigned long flags;
389
390 if ((giu_flags & GPIO_HAS_PULLUPDOWN_IO) != GPIO_HAS_PULLUPDOWN_IO)
391 return -EPERM;
392
393 if (pin >= 15)
394 return -EINVAL;
395
396 mask = 1 << pin;
397
398 spin_lock_irqsave(&giu_lock, flags);
399
400 if (pull == GPIO_PULL_UP || pull == GPIO_PULL_DOWN) {
401 reg = giu_read(GIUTERMUPDN);
402 if (pull == GPIO_PULL_UP)
403 reg |= mask;
404 else
405 reg &= ~mask;
406 giu_write(GIUTERMUPDN, reg);
407
408 reg = giu_read(GIUUSEUPDN);
409 reg |= mask;
410 giu_write(GIUUSEUPDN, reg);
411 } else {
412 reg = giu_read(GIUUSEUPDN);
413 reg &= ~mask;
414 giu_write(GIUUSEUPDN, reg);
415 }
416
417 spin_unlock_irqrestore(&giu_lock, flags);
418
419 return 0;
420 }
421 EXPORT_SYMBOL_GPL(vr41xx_gpio_pullupdown);
422
vr41xx_gpio_get(struct gpio_chip * chip,unsigned pin)423 static int vr41xx_gpio_get(struct gpio_chip *chip, unsigned pin)
424 {
425 u16 reg, mask;
426
427 if (pin >= chip->ngpio)
428 return -EINVAL;
429
430 if (pin < 16) {
431 reg = giu_read(GIUPIODL);
432 mask = 1 << pin;
433 } else if (pin < 32) {
434 reg = giu_read(GIUPIODH);
435 mask = 1 << (pin - 16);
436 } else if (pin < 48) {
437 reg = giu_read(GIUPODATL);
438 mask = 1 << (pin - 32);
439 } else {
440 reg = giu_read(GIUPODATH);
441 mask = 1 << (pin - 48);
442 }
443
444 if (reg & mask)
445 return 1;
446
447 return 0;
448 }
449
vr41xx_gpio_set(struct gpio_chip * chip,unsigned pin,int value)450 static void vr41xx_gpio_set(struct gpio_chip *chip, unsigned pin,
451 int value)
452 {
453 u16 offset, mask, reg;
454 unsigned long flags;
455
456 if (pin >= chip->ngpio)
457 return;
458
459 if (pin < 16) {
460 offset = GIUPIODL;
461 mask = 1 << pin;
462 } else if (pin < 32) {
463 offset = GIUPIODH;
464 mask = 1 << (pin - 16);
465 } else if (pin < 48) {
466 offset = GIUPODATL;
467 mask = 1 << (pin - 32);
468 } else {
469 offset = GIUPODATH;
470 mask = 1 << (pin - 48);
471 }
472
473 spin_lock_irqsave(&giu_lock, flags);
474
475 reg = giu_read(offset);
476 if (value)
477 reg |= mask;
478 else
479 reg &= ~mask;
480 giu_write(offset, reg);
481
482 spin_unlock_irqrestore(&giu_lock, flags);
483 }
484
485
vr41xx_gpio_direction_input(struct gpio_chip * chip,unsigned offset)486 static int vr41xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
487 {
488 return giu_set_direction(chip, offset, GPIO_INPUT);
489 }
490
vr41xx_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)491 static int vr41xx_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
492 int value)
493 {
494 vr41xx_gpio_set(chip, offset, value);
495
496 return giu_set_direction(chip, offset, GPIO_OUTPUT);
497 }
498
vr41xx_gpio_to_irq(struct gpio_chip * chip,unsigned offset)499 static int vr41xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
500 {
501 if (offset >= chip->ngpio)
502 return -EINVAL;
503
504 return GIU_IRQ_BASE + offset;
505 }
506
507 static struct gpio_chip vr41xx_gpio_chip = {
508 .label = "vr41xx",
509 .owner = THIS_MODULE,
510 .direction_input = vr41xx_gpio_direction_input,
511 .get = vr41xx_gpio_get,
512 .direction_output = vr41xx_gpio_direction_output,
513 .set = vr41xx_gpio_set,
514 .to_irq = vr41xx_gpio_to_irq,
515 };
516
giu_probe(struct platform_device * pdev)517 static int giu_probe(struct platform_device *pdev)
518 {
519 struct resource *res;
520 unsigned int trigger, i, pin;
521 struct irq_chip *chip;
522 int irq, ret;
523
524 switch (pdev->id) {
525 case GPIO_50PINS_PULLUPDOWN:
526 giu_flags = GPIO_HAS_PULLUPDOWN_IO;
527 vr41xx_gpio_chip.ngpio = 50;
528 break;
529 case GPIO_36PINS:
530 vr41xx_gpio_chip.ngpio = 36;
531 break;
532 case GPIO_48PINS_EDGE_SELECT:
533 giu_flags = GPIO_HAS_INTERRUPT_EDGE_SELECT;
534 vr41xx_gpio_chip.ngpio = 48;
535 break;
536 default:
537 dev_err(&pdev->dev, "GIU: unknown ID %d\n", pdev->id);
538 return -ENODEV;
539 }
540
541 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
542 if (!res)
543 return -EBUSY;
544
545 giu_base = ioremap(res->start, resource_size(res));
546 if (!giu_base)
547 return -ENOMEM;
548
549 vr41xx_gpio_chip.parent = &pdev->dev;
550
551 ret = gpiochip_add_data(&vr41xx_gpio_chip, NULL);
552 if (!ret) {
553 iounmap(giu_base);
554 return -ENODEV;
555 }
556
557 giu_write(GIUINTENL, 0);
558 giu_write(GIUINTENH, 0);
559
560 trigger = giu_read(GIUINTTYPH) << 16;
561 trigger |= giu_read(GIUINTTYPL);
562 for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
563 pin = GPIO_PIN_OF_IRQ(i);
564 if (pin < GIUINT_HIGH_OFFSET)
565 chip = &giuint_low_irq_chip;
566 else
567 chip = &giuint_high_irq_chip;
568
569 if (trigger & (1 << pin))
570 irq_set_chip_and_handler(i, chip, handle_edge_irq);
571 else
572 irq_set_chip_and_handler(i, chip, handle_level_irq);
573
574 }
575
576 irq = platform_get_irq(pdev, 0);
577 if (irq < 0 || irq >= nr_irqs)
578 return -EBUSY;
579
580 return cascade_irq(irq, giu_get_irq);
581 }
582
giu_remove(struct platform_device * pdev)583 static int giu_remove(struct platform_device *pdev)
584 {
585 if (giu_base) {
586 iounmap(giu_base);
587 giu_base = NULL;
588 }
589
590 return 0;
591 }
592
593 static struct platform_driver giu_device_driver = {
594 .probe = giu_probe,
595 .remove = giu_remove,
596 .driver = {
597 .name = "GIU",
598 },
599 };
600
601 module_platform_driver(giu_device_driver);
602