1 /*
2  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; version 2 of the License.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  */
13 
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/delay.h>
17 #include <linux/errno.h>
18 #include <linux/i2c.h>
19 #include <linux/fs.h>
20 #include <linux/io.h>
21 #include <linux/types.h>
22 #include <linux/interrupt.h>
23 #include <linux/jiffies.h>
24 #include <linux/pci.h>
25 #include <linux/mutex.h>
26 #include <linux/ktime.h>
27 #include <linux/slab.h>
28 
29 #define PCH_EVENT_SET	0	/* I2C Interrupt Event Set Status */
30 #define PCH_EVENT_NONE	1	/* I2C Interrupt Event Clear Status */
31 #define PCH_MAX_CLK		100000	/* Maximum Clock speed in MHz */
32 #define PCH_BUFFER_MODE_ENABLE	0x0002	/* flag for Buffer mode enable */
33 #define PCH_EEPROM_SW_RST_MODE_ENABLE	0x0008	/* EEPROM SW RST enable flag */
34 
35 #define PCH_I2CSADR	0x00	/* I2C slave address register */
36 #define PCH_I2CCTL	0x04	/* I2C control register */
37 #define PCH_I2CSR	0x08	/* I2C status register */
38 #define PCH_I2CDR	0x0C	/* I2C data register */
39 #define PCH_I2CMON	0x10	/* I2C bus monitor register */
40 #define PCH_I2CBC	0x14	/* I2C bus transfer rate setup counter */
41 #define PCH_I2CMOD	0x18	/* I2C mode register */
42 #define PCH_I2CBUFSLV	0x1C	/* I2C buffer mode slave address register */
43 #define PCH_I2CBUFSUB	0x20	/* I2C buffer mode subaddress register */
44 #define PCH_I2CBUFFOR	0x24	/* I2C buffer mode format register */
45 #define PCH_I2CBUFCTL	0x28	/* I2C buffer mode control register */
46 #define PCH_I2CBUFMSK	0x2C	/* I2C buffer mode interrupt mask register */
47 #define PCH_I2CBUFSTA	0x30	/* I2C buffer mode status register */
48 #define PCH_I2CBUFLEV	0x34	/* I2C buffer mode level register */
49 #define PCH_I2CESRFOR	0x38	/* EEPROM software reset mode format register */
50 #define PCH_I2CESRCTL	0x3C	/* EEPROM software reset mode ctrl register */
51 #define PCH_I2CESRMSK	0x40	/* EEPROM software reset mode */
52 #define PCH_I2CESRSTA	0x44	/* EEPROM software reset mode status register */
53 #define PCH_I2CTMR	0x48	/* I2C timer register */
54 #define PCH_I2CSRST	0xFC	/* I2C reset register */
55 #define PCH_I2CNF	0xF8	/* I2C noise filter register */
56 
57 #define BUS_IDLE_TIMEOUT	20
58 #define PCH_I2CCTL_I2CMEN	0x0080
59 #define TEN_BIT_ADDR_DEFAULT	0xF000
60 #define TEN_BIT_ADDR_MASK	0xF0
61 #define PCH_START		0x0020
62 #define PCH_RESTART		0x0004
63 #define PCH_ESR_START		0x0001
64 #define PCH_BUFF_START		0x1
65 #define PCH_REPSTART		0x0004
66 #define PCH_ACK			0x0008
67 #define PCH_GETACK		0x0001
68 #define CLR_REG			0x0
69 #define I2C_RD			0x1
70 #define I2CMCF_BIT		0x0080
71 #define I2CMIF_BIT		0x0002
72 #define I2CMAL_BIT		0x0010
73 #define I2CBMFI_BIT		0x0001
74 #define I2CBMAL_BIT		0x0002
75 #define I2CBMNA_BIT		0x0004
76 #define I2CBMTO_BIT		0x0008
77 #define I2CBMIS_BIT		0x0010
78 #define I2CESRFI_BIT		0X0001
79 #define I2CESRTO_BIT		0x0002
80 #define I2CESRFIIE_BIT		0x1
81 #define I2CESRTOIE_BIT		0x2
82 #define I2CBMDZ_BIT		0x0040
83 #define I2CBMAG_BIT		0x0020
84 #define I2CMBB_BIT		0x0020
85 #define BUFFER_MODE_MASK	(I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
86 				I2CBMTO_BIT | I2CBMIS_BIT)
87 #define I2C_ADDR_MSK		0xFF
88 #define I2C_MSB_2B_MSK		0x300
89 #define FAST_MODE_CLK		400
90 #define FAST_MODE_EN		0x0001
91 #define SUB_ADDR_LEN_MAX	4
92 #define BUF_LEN_MAX		32
93 #define PCH_BUFFER_MODE		0x1
94 #define EEPROM_SW_RST_MODE	0x0002
95 #define NORMAL_INTR_ENBL	0x0300
96 #define EEPROM_RST_INTR_ENBL	(I2CESRFIIE_BIT | I2CESRTOIE_BIT)
97 #define EEPROM_RST_INTR_DISBL	0x0
98 #define BUFFER_MODE_INTR_ENBL	0x001F
99 #define BUFFER_MODE_INTR_DISBL	0x0
100 #define NORMAL_MODE		0x0
101 #define BUFFER_MODE		0x1
102 #define EEPROM_SR_MODE		0x2
103 #define I2C_TX_MODE		0x0010
104 #define PCH_BUF_TX		0xFFF7
105 #define PCH_BUF_RD		0x0008
106 #define I2C_ERROR_MASK	(I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
107 			I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
108 #define I2CMAL_EVENT		0x0001
109 #define I2CMCF_EVENT		0x0002
110 #define I2CBMFI_EVENT		0x0004
111 #define I2CBMAL_EVENT		0x0008
112 #define I2CBMNA_EVENT		0x0010
113 #define I2CBMTO_EVENT		0x0020
114 #define I2CBMIS_EVENT		0x0040
115 #define I2CESRFI_EVENT		0x0080
116 #define I2CESRTO_EVENT		0x0100
117 #define PCI_DEVICE_ID_PCH_I2C	0x8817
118 
119 #define pch_dbg(adap, fmt, arg...)  \
120 	dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
121 
122 #define pch_err(adap, fmt, arg...)  \
123 	dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
124 
125 #define pch_pci_err(pdev, fmt, arg...)  \
126 	dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
127 
128 #define pch_pci_dbg(pdev, fmt, arg...)  \
129 	dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
130 
131 /*
132 Set the number of I2C instance max
133 Intel EG20T PCH :		1ch
134 LAPIS Semiconductor ML7213 IOH :	2ch
135 LAPIS Semiconductor ML7831 IOH :	1ch
136 */
137 #define PCH_I2C_MAX_DEV			2
138 
139 /**
140  * struct i2c_algo_pch_data - for I2C driver functionalities
141  * @pch_adapter:		stores the reference to i2c_adapter structure
142  * @p_adapter_info:		stores the reference to adapter_info structure
143  * @pch_base_address:		specifies the remapped base address
144  * @pch_buff_mode_en:		specifies if buffer mode is enabled
145  * @pch_event_flag:		specifies occurrence of interrupt events
146  * @pch_i2c_xfer_in_progress:	specifies whether the transfer is completed
147  */
148 struct i2c_algo_pch_data {
149 	struct i2c_adapter pch_adapter;
150 	struct adapter_info *p_adapter_info;
151 	void __iomem *pch_base_address;
152 	int pch_buff_mode_en;
153 	u32 pch_event_flag;
154 	bool pch_i2c_xfer_in_progress;
155 };
156 
157 /**
158  * struct adapter_info - This structure holds the adapter information for the
159 			 PCH i2c controller
160  * @pch_data:		stores a list of i2c_algo_pch_data
161  * @pch_i2c_suspended:	specifies whether the system is suspended or not
162  *			perhaps with more lines and words.
163  * @ch_num:		specifies the number of i2c instance
164  *
165  * pch_data has as many elements as maximum I2C channels
166  */
167 struct adapter_info {
168 	struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV];
169 	bool pch_i2c_suspended;
170 	int ch_num;
171 };
172 
173 
174 static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
175 static int pch_clk = 50000;	/* specifies I2C clock speed in KHz */
176 static wait_queue_head_t pch_event;
177 static DEFINE_MUTEX(pch_mutex);
178 
179 /* Definition for ML7213 by LAPIS Semiconductor */
180 #define PCI_DEVICE_ID_ML7213_I2C	0x802D
181 #define PCI_DEVICE_ID_ML7223_I2C	0x8010
182 #define PCI_DEVICE_ID_ML7831_I2C	0x8817
183 
184 static const struct pci_device_id pch_pcidev_id[] = {
185 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C),   1, },
186 	{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
187 	{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, },
188 	{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_I2C), 1, },
189 	{0,}
190 };
191 MODULE_DEVICE_TABLE(pci, pch_pcidev_id);
192 
193 static irqreturn_t pch_i2c_handler(int irq, void *pData);
194 
pch_setbit(void __iomem * addr,u32 offset,u32 bitmask)195 static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
196 {
197 	u32 val;
198 	val = ioread32(addr + offset);
199 	val |= bitmask;
200 	iowrite32(val, addr + offset);
201 }
202 
pch_clrbit(void __iomem * addr,u32 offset,u32 bitmask)203 static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
204 {
205 	u32 val;
206 	val = ioread32(addr + offset);
207 	val &= (~bitmask);
208 	iowrite32(val, addr + offset);
209 }
210 
211 /**
212  * pch_i2c_init() - hardware initialization of I2C module
213  * @adap:	Pointer to struct i2c_algo_pch_data.
214  */
pch_i2c_init(struct i2c_algo_pch_data * adap)215 static void pch_i2c_init(struct i2c_algo_pch_data *adap)
216 {
217 	void __iomem *p = adap->pch_base_address;
218 	u32 pch_i2cbc;
219 	u32 pch_i2ctmr;
220 	u32 reg_value;
221 
222 	/* reset I2C controller */
223 	iowrite32(0x01, p + PCH_I2CSRST);
224 	msleep(20);
225 	iowrite32(0x0, p + PCH_I2CSRST);
226 
227 	/* Initialize I2C registers */
228 	iowrite32(0x21, p + PCH_I2CNF);
229 
230 	pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);
231 
232 	if (pch_i2c_speed != 400)
233 		pch_i2c_speed = 100;
234 
235 	reg_value = PCH_I2CCTL_I2CMEN;
236 	if (pch_i2c_speed == FAST_MODE_CLK) {
237 		reg_value |= FAST_MODE_EN;
238 		pch_dbg(adap, "Fast mode enabled\n");
239 	}
240 
241 	if (pch_clk > PCH_MAX_CLK)
242 		pch_clk = 62500;
243 
244 	pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
245 	/* Set transfer speed in I2CBC */
246 	iowrite32(pch_i2cbc, p + PCH_I2CBC);
247 
248 	pch_i2ctmr = (pch_clk) / 8;
249 	iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
250 
251 	reg_value |= NORMAL_INTR_ENBL;	/* Enable interrupts in normal mode */
252 	iowrite32(reg_value, p + PCH_I2CCTL);
253 
254 	pch_dbg(adap,
255 		"I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
256 		ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
257 
258 	init_waitqueue_head(&pch_event);
259 }
260 
261 /**
262  * pch_i2c_wait_for_bus_idle() - check the status of bus.
263  * @adap:	Pointer to struct i2c_algo_pch_data.
264  * @timeout:	waiting time counter (ms).
265  */
pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data * adap,s32 timeout)266 static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
267 				     s32 timeout)
268 {
269 	void __iomem *p = adap->pch_base_address;
270 	int schedule = 0;
271 	unsigned long end = jiffies + msecs_to_jiffies(timeout);
272 
273 	while (ioread32(p + PCH_I2CSR) & I2CMBB_BIT) {
274 		if (time_after(jiffies, end)) {
275 			pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
276 			pch_err(adap, "%s: Timeout Error.return%d\n",
277 					__func__, -ETIME);
278 			pch_i2c_init(adap);
279 
280 			return -ETIME;
281 		}
282 
283 		if (!schedule)
284 			/* Retry after some usecs */
285 			udelay(5);
286 		else
287 			/* Wait a bit more without consuming CPU */
288 			usleep_range(20, 1000);
289 
290 		schedule = 1;
291 	}
292 
293 	return 0;
294 }
295 
296 /**
297  * pch_i2c_start() - Generate I2C start condition in normal mode.
298  * @adap:	Pointer to struct i2c_algo_pch_data.
299  *
300  * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
301  */
pch_i2c_start(struct i2c_algo_pch_data * adap)302 static void pch_i2c_start(struct i2c_algo_pch_data *adap)
303 {
304 	void __iomem *p = adap->pch_base_address;
305 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
306 	pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
307 }
308 
309 /**
310  * pch_i2c_stop() - generate stop condition in normal mode.
311  * @adap:	Pointer to struct i2c_algo_pch_data.
312  */
pch_i2c_stop(struct i2c_algo_pch_data * adap)313 static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
314 {
315 	void __iomem *p = adap->pch_base_address;
316 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
317 	/* clear the start bit */
318 	pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
319 }
320 
pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data * adap)321 static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap)
322 {
323 	long ret;
324 	void __iomem *p = adap->pch_base_address;
325 
326 	ret = wait_event_timeout(pch_event,
327 			(adap->pch_event_flag != 0), msecs_to_jiffies(1000));
328 	if (!ret) {
329 		pch_err(adap, "%s:wait-event timeout\n", __func__);
330 		adap->pch_event_flag = 0;
331 		pch_i2c_stop(adap);
332 		pch_i2c_init(adap);
333 		return -ETIMEDOUT;
334 	}
335 
336 	if (adap->pch_event_flag & I2C_ERROR_MASK) {
337 		pch_err(adap, "Lost Arbitration\n");
338 		adap->pch_event_flag = 0;
339 		pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
340 		pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
341 		pch_i2c_init(adap);
342 		return -EAGAIN;
343 	}
344 
345 	adap->pch_event_flag = 0;
346 
347 	if (ioread32(p + PCH_I2CSR) & PCH_GETACK) {
348 		pch_dbg(adap, "Receive NACK for slave address setting\n");
349 		return -ENXIO;
350 	}
351 
352 	return 0;
353 }
354 
355 /**
356  * pch_i2c_repstart() - generate repeated start condition in normal mode
357  * @adap:	Pointer to struct i2c_algo_pch_data.
358  */
pch_i2c_repstart(struct i2c_algo_pch_data * adap)359 static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
360 {
361 	void __iomem *p = adap->pch_base_address;
362 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
363 	pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
364 }
365 
366 /**
367  * pch_i2c_writebytes() - write data to I2C bus in normal mode
368  * @i2c_adap:	Pointer to the struct i2c_adapter.
369  * @last:	specifies whether last message or not.
370  *		In the case of compound mode it will be 1 for last message,
371  *		otherwise 0.
372  * @first:	specifies whether first message or not.
373  *		1 for first message otherwise 0.
374  */
pch_i2c_writebytes(struct i2c_adapter * i2c_adap,struct i2c_msg * msgs,u32 last,u32 first)375 static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
376 			      struct i2c_msg *msgs, u32 last, u32 first)
377 {
378 	struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
379 	u8 *buf;
380 	u32 length;
381 	u32 addr;
382 	u32 addr_2_msb;
383 	u32 addr_8_lsb;
384 	s32 wrcount;
385 	s32 rtn;
386 	void __iomem *p = adap->pch_base_address;
387 
388 	length = msgs->len;
389 	buf = msgs->buf;
390 	addr = msgs->addr;
391 
392 	/* enable master tx */
393 	pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
394 
395 	pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
396 		length);
397 
398 	if (first) {
399 		if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
400 			return -ETIME;
401 	}
402 
403 	if (msgs->flags & I2C_M_TEN) {
404 		addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06;
405 		iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
406 		if (first)
407 			pch_i2c_start(adap);
408 
409 		rtn = pch_i2c_wait_for_check_xfer(adap);
410 		if (rtn)
411 			return rtn;
412 
413 		addr_8_lsb = (addr & I2C_ADDR_MSK);
414 		iowrite32(addr_8_lsb, p + PCH_I2CDR);
415 	} else {
416 		/* set 7 bit slave address and R/W bit as 0 */
417 		iowrite32(i2c_8bit_addr_from_msg(msgs), p + PCH_I2CDR);
418 		if (first)
419 			pch_i2c_start(adap);
420 	}
421 
422 	rtn = pch_i2c_wait_for_check_xfer(adap);
423 	if (rtn)
424 		return rtn;
425 
426 	for (wrcount = 0; wrcount < length; ++wrcount) {
427 		/* write buffer value to I2C data register */
428 		iowrite32(buf[wrcount], p + PCH_I2CDR);
429 		pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);
430 
431 		rtn = pch_i2c_wait_for_check_xfer(adap);
432 		if (rtn)
433 			return rtn;
434 
435 		pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMCF_BIT);
436 		pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
437 	}
438 
439 	/* check if this is the last message */
440 	if (last)
441 		pch_i2c_stop(adap);
442 	else
443 		pch_i2c_repstart(adap);
444 
445 	pch_dbg(adap, "return=%d\n", wrcount);
446 
447 	return wrcount;
448 }
449 
450 /**
451  * pch_i2c_sendack() - send ACK
452  * @adap:	Pointer to struct i2c_algo_pch_data.
453  */
pch_i2c_sendack(struct i2c_algo_pch_data * adap)454 static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
455 {
456 	void __iomem *p = adap->pch_base_address;
457 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
458 	pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
459 }
460 
461 /**
462  * pch_i2c_sendnack() - send NACK
463  * @adap:	Pointer to struct i2c_algo_pch_data.
464  */
pch_i2c_sendnack(struct i2c_algo_pch_data * adap)465 static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
466 {
467 	void __iomem *p = adap->pch_base_address;
468 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
469 	pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
470 }
471 
472 /**
473  * pch_i2c_restart() - Generate I2C restart condition in normal mode.
474  * @adap:	Pointer to struct i2c_algo_pch_data.
475  *
476  * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA.
477  */
pch_i2c_restart(struct i2c_algo_pch_data * adap)478 static void pch_i2c_restart(struct i2c_algo_pch_data *adap)
479 {
480 	void __iomem *p = adap->pch_base_address;
481 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
482 	pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);
483 }
484 
485 /**
486  * pch_i2c_readbytes() - read data  from I2C bus in normal mode.
487  * @i2c_adap:	Pointer to the struct i2c_adapter.
488  * @msgs:	Pointer to i2c_msg structure.
489  * @last:	specifies whether last message or not.
490  * @first:	specifies whether first message or not.
491  */
pch_i2c_readbytes(struct i2c_adapter * i2c_adap,struct i2c_msg * msgs,u32 last,u32 first)492 static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
493 			     u32 last, u32 first)
494 {
495 	struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
496 
497 	u8 *buf;
498 	u32 count;
499 	u32 length;
500 	u32 addr;
501 	u32 addr_2_msb;
502 	u32 addr_8_lsb;
503 	void __iomem *p = adap->pch_base_address;
504 	s32 rtn;
505 
506 	length = msgs->len;
507 	buf = msgs->buf;
508 	addr = msgs->addr;
509 
510 	/* enable master reception */
511 	pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
512 
513 	if (first) {
514 		if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
515 			return -ETIME;
516 	}
517 
518 	if (msgs->flags & I2C_M_TEN) {
519 		addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
520 		iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
521 		if (first)
522 			pch_i2c_start(adap);
523 
524 		rtn = pch_i2c_wait_for_check_xfer(adap);
525 		if (rtn)
526 			return rtn;
527 
528 		addr_8_lsb = (addr & I2C_ADDR_MSK);
529 		iowrite32(addr_8_lsb, p + PCH_I2CDR);
530 
531 		pch_i2c_restart(adap);
532 
533 		rtn = pch_i2c_wait_for_check_xfer(adap);
534 		if (rtn)
535 			return rtn;
536 
537 		addr_2_msb |= I2C_RD;
538 		iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
539 	} else {
540 		/* 7 address bits + R/W bit */
541 		iowrite32(i2c_8bit_addr_from_msg(msgs), p + PCH_I2CDR);
542 	}
543 
544 	/* check if it is the first message */
545 	if (first)
546 		pch_i2c_start(adap);
547 
548 	rtn = pch_i2c_wait_for_check_xfer(adap);
549 	if (rtn)
550 		return rtn;
551 
552 	if (length == 0) {
553 		pch_i2c_stop(adap);
554 		ioread32(p + PCH_I2CDR); /* Dummy read needs */
555 
556 		count = length;
557 	} else {
558 		int read_index;
559 		int loop;
560 		pch_i2c_sendack(adap);
561 
562 		/* Dummy read */
563 		for (loop = 1, read_index = 0; loop < length; loop++) {
564 			buf[read_index] = ioread32(p + PCH_I2CDR);
565 
566 			if (loop != 1)
567 				read_index++;
568 
569 			rtn = pch_i2c_wait_for_check_xfer(adap);
570 			if (rtn)
571 				return rtn;
572 		}	/* end for */
573 
574 		pch_i2c_sendnack(adap);
575 
576 		buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */
577 
578 		if (length != 1)
579 			read_index++;
580 
581 		rtn = pch_i2c_wait_for_check_xfer(adap);
582 		if (rtn)
583 			return rtn;
584 
585 		if (last)
586 			pch_i2c_stop(adap);
587 		else
588 			pch_i2c_repstart(adap);
589 
590 		buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */
591 		count = read_index;
592 	}
593 
594 	return count;
595 }
596 
597 /**
598  * pch_i2c_cb() - Interrupt handler Call back function
599  * @adap:	Pointer to struct i2c_algo_pch_data.
600  */
pch_i2c_cb(struct i2c_algo_pch_data * adap)601 static void pch_i2c_cb(struct i2c_algo_pch_data *adap)
602 {
603 	u32 sts;
604 	void __iomem *p = adap->pch_base_address;
605 
606 	sts = ioread32(p + PCH_I2CSR);
607 	sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
608 	if (sts & I2CMAL_BIT)
609 		adap->pch_event_flag |= I2CMAL_EVENT;
610 
611 	if (sts & I2CMCF_BIT)
612 		adap->pch_event_flag |= I2CMCF_EVENT;
613 
614 	/* clear the applicable bits */
615 	pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
616 
617 	pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
618 
619 	wake_up(&pch_event);
620 }
621 
622 /**
623  * pch_i2c_handler() - interrupt handler for the PCH I2C controller
624  * @irq:	irq number.
625  * @pData:	cookie passed back to the handler function.
626  */
pch_i2c_handler(int irq,void * pData)627 static irqreturn_t pch_i2c_handler(int irq, void *pData)
628 {
629 	u32 reg_val;
630 	int flag;
631 	int i;
632 	struct adapter_info *adap_info = pData;
633 	void __iomem *p;
634 	u32 mode;
635 
636 	for (i = 0, flag = 0; i < adap_info->ch_num; i++) {
637 		p = adap_info->pch_data[i].pch_base_address;
638 		mode = ioread32(p + PCH_I2CMOD);
639 		mode &= BUFFER_MODE | EEPROM_SR_MODE;
640 		if (mode != NORMAL_MODE) {
641 			pch_err(adap_info->pch_data,
642 				"I2C-%d mode(%d) is not supported\n", mode, i);
643 			continue;
644 		}
645 		reg_val = ioread32(p + PCH_I2CSR);
646 		if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {
647 			pch_i2c_cb(&adap_info->pch_data[i]);
648 			flag = 1;
649 		}
650 	}
651 
652 	return flag ? IRQ_HANDLED : IRQ_NONE;
653 }
654 
655 /**
656  * pch_i2c_xfer() - Reading adnd writing data through I2C bus
657  * @i2c_adap:	Pointer to the struct i2c_adapter.
658  * @msgs:	Pointer to i2c_msg structure.
659  * @num:	number of messages.
660  */
pch_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msgs,s32 num)661 static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
662 			struct i2c_msg *msgs, s32 num)
663 {
664 	struct i2c_msg *pmsg;
665 	u32 i = 0;
666 	u32 status;
667 	s32 ret;
668 
669 	struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
670 
671 	ret = mutex_lock_interruptible(&pch_mutex);
672 	if (ret)
673 		return ret;
674 
675 	if (adap->p_adapter_info->pch_i2c_suspended) {
676 		mutex_unlock(&pch_mutex);
677 		return -EBUSY;
678 	}
679 
680 	pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
681 		adap->p_adapter_info->pch_i2c_suspended);
682 	/* transfer not completed */
683 	adap->pch_i2c_xfer_in_progress = true;
684 
685 	for (i = 0; i < num && ret >= 0; i++) {
686 		pmsg = &msgs[i];
687 		pmsg->flags |= adap->pch_buff_mode_en;
688 		status = pmsg->flags;
689 		pch_dbg(adap,
690 			"After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
691 
692 		if ((status & (I2C_M_RD)) != false) {
693 			ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
694 						(i == 0));
695 		} else {
696 			ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
697 						 (i == 0));
698 		}
699 	}
700 
701 	adap->pch_i2c_xfer_in_progress = false;	/* transfer completed */
702 
703 	mutex_unlock(&pch_mutex);
704 
705 	return (ret < 0) ? ret : num;
706 }
707 
708 /**
709  * pch_i2c_func() - return the functionality of the I2C driver
710  * @adap:	Pointer to struct i2c_algo_pch_data.
711  */
pch_i2c_func(struct i2c_adapter * adap)712 static u32 pch_i2c_func(struct i2c_adapter *adap)
713 {
714 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
715 }
716 
717 static const struct i2c_algorithm pch_algorithm = {
718 	.master_xfer = pch_i2c_xfer,
719 	.functionality = pch_i2c_func
720 };
721 
722 /**
723  * pch_i2c_disbl_int() - Disable PCH I2C interrupts
724  * @adap:	Pointer to struct i2c_algo_pch_data.
725  */
pch_i2c_disbl_int(struct i2c_algo_pch_data * adap)726 static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
727 {
728 	void __iomem *p = adap->pch_base_address;
729 
730 	pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
731 
732 	iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
733 
734 	iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
735 }
736 
pch_i2c_probe(struct pci_dev * pdev,const struct pci_device_id * id)737 static int pch_i2c_probe(struct pci_dev *pdev,
738 				   const struct pci_device_id *id)
739 {
740 	void __iomem *base_addr;
741 	int ret;
742 	int i, j;
743 	struct adapter_info *adap_info;
744 	struct i2c_adapter *pch_adap;
745 
746 	pch_pci_dbg(pdev, "Entered.\n");
747 
748 	adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
749 	if (adap_info == NULL)
750 		return -ENOMEM;
751 
752 	ret = pci_enable_device(pdev);
753 	if (ret) {
754 		pch_pci_err(pdev, "pci_enable_device FAILED\n");
755 		goto err_pci_enable;
756 	}
757 
758 	ret = pci_request_regions(pdev, KBUILD_MODNAME);
759 	if (ret) {
760 		pch_pci_err(pdev, "pci_request_regions FAILED\n");
761 		goto err_pci_req;
762 	}
763 
764 	base_addr = pci_iomap(pdev, 1, 0);
765 
766 	if (base_addr == NULL) {
767 		pch_pci_err(pdev, "pci_iomap FAILED\n");
768 		ret = -ENOMEM;
769 		goto err_pci_iomap;
770 	}
771 
772 	/* Set the number of I2C channel instance */
773 	adap_info->ch_num = id->driver_data;
774 
775 	for (i = 0; i < adap_info->ch_num; i++) {
776 		pch_adap = &adap_info->pch_data[i].pch_adapter;
777 		adap_info->pch_i2c_suspended = false;
778 
779 		adap_info->pch_data[i].p_adapter_info = adap_info;
780 
781 		pch_adap->owner = THIS_MODULE;
782 		pch_adap->class = I2C_CLASS_HWMON;
783 		strlcpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name));
784 		pch_adap->algo = &pch_algorithm;
785 		pch_adap->algo_data = &adap_info->pch_data[i];
786 
787 		/* base_addr + offset; */
788 		adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
789 
790 		pch_adap->dev.of_node = pdev->dev.of_node;
791 		pch_adap->dev.parent = &pdev->dev;
792 	}
793 
794 	ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
795 		  KBUILD_MODNAME, adap_info);
796 	if (ret) {
797 		pch_pci_err(pdev, "request_irq FAILED\n");
798 		goto err_request_irq;
799 	}
800 
801 	for (i = 0; i < adap_info->ch_num; i++) {
802 		pch_adap = &adap_info->pch_data[i].pch_adapter;
803 
804 		pch_i2c_init(&adap_info->pch_data[i]);
805 
806 		pch_adap->nr = i;
807 		ret = i2c_add_numbered_adapter(pch_adap);
808 		if (ret) {
809 			pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i);
810 			goto err_add_adapter;
811 		}
812 	}
813 
814 	pci_set_drvdata(pdev, adap_info);
815 	pch_pci_dbg(pdev, "returns %d.\n", ret);
816 	return 0;
817 
818 err_add_adapter:
819 	for (j = 0; j < i; j++)
820 		i2c_del_adapter(&adap_info->pch_data[j].pch_adapter);
821 	free_irq(pdev->irq, adap_info);
822 err_request_irq:
823 	pci_iounmap(pdev, base_addr);
824 err_pci_iomap:
825 	pci_release_regions(pdev);
826 err_pci_req:
827 	pci_disable_device(pdev);
828 err_pci_enable:
829 	kfree(adap_info);
830 	return ret;
831 }
832 
pch_i2c_remove(struct pci_dev * pdev)833 static void pch_i2c_remove(struct pci_dev *pdev)
834 {
835 	int i;
836 	struct adapter_info *adap_info = pci_get_drvdata(pdev);
837 
838 	free_irq(pdev->irq, adap_info);
839 
840 	for (i = 0; i < adap_info->ch_num; i++) {
841 		pch_i2c_disbl_int(&adap_info->pch_data[i]);
842 		i2c_del_adapter(&adap_info->pch_data[i].pch_adapter);
843 	}
844 
845 	if (adap_info->pch_data[0].pch_base_address)
846 		pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
847 
848 	for (i = 0; i < adap_info->ch_num; i++)
849 		adap_info->pch_data[i].pch_base_address = NULL;
850 
851 	pci_release_regions(pdev);
852 
853 	pci_disable_device(pdev);
854 	kfree(adap_info);
855 }
856 
857 #ifdef CONFIG_PM
pch_i2c_suspend(struct pci_dev * pdev,pm_message_t state)858 static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state)
859 {
860 	int ret;
861 	int i;
862 	struct adapter_info *adap_info = pci_get_drvdata(pdev);
863 	void __iomem *p = adap_info->pch_data[0].pch_base_address;
864 
865 	adap_info->pch_i2c_suspended = true;
866 
867 	for (i = 0; i < adap_info->ch_num; i++) {
868 		while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) {
869 			/* Wait until all channel transfers are completed */
870 			msleep(20);
871 		}
872 	}
873 
874 	/* Disable the i2c interrupts */
875 	for (i = 0; i < adap_info->ch_num; i++)
876 		pch_i2c_disbl_int(&adap_info->pch_data[i]);
877 
878 	pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
879 		"invoked function pch_i2c_disbl_int successfully\n",
880 		ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
881 		ioread32(p + PCH_I2CESRSTA));
882 
883 	ret = pci_save_state(pdev);
884 
885 	if (ret) {
886 		pch_pci_err(pdev, "pci_save_state\n");
887 		return ret;
888 	}
889 
890 	pci_enable_wake(pdev, PCI_D3hot, 0);
891 	pci_disable_device(pdev);
892 	pci_set_power_state(pdev, pci_choose_state(pdev, state));
893 
894 	return 0;
895 }
896 
pch_i2c_resume(struct pci_dev * pdev)897 static int pch_i2c_resume(struct pci_dev *pdev)
898 {
899 	int i;
900 	struct adapter_info *adap_info = pci_get_drvdata(pdev);
901 
902 	pci_set_power_state(pdev, PCI_D0);
903 	pci_restore_state(pdev);
904 
905 	if (pci_enable_device(pdev) < 0) {
906 		pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n");
907 		return -EIO;
908 	}
909 
910 	pci_enable_wake(pdev, PCI_D3hot, 0);
911 
912 	for (i = 0; i < adap_info->ch_num; i++)
913 		pch_i2c_init(&adap_info->pch_data[i]);
914 
915 	adap_info->pch_i2c_suspended = false;
916 
917 	return 0;
918 }
919 #else
920 #define pch_i2c_suspend NULL
921 #define pch_i2c_resume NULL
922 #endif
923 
924 static struct pci_driver pch_pcidriver = {
925 	.name = KBUILD_MODNAME,
926 	.id_table = pch_pcidev_id,
927 	.probe = pch_i2c_probe,
928 	.remove = pch_i2c_remove,
929 	.suspend = pch_i2c_suspend,
930 	.resume = pch_i2c_resume
931 };
932 
933 module_pci_driver(pch_pcidriver);
934 
935 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semico ML7213/ML7223/ML7831 IOH I2C");
936 MODULE_LICENSE("GPL");
937 MODULE_AUTHOR("Tomoya MORINAGA. <tomoya.rohm@gmail.com>");
938 module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
939 module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
940