1 /*
2 * I2C bus driver for Amlogic Meson SoCs
3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/clk.h>
13 #include <linux/completion.h>
14 #include <linux/i2c.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/types.h>
23
24 /* Meson I2C register map */
25 #define REG_CTRL 0x00
26 #define REG_SLAVE_ADDR 0x04
27 #define REG_TOK_LIST0 0x08
28 #define REG_TOK_LIST1 0x0c
29 #define REG_TOK_WDATA0 0x10
30 #define REG_TOK_WDATA1 0x14
31 #define REG_TOK_RDATA0 0x18
32 #define REG_TOK_RDATA1 0x1c
33
34 /* Control register fields */
35 #define REG_CTRL_START BIT(0)
36 #define REG_CTRL_ACK_IGNORE BIT(1)
37 #define REG_CTRL_STATUS BIT(2)
38 #define REG_CTRL_ERROR BIT(3)
39 #define REG_CTRL_CLKDIV GENMASK(21, 12)
40 #define REG_CTRL_CLKDIVEXT GENMASK(29, 28)
41
42 #define REG_SLV_ADDR GENMASK(7, 0)
43 #define REG_SLV_SDA_FILTER GENMASK(10, 8)
44 #define REG_SLV_SCL_FILTER GENMASK(13, 11)
45 #define REG_SLV_SCL_LOW GENMASK(27, 16)
46 #define REG_SLV_SCL_LOW_EN BIT(28)
47
48 #define I2C_TIMEOUT_MS 500
49 #define FILTER_DELAY 15
50
51 enum {
52 TOKEN_END = 0,
53 TOKEN_START,
54 TOKEN_SLAVE_ADDR_WRITE,
55 TOKEN_SLAVE_ADDR_READ,
56 TOKEN_DATA,
57 TOKEN_DATA_LAST,
58 TOKEN_STOP,
59 };
60
61 enum {
62 STATE_IDLE,
63 STATE_READ,
64 STATE_WRITE,
65 };
66
67 struct meson_i2c_data {
68 unsigned char div_factor;
69 };
70
71 /**
72 * struct meson_i2c - Meson I2C device private data
73 *
74 * @adap: I2C adapter instance
75 * @dev: Pointer to device structure
76 * @regs: Base address of the device memory mapped registers
77 * @clk: Pointer to clock structure
78 * @msg: Pointer to the current I2C message
79 * @state: Current state in the driver state machine
80 * @last: Flag set for the last message in the transfer
81 * @count: Number of bytes to be sent/received in current transfer
82 * @pos: Current position in the send/receive buffer
83 * @error: Flag set when an error is received
84 * @lock: To avoid race conditions between irq handler and xfer code
85 * @done: Completion used to wait for transfer termination
86 * @tokens: Sequence of tokens to be written to the device
87 * @num_tokens: Number of tokens
88 * @data: Pointer to the controlller's platform data
89 */
90 struct meson_i2c {
91 struct i2c_adapter adap;
92 struct device *dev;
93 void __iomem *regs;
94 struct clk *clk;
95
96 struct i2c_msg *msg;
97 int state;
98 bool last;
99 int count;
100 int pos;
101 int error;
102
103 spinlock_t lock;
104 struct completion done;
105 u32 tokens[2];
106 int num_tokens;
107
108 const struct meson_i2c_data *data;
109 };
110
meson_i2c_set_mask(struct meson_i2c * i2c,int reg,u32 mask,u32 val)111 static void meson_i2c_set_mask(struct meson_i2c *i2c, int reg, u32 mask,
112 u32 val)
113 {
114 u32 data;
115
116 data = readl(i2c->regs + reg);
117 data &= ~mask;
118 data |= val & mask;
119 writel(data, i2c->regs + reg);
120 }
121
meson_i2c_reset_tokens(struct meson_i2c * i2c)122 static void meson_i2c_reset_tokens(struct meson_i2c *i2c)
123 {
124 i2c->tokens[0] = 0;
125 i2c->tokens[1] = 0;
126 i2c->num_tokens = 0;
127 }
128
meson_i2c_add_token(struct meson_i2c * i2c,int token)129 static void meson_i2c_add_token(struct meson_i2c *i2c, int token)
130 {
131 if (i2c->num_tokens < 8)
132 i2c->tokens[0] |= (token & 0xf) << (i2c->num_tokens * 4);
133 else
134 i2c->tokens[1] |= (token & 0xf) << ((i2c->num_tokens % 8) * 4);
135
136 i2c->num_tokens++;
137 }
138
meson_i2c_set_clk_div(struct meson_i2c * i2c,unsigned int freq)139 static void meson_i2c_set_clk_div(struct meson_i2c *i2c, unsigned int freq)
140 {
141 unsigned long clk_rate = clk_get_rate(i2c->clk);
142 unsigned int div;
143
144 div = DIV_ROUND_UP(clk_rate, freq);
145 div -= FILTER_DELAY;
146 div = DIV_ROUND_UP(div, i2c->data->div_factor);
147
148 /* clock divider has 12 bits */
149 if (div > GENMASK(11, 0)) {
150 dev_err(i2c->dev, "requested bus frequency too low\n");
151 div = GENMASK(11, 0);
152 }
153
154 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV,
155 FIELD_PREP(REG_CTRL_CLKDIV, div & GENMASK(9, 0)));
156
157 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIVEXT,
158 FIELD_PREP(REG_CTRL_CLKDIVEXT, div >> 10));
159
160 /* Disable HIGH/LOW mode */
161 meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_SCL_LOW_EN, 0);
162
163 dev_dbg(i2c->dev, "%s: clk %lu, freq %u, div %u\n", __func__,
164 clk_rate, freq, div);
165 }
166
meson_i2c_get_data(struct meson_i2c * i2c,char * buf,int len)167 static void meson_i2c_get_data(struct meson_i2c *i2c, char *buf, int len)
168 {
169 u32 rdata0, rdata1;
170 int i;
171
172 rdata0 = readl(i2c->regs + REG_TOK_RDATA0);
173 rdata1 = readl(i2c->regs + REG_TOK_RDATA1);
174
175 dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
176 rdata0, rdata1, len);
177
178 for (i = 0; i < min(4, len); i++)
179 *buf++ = (rdata0 >> i * 8) & 0xff;
180
181 for (i = 4; i < min(8, len); i++)
182 *buf++ = (rdata1 >> (i - 4) * 8) & 0xff;
183 }
184
meson_i2c_put_data(struct meson_i2c * i2c,char * buf,int len)185 static void meson_i2c_put_data(struct meson_i2c *i2c, char *buf, int len)
186 {
187 u32 wdata0 = 0, wdata1 = 0;
188 int i;
189
190 for (i = 0; i < min(4, len); i++)
191 wdata0 |= *buf++ << (i * 8);
192
193 for (i = 4; i < min(8, len); i++)
194 wdata1 |= *buf++ << ((i - 4) * 8);
195
196 writel(wdata0, i2c->regs + REG_TOK_WDATA0);
197 writel(wdata1, i2c->regs + REG_TOK_WDATA1);
198
199 dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
200 wdata0, wdata1, len);
201 }
202
meson_i2c_prepare_xfer(struct meson_i2c * i2c)203 static void meson_i2c_prepare_xfer(struct meson_i2c *i2c)
204 {
205 bool write = !(i2c->msg->flags & I2C_M_RD);
206 int i;
207
208 i2c->count = min(i2c->msg->len - i2c->pos, 8);
209
210 for (i = 0; i < i2c->count - 1; i++)
211 meson_i2c_add_token(i2c, TOKEN_DATA);
212
213 if (i2c->count) {
214 if (write || i2c->pos + i2c->count < i2c->msg->len)
215 meson_i2c_add_token(i2c, TOKEN_DATA);
216 else
217 meson_i2c_add_token(i2c, TOKEN_DATA_LAST);
218 }
219
220 if (write)
221 meson_i2c_put_data(i2c, i2c->msg->buf + i2c->pos, i2c->count);
222
223 if (i2c->last && i2c->pos + i2c->count >= i2c->msg->len)
224 meson_i2c_add_token(i2c, TOKEN_STOP);
225
226 writel(i2c->tokens[0], i2c->regs + REG_TOK_LIST0);
227 writel(i2c->tokens[1], i2c->regs + REG_TOK_LIST1);
228 }
229
meson_i2c_irq(int irqno,void * dev_id)230 static irqreturn_t meson_i2c_irq(int irqno, void *dev_id)
231 {
232 struct meson_i2c *i2c = dev_id;
233 unsigned int ctrl;
234
235 spin_lock(&i2c->lock);
236
237 meson_i2c_reset_tokens(i2c);
238 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
239 ctrl = readl(i2c->regs + REG_CTRL);
240
241 dev_dbg(i2c->dev, "irq: state %d, pos %d, count %d, ctrl %08x\n",
242 i2c->state, i2c->pos, i2c->count, ctrl);
243
244 if (i2c->state == STATE_IDLE) {
245 spin_unlock(&i2c->lock);
246 return IRQ_NONE;
247 }
248
249 if (ctrl & REG_CTRL_ERROR) {
250 /*
251 * The bit is set when the IGNORE_NAK bit is cleared
252 * and the device didn't respond. In this case, the
253 * I2C controller automatically generates a STOP
254 * condition.
255 */
256 dev_dbg(i2c->dev, "error bit set\n");
257 i2c->error = -ENXIO;
258 i2c->state = STATE_IDLE;
259 complete(&i2c->done);
260 goto out;
261 }
262
263 if (i2c->state == STATE_READ && i2c->count)
264 meson_i2c_get_data(i2c, i2c->msg->buf + i2c->pos, i2c->count);
265
266 i2c->pos += i2c->count;
267
268 if (i2c->pos >= i2c->msg->len) {
269 i2c->state = STATE_IDLE;
270 complete(&i2c->done);
271 goto out;
272 }
273
274 /* Restart the processing */
275 meson_i2c_prepare_xfer(i2c);
276 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
277 out:
278 spin_unlock(&i2c->lock);
279
280 return IRQ_HANDLED;
281 }
282
meson_i2c_do_start(struct meson_i2c * i2c,struct i2c_msg * msg)283 static void meson_i2c_do_start(struct meson_i2c *i2c, struct i2c_msg *msg)
284 {
285 int token;
286
287 token = (msg->flags & I2C_M_RD) ? TOKEN_SLAVE_ADDR_READ :
288 TOKEN_SLAVE_ADDR_WRITE;
289
290
291 meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_ADDR,
292 FIELD_PREP(REG_SLV_ADDR, msg->addr << 1));
293
294 meson_i2c_add_token(i2c, TOKEN_START);
295 meson_i2c_add_token(i2c, token);
296 }
297
meson_i2c_xfer_msg(struct meson_i2c * i2c,struct i2c_msg * msg,int last)298 static int meson_i2c_xfer_msg(struct meson_i2c *i2c, struct i2c_msg *msg,
299 int last)
300 {
301 unsigned long time_left, flags;
302 int ret = 0;
303
304 i2c->msg = msg;
305 i2c->last = last;
306 i2c->pos = 0;
307 i2c->count = 0;
308 i2c->error = 0;
309
310 meson_i2c_reset_tokens(i2c);
311
312 flags = (msg->flags & I2C_M_IGNORE_NAK) ? REG_CTRL_ACK_IGNORE : 0;
313 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_ACK_IGNORE, flags);
314
315 if (!(msg->flags & I2C_M_NOSTART))
316 meson_i2c_do_start(i2c, msg);
317
318 i2c->state = (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
319 meson_i2c_prepare_xfer(i2c);
320 reinit_completion(&i2c->done);
321
322 /* Start the transfer */
323 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
324
325 time_left = msecs_to_jiffies(I2C_TIMEOUT_MS);
326 time_left = wait_for_completion_timeout(&i2c->done, time_left);
327
328 /*
329 * Protect access to i2c struct and registers from interrupt
330 * handlers triggered by a transfer terminated after the
331 * timeout period
332 */
333 spin_lock_irqsave(&i2c->lock, flags);
334
335 /* Abort any active operation */
336 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
337
338 if (!time_left) {
339 i2c->state = STATE_IDLE;
340 ret = -ETIMEDOUT;
341 }
342
343 if (i2c->error)
344 ret = i2c->error;
345
346 spin_unlock_irqrestore(&i2c->lock, flags);
347
348 return ret;
349 }
350
meson_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)351 static int meson_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
352 int num)
353 {
354 struct meson_i2c *i2c = adap->algo_data;
355 int i, ret = 0;
356
357 clk_enable(i2c->clk);
358
359 for (i = 0; i < num; i++) {
360 ret = meson_i2c_xfer_msg(i2c, msgs + i, i == num - 1);
361 if (ret)
362 break;
363 }
364
365 clk_disable(i2c->clk);
366
367 return ret ?: i;
368 }
369
meson_i2c_func(struct i2c_adapter * adap)370 static u32 meson_i2c_func(struct i2c_adapter *adap)
371 {
372 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
373 }
374
375 static const struct i2c_algorithm meson_i2c_algorithm = {
376 .master_xfer = meson_i2c_xfer,
377 .functionality = meson_i2c_func,
378 };
379
meson_i2c_probe(struct platform_device * pdev)380 static int meson_i2c_probe(struct platform_device *pdev)
381 {
382 struct device_node *np = pdev->dev.of_node;
383 struct meson_i2c *i2c;
384 struct resource *mem;
385 struct i2c_timings timings;
386 int irq, ret = 0;
387
388 i2c = devm_kzalloc(&pdev->dev, sizeof(struct meson_i2c), GFP_KERNEL);
389 if (!i2c)
390 return -ENOMEM;
391
392 i2c_parse_fw_timings(&pdev->dev, &timings, true);
393
394 i2c->dev = &pdev->dev;
395 platform_set_drvdata(pdev, i2c);
396
397 spin_lock_init(&i2c->lock);
398 init_completion(&i2c->done);
399
400 i2c->data = (const struct meson_i2c_data *)
401 of_device_get_match_data(&pdev->dev);
402
403 i2c->clk = devm_clk_get(&pdev->dev, NULL);
404 if (IS_ERR(i2c->clk)) {
405 dev_err(&pdev->dev, "can't get device clock\n");
406 return PTR_ERR(i2c->clk);
407 }
408
409 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
410 i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
411 if (IS_ERR(i2c->regs))
412 return PTR_ERR(i2c->regs);
413
414 irq = platform_get_irq(pdev, 0);
415 if (irq < 0) {
416 dev_err(&pdev->dev, "can't find IRQ\n");
417 return irq;
418 }
419
420 ret = devm_request_irq(&pdev->dev, irq, meson_i2c_irq, 0, NULL, i2c);
421 if (ret < 0) {
422 dev_err(&pdev->dev, "can't request IRQ\n");
423 return ret;
424 }
425
426 ret = clk_prepare(i2c->clk);
427 if (ret < 0) {
428 dev_err(&pdev->dev, "can't prepare clock\n");
429 return ret;
430 }
431
432 strlcpy(i2c->adap.name, "Meson I2C adapter",
433 sizeof(i2c->adap.name));
434 i2c->adap.owner = THIS_MODULE;
435 i2c->adap.algo = &meson_i2c_algorithm;
436 i2c->adap.dev.parent = &pdev->dev;
437 i2c->adap.dev.of_node = np;
438 i2c->adap.algo_data = i2c;
439
440 /*
441 * A transfer is triggered when START bit changes from 0 to 1.
442 * Ensure that the bit is set to 0 after probe
443 */
444 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
445
446 ret = i2c_add_adapter(&i2c->adap);
447 if (ret < 0) {
448 clk_unprepare(i2c->clk);
449 return ret;
450 }
451
452 /* Disable filtering */
453 meson_i2c_set_mask(i2c, REG_SLAVE_ADDR,
454 REG_SLV_SDA_FILTER | REG_SLV_SCL_FILTER, 0);
455
456 meson_i2c_set_clk_div(i2c, timings.bus_freq_hz);
457
458 return 0;
459 }
460
meson_i2c_remove(struct platform_device * pdev)461 static int meson_i2c_remove(struct platform_device *pdev)
462 {
463 struct meson_i2c *i2c = platform_get_drvdata(pdev);
464
465 i2c_del_adapter(&i2c->adap);
466 clk_unprepare(i2c->clk);
467
468 return 0;
469 }
470
471 static const struct meson_i2c_data i2c_meson6_data = {
472 .div_factor = 4,
473 };
474
475 static const struct meson_i2c_data i2c_gxbb_data = {
476 .div_factor = 4,
477 };
478
479 static const struct meson_i2c_data i2c_axg_data = {
480 .div_factor = 3,
481 };
482
483 static const struct of_device_id meson_i2c_match[] = {
484 { .compatible = "amlogic,meson6-i2c", .data = &i2c_meson6_data },
485 { .compatible = "amlogic,meson-gxbb-i2c", .data = &i2c_gxbb_data },
486 { .compatible = "amlogic,meson-axg-i2c", .data = &i2c_axg_data },
487 {},
488 };
489
490 MODULE_DEVICE_TABLE(of, meson_i2c_match);
491
492 static struct platform_driver meson_i2c_driver = {
493 .probe = meson_i2c_probe,
494 .remove = meson_i2c_remove,
495 .driver = {
496 .name = "meson-i2c",
497 .of_match_table = meson_i2c_match,
498 },
499 };
500
501 module_platform_driver(meson_i2c_driver);
502
503 MODULE_DESCRIPTION("Amlogic Meson I2C Bus driver");
504 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
505 MODULE_LICENSE("GPL v2");
506