1 /*
2  * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
3  * (https://opencores.org/project/i2c/overview)
4  *
5  * Peter Korsgaard <peter@korsgaard.com>
6  *
7  * Support for the GRLIB port of the controller by
8  * Andreas Larsson <andreas@gaisler.com>
9  *
10  * This file is licensed under the terms of the GNU General Public License
11  * version 2.  This program is licensed "as is" without any warranty of any
12  * kind, whether express or implied.
13  */
14 
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/errno.h>
20 #include <linux/platform_device.h>
21 #include <linux/i2c.h>
22 #include <linux/interrupt.h>
23 #include <linux/wait.h>
24 #include <linux/platform_data/i2c-ocores.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/log2.h>
28 
29 struct ocores_i2c {
30 	void __iomem *base;
31 	u32 reg_shift;
32 	u32 reg_io_width;
33 	wait_queue_head_t wait;
34 	struct i2c_adapter adap;
35 	struct i2c_msg *msg;
36 	int pos;
37 	int nmsgs;
38 	int state; /* see STATE_ */
39 	struct clk *clk;
40 	int ip_clock_khz;
41 	int bus_clock_khz;
42 	void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
43 	u8 (*getreg)(struct ocores_i2c *i2c, int reg);
44 };
45 
46 /* registers */
47 #define OCI2C_PRELOW		0
48 #define OCI2C_PREHIGH		1
49 #define OCI2C_CONTROL		2
50 #define OCI2C_DATA		3
51 #define OCI2C_CMD		4 /* write only */
52 #define OCI2C_STATUS		4 /* read only, same address as OCI2C_CMD */
53 
54 #define OCI2C_CTRL_IEN		0x40
55 #define OCI2C_CTRL_EN		0x80
56 
57 #define OCI2C_CMD_START		0x91
58 #define OCI2C_CMD_STOP		0x41
59 #define OCI2C_CMD_READ		0x21
60 #define OCI2C_CMD_WRITE		0x11
61 #define OCI2C_CMD_READ_ACK	0x21
62 #define OCI2C_CMD_READ_NACK	0x29
63 #define OCI2C_CMD_IACK		0x01
64 
65 #define OCI2C_STAT_IF		0x01
66 #define OCI2C_STAT_TIP		0x02
67 #define OCI2C_STAT_ARBLOST	0x20
68 #define OCI2C_STAT_BUSY		0x40
69 #define OCI2C_STAT_NACK		0x80
70 
71 #define STATE_DONE		0
72 #define STATE_START		1
73 #define STATE_WRITE		2
74 #define STATE_READ		3
75 #define STATE_ERROR		4
76 
77 #define TYPE_OCORES		0
78 #define TYPE_GRLIB		1
79 
oc_setreg_8(struct ocores_i2c * i2c,int reg,u8 value)80 static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
81 {
82 	iowrite8(value, i2c->base + (reg << i2c->reg_shift));
83 }
84 
oc_setreg_16(struct ocores_i2c * i2c,int reg,u8 value)85 static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
86 {
87 	iowrite16(value, i2c->base + (reg << i2c->reg_shift));
88 }
89 
oc_setreg_32(struct ocores_i2c * i2c,int reg,u8 value)90 static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
91 {
92 	iowrite32(value, i2c->base + (reg << i2c->reg_shift));
93 }
94 
oc_setreg_16be(struct ocores_i2c * i2c,int reg,u8 value)95 static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value)
96 {
97 	iowrite16be(value, i2c->base + (reg << i2c->reg_shift));
98 }
99 
oc_setreg_32be(struct ocores_i2c * i2c,int reg,u8 value)100 static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value)
101 {
102 	iowrite32be(value, i2c->base + (reg << i2c->reg_shift));
103 }
104 
oc_getreg_8(struct ocores_i2c * i2c,int reg)105 static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
106 {
107 	return ioread8(i2c->base + (reg << i2c->reg_shift));
108 }
109 
oc_getreg_16(struct ocores_i2c * i2c,int reg)110 static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
111 {
112 	return ioread16(i2c->base + (reg << i2c->reg_shift));
113 }
114 
oc_getreg_32(struct ocores_i2c * i2c,int reg)115 static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
116 {
117 	return ioread32(i2c->base + (reg << i2c->reg_shift));
118 }
119 
oc_getreg_16be(struct ocores_i2c * i2c,int reg)120 static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg)
121 {
122 	return ioread16be(i2c->base + (reg << i2c->reg_shift));
123 }
124 
oc_getreg_32be(struct ocores_i2c * i2c,int reg)125 static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg)
126 {
127 	return ioread32be(i2c->base + (reg << i2c->reg_shift));
128 }
129 
oc_setreg(struct ocores_i2c * i2c,int reg,u8 value)130 static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
131 {
132 	i2c->setreg(i2c, reg, value);
133 }
134 
oc_getreg(struct ocores_i2c * i2c,int reg)135 static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
136 {
137 	return i2c->getreg(i2c, reg);
138 }
139 
ocores_process(struct ocores_i2c * i2c)140 static void ocores_process(struct ocores_i2c *i2c)
141 {
142 	struct i2c_msg *msg = i2c->msg;
143 	u8 stat = oc_getreg(i2c, OCI2C_STATUS);
144 
145 	if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
146 		/* stop has been sent */
147 		oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
148 		wake_up(&i2c->wait);
149 		return;
150 	}
151 
152 	/* error? */
153 	if (stat & OCI2C_STAT_ARBLOST) {
154 		i2c->state = STATE_ERROR;
155 		oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
156 		return;
157 	}
158 
159 	if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
160 		i2c->state =
161 			(msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
162 
163 		if (stat & OCI2C_STAT_NACK) {
164 			i2c->state = STATE_ERROR;
165 			oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
166 			return;
167 		}
168 	} else
169 		msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
170 
171 	/* end of msg? */
172 	if (i2c->pos == msg->len) {
173 		i2c->nmsgs--;
174 		i2c->msg++;
175 		i2c->pos = 0;
176 		msg = i2c->msg;
177 
178 		if (i2c->nmsgs) {	/* end? */
179 			/* send start? */
180 			if (!(msg->flags & I2C_M_NOSTART)) {
181 				u8 addr = i2c_8bit_addr_from_msg(msg);
182 
183 				i2c->state = STATE_START;
184 
185 				oc_setreg(i2c, OCI2C_DATA, addr);
186 				oc_setreg(i2c, OCI2C_CMD,  OCI2C_CMD_START);
187 				return;
188 			} else
189 				i2c->state = (msg->flags & I2C_M_RD)
190 					? STATE_READ : STATE_WRITE;
191 		} else {
192 			i2c->state = STATE_DONE;
193 			oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
194 			return;
195 		}
196 	}
197 
198 	if (i2c->state == STATE_READ) {
199 		oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
200 			  OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
201 	} else {
202 		oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
203 		oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
204 	}
205 }
206 
ocores_isr(int irq,void * dev_id)207 static irqreturn_t ocores_isr(int irq, void *dev_id)
208 {
209 	struct ocores_i2c *i2c = dev_id;
210 
211 	ocores_process(i2c);
212 
213 	return IRQ_HANDLED;
214 }
215 
ocores_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)216 static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
217 {
218 	struct ocores_i2c *i2c = i2c_get_adapdata(adap);
219 
220 	i2c->msg = msgs;
221 	i2c->pos = 0;
222 	i2c->nmsgs = num;
223 	i2c->state = STATE_START;
224 
225 	oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg));
226 	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
227 
228 	if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
229 			       (i2c->state == STATE_DONE), HZ))
230 		return (i2c->state == STATE_DONE) ? num : -EIO;
231 	else
232 		return -ETIMEDOUT;
233 }
234 
ocores_init(struct device * dev,struct ocores_i2c * i2c)235 static int ocores_init(struct device *dev, struct ocores_i2c *i2c)
236 {
237 	int prescale;
238 	int diff;
239 	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
240 
241 	/* make sure the device is disabled */
242 	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
243 
244 	prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1;
245 	prescale = clamp(prescale, 0, 0xffff);
246 
247 	diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz;
248 	if (abs(diff) > i2c->bus_clock_khz / 10) {
249 		dev_err(dev,
250 			"Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
251 			i2c->ip_clock_khz, i2c->bus_clock_khz);
252 		return -EINVAL;
253 	}
254 
255 	oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
256 	oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
257 
258 	/* Init the device */
259 	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
260 	oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN);
261 
262 	return 0;
263 }
264 
265 
ocores_func(struct i2c_adapter * adap)266 static u32 ocores_func(struct i2c_adapter *adap)
267 {
268 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
269 }
270 
271 static const struct i2c_algorithm ocores_algorithm = {
272 	.master_xfer = ocores_xfer,
273 	.functionality = ocores_func,
274 };
275 
276 static const struct i2c_adapter ocores_adapter = {
277 	.owner = THIS_MODULE,
278 	.name = "i2c-ocores",
279 	.class = I2C_CLASS_DEPRECATED,
280 	.algo = &ocores_algorithm,
281 };
282 
283 static const struct of_device_id ocores_i2c_match[] = {
284 	{
285 		.compatible = "opencores,i2c-ocores",
286 		.data = (void *)TYPE_OCORES,
287 	},
288 	{
289 		.compatible = "aeroflexgaisler,i2cmst",
290 		.data = (void *)TYPE_GRLIB,
291 	},
292 	{},
293 };
294 MODULE_DEVICE_TABLE(of, ocores_i2c_match);
295 
296 #ifdef CONFIG_OF
297 /* Read and write functions for the GRLIB port of the controller. Registers are
298  * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
299  * register. The subsequent registers has their offset decreased accordingly. */
oc_getreg_grlib(struct ocores_i2c * i2c,int reg)300 static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
301 {
302 	u32 rd;
303 	int rreg = reg;
304 	if (reg != OCI2C_PRELOW)
305 		rreg--;
306 	rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
307 	if (reg == OCI2C_PREHIGH)
308 		return (u8)(rd >> 8);
309 	else
310 		return (u8)rd;
311 }
312 
oc_setreg_grlib(struct ocores_i2c * i2c,int reg,u8 value)313 static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
314 {
315 	u32 curr, wr;
316 	int rreg = reg;
317 	if (reg != OCI2C_PRELOW)
318 		rreg--;
319 	if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
320 		curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
321 		if (reg == OCI2C_PRELOW)
322 			wr = (curr & 0xff00) | value;
323 		else
324 			wr = (((u32)value) << 8) | (curr & 0xff);
325 	} else {
326 		wr = value;
327 	}
328 	iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
329 }
330 
ocores_i2c_of_probe(struct platform_device * pdev,struct ocores_i2c * i2c)331 static int ocores_i2c_of_probe(struct platform_device *pdev,
332 				struct ocores_i2c *i2c)
333 {
334 	struct device_node *np = pdev->dev.of_node;
335 	const struct of_device_id *match;
336 	u32 val;
337 	u32 clock_frequency;
338 	bool clock_frequency_present;
339 
340 	if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
341 		/* no 'reg-shift', check for deprecated 'regstep' */
342 		if (!of_property_read_u32(np, "regstep", &val)) {
343 			if (!is_power_of_2(val)) {
344 				dev_err(&pdev->dev, "invalid regstep %d\n",
345 					val);
346 				return -EINVAL;
347 			}
348 			i2c->reg_shift = ilog2(val);
349 			dev_warn(&pdev->dev,
350 				"regstep property deprecated, use reg-shift\n");
351 		}
352 	}
353 
354 	clock_frequency_present = !of_property_read_u32(np, "clock-frequency",
355 							&clock_frequency);
356 	i2c->bus_clock_khz = 100;
357 
358 	i2c->clk = devm_clk_get(&pdev->dev, NULL);
359 
360 	if (!IS_ERR(i2c->clk)) {
361 		int ret = clk_prepare_enable(i2c->clk);
362 
363 		if (ret) {
364 			dev_err(&pdev->dev,
365 				"clk_prepare_enable failed: %d\n", ret);
366 			return ret;
367 		}
368 		i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000;
369 		if (clock_frequency_present)
370 			i2c->bus_clock_khz = clock_frequency / 1000;
371 	}
372 
373 	if (i2c->ip_clock_khz == 0) {
374 		if (of_property_read_u32(np, "opencores,ip-clock-frequency",
375 						&val)) {
376 			if (!clock_frequency_present) {
377 				dev_err(&pdev->dev,
378 					"Missing required parameter 'opencores,ip-clock-frequency'\n");
379 				clk_disable_unprepare(i2c->clk);
380 				return -ENODEV;
381 			}
382 			i2c->ip_clock_khz = clock_frequency / 1000;
383 			dev_warn(&pdev->dev,
384 				 "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n");
385 		} else {
386 			i2c->ip_clock_khz = val / 1000;
387 			if (clock_frequency_present)
388 				i2c->bus_clock_khz = clock_frequency / 1000;
389 		}
390 	}
391 
392 	of_property_read_u32(pdev->dev.of_node, "reg-io-width",
393 				&i2c->reg_io_width);
394 
395 	match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
396 	if (match && (long)match->data == TYPE_GRLIB) {
397 		dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
398 		i2c->setreg = oc_setreg_grlib;
399 		i2c->getreg = oc_getreg_grlib;
400 	}
401 
402 	return 0;
403 }
404 #else
405 #define ocores_i2c_of_probe(pdev,i2c) -ENODEV
406 #endif
407 
ocores_i2c_probe(struct platform_device * pdev)408 static int ocores_i2c_probe(struct platform_device *pdev)
409 {
410 	struct ocores_i2c *i2c;
411 	struct ocores_i2c_platform_data *pdata;
412 	struct resource *res;
413 	int irq;
414 	int ret;
415 	int i;
416 
417 	irq = platform_get_irq(pdev, 0);
418 	if (irq < 0)
419 		return irq;
420 
421 	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
422 	if (!i2c)
423 		return -ENOMEM;
424 
425 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
426 	i2c->base = devm_ioremap_resource(&pdev->dev, res);
427 	if (IS_ERR(i2c->base))
428 		return PTR_ERR(i2c->base);
429 
430 	pdata = dev_get_platdata(&pdev->dev);
431 	if (pdata) {
432 		i2c->reg_shift = pdata->reg_shift;
433 		i2c->reg_io_width = pdata->reg_io_width;
434 		i2c->ip_clock_khz = pdata->clock_khz;
435 		i2c->bus_clock_khz = 100;
436 	} else {
437 		ret = ocores_i2c_of_probe(pdev, i2c);
438 		if (ret)
439 			return ret;
440 	}
441 
442 	if (i2c->reg_io_width == 0)
443 		i2c->reg_io_width = 1; /* Set to default value */
444 
445 	if (!i2c->setreg || !i2c->getreg) {
446 		bool be = pdata ? pdata->big_endian :
447 			of_device_is_big_endian(pdev->dev.of_node);
448 
449 		switch (i2c->reg_io_width) {
450 		case 1:
451 			i2c->setreg = oc_setreg_8;
452 			i2c->getreg = oc_getreg_8;
453 			break;
454 
455 		case 2:
456 			i2c->setreg = be ? oc_setreg_16be : oc_setreg_16;
457 			i2c->getreg = be ? oc_getreg_16be : oc_getreg_16;
458 			break;
459 
460 		case 4:
461 			i2c->setreg = be ? oc_setreg_32be : oc_setreg_32;
462 			i2c->getreg = be ? oc_getreg_32be : oc_getreg_32;
463 			break;
464 
465 		default:
466 			dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
467 				i2c->reg_io_width);
468 			ret = -EINVAL;
469 			goto err_clk;
470 		}
471 	}
472 
473 	ret = ocores_init(&pdev->dev, i2c);
474 	if (ret)
475 		goto err_clk;
476 
477 	init_waitqueue_head(&i2c->wait);
478 	ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
479 			       pdev->name, i2c);
480 	if (ret) {
481 		dev_err(&pdev->dev, "Cannot claim IRQ\n");
482 		goto err_clk;
483 	}
484 
485 	/* hook up driver to tree */
486 	platform_set_drvdata(pdev, i2c);
487 	i2c->adap = ocores_adapter;
488 	i2c_set_adapdata(&i2c->adap, i2c);
489 	i2c->adap.dev.parent = &pdev->dev;
490 	i2c->adap.dev.of_node = pdev->dev.of_node;
491 
492 	/* add i2c adapter to i2c tree */
493 	ret = i2c_add_adapter(&i2c->adap);
494 	if (ret)
495 		goto err_clk;
496 
497 	/* add in known devices to the bus */
498 	if (pdata) {
499 		for (i = 0; i < pdata->num_devices; i++)
500 			i2c_new_device(&i2c->adap, pdata->devices + i);
501 	}
502 
503 	return 0;
504 
505 err_clk:
506 	clk_disable_unprepare(i2c->clk);
507 	return ret;
508 }
509 
ocores_i2c_remove(struct platform_device * pdev)510 static int ocores_i2c_remove(struct platform_device *pdev)
511 {
512 	struct ocores_i2c *i2c = platform_get_drvdata(pdev);
513 
514 	/* disable i2c logic */
515 	oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
516 		  & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
517 
518 	/* remove adapter & data */
519 	i2c_del_adapter(&i2c->adap);
520 
521 	if (!IS_ERR(i2c->clk))
522 		clk_disable_unprepare(i2c->clk);
523 
524 	return 0;
525 }
526 
527 #ifdef CONFIG_PM_SLEEP
ocores_i2c_suspend(struct device * dev)528 static int ocores_i2c_suspend(struct device *dev)
529 {
530 	struct ocores_i2c *i2c = dev_get_drvdata(dev);
531 	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
532 
533 	/* make sure the device is disabled */
534 	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
535 
536 	if (!IS_ERR(i2c->clk))
537 		clk_disable_unprepare(i2c->clk);
538 	return 0;
539 }
540 
ocores_i2c_resume(struct device * dev)541 static int ocores_i2c_resume(struct device *dev)
542 {
543 	struct ocores_i2c *i2c = dev_get_drvdata(dev);
544 
545 	if (!IS_ERR(i2c->clk)) {
546 		unsigned long rate;
547 		int ret = clk_prepare_enable(i2c->clk);
548 
549 		if (ret) {
550 			dev_err(dev,
551 				"clk_prepare_enable failed: %d\n", ret);
552 			return ret;
553 		}
554 		rate = clk_get_rate(i2c->clk) / 1000;
555 		if (rate)
556 			i2c->ip_clock_khz = rate;
557 	}
558 	return ocores_init(dev, i2c);
559 }
560 
561 static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
562 #define OCORES_I2C_PM	(&ocores_i2c_pm)
563 #else
564 #define OCORES_I2C_PM	NULL
565 #endif
566 
567 static struct platform_driver ocores_i2c_driver = {
568 	.probe   = ocores_i2c_probe,
569 	.remove  = ocores_i2c_remove,
570 	.driver  = {
571 		.name = "ocores-i2c",
572 		.of_match_table = ocores_i2c_match,
573 		.pm = OCORES_I2C_PM,
574 	},
575 };
576 
577 module_platform_driver(ocores_i2c_driver);
578 
579 MODULE_AUTHOR("Peter Korsgaard <peter@korsgaard.com>");
580 MODULE_DESCRIPTION("OpenCores I2C bus driver");
581 MODULE_LICENSE("GPL");
582 MODULE_ALIAS("platform:ocores-i2c");
583