1 /*
2 * Marvell Armada 370 and Armada XP SoC IRQ handling
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/interrupt.h>
21 #include <linux/irqchip.h>
22 #include <linux/irqchip/chained_irq.h>
23 #include <linux/cpu.h>
24 #include <linux/io.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_pci.h>
28 #include <linux/irqdomain.h>
29 #include <linux/slab.h>
30 #include <linux/syscore_ops.h>
31 #include <linux/msi.h>
32 #include <asm/mach/arch.h>
33 #include <asm/exception.h>
34 #include <asm/smp_plat.h>
35 #include <asm/mach/irq.h>
36
37 /*
38 * Overall diagram of the Armada XP interrupt controller:
39 *
40 * To CPU 0 To CPU 1
41 *
42 * /\ /\
43 * || ||
44 * +---------------+ +---------------+
45 * | | | |
46 * | per-CPU | | per-CPU |
47 * | mask/unmask | | mask/unmask |
48 * | CPU0 | | CPU1 |
49 * | | | |
50 * +---------------+ +---------------+
51 * /\ /\
52 * || ||
53 * \\_______________________//
54 * ||
55 * +-------------------+
56 * | |
57 * | Global interrupt |
58 * | mask/unmask |
59 * | |
60 * +-------------------+
61 * /\
62 * ||
63 * interrupt from
64 * device
65 *
66 * The "global interrupt mask/unmask" is modified using the
67 * ARMADA_370_XP_INT_SET_ENABLE_OFFS and
68 * ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS registers, which are relative
69 * to "main_int_base".
70 *
71 * The "per-CPU mask/unmask" is modified using the
72 * ARMADA_370_XP_INT_SET_MASK_OFFS and
73 * ARMADA_370_XP_INT_CLEAR_MASK_OFFS registers, which are relative to
74 * "per_cpu_int_base". This base address points to a special address,
75 * which automatically accesses the registers of the current CPU.
76 *
77 * The per-CPU mask/unmask can also be adjusted using the global
78 * per-interrupt ARMADA_370_XP_INT_SOURCE_CTL register, which we use
79 * to configure interrupt affinity.
80 *
81 * Due to this model, all interrupts need to be mask/unmasked at two
82 * different levels: at the global level and at the per-CPU level.
83 *
84 * This driver takes the following approach to deal with this:
85 *
86 * - For global interrupts:
87 *
88 * At ->map() time, a global interrupt is unmasked at the per-CPU
89 * mask/unmask level. It is therefore unmasked at this level for
90 * the current CPU, running the ->map() code. This allows to have
91 * the interrupt unmasked at this level in non-SMP
92 * configurations. In SMP configurations, the ->set_affinity()
93 * callback is called, which using the
94 * ARMADA_370_XP_INT_SOURCE_CTL() readjusts the per-CPU mask/unmask
95 * for the interrupt.
96 *
97 * The ->mask() and ->unmask() operations only mask/unmask the
98 * interrupt at the "global" level.
99 *
100 * So, a global interrupt is enabled at the per-CPU level as soon
101 * as it is mapped. At run time, the masking/unmasking takes place
102 * at the global level.
103 *
104 * - For per-CPU interrupts
105 *
106 * At ->map() time, a per-CPU interrupt is unmasked at the global
107 * mask/unmask level.
108 *
109 * The ->mask() and ->unmask() operations mask/unmask the interrupt
110 * at the per-CPU level.
111 *
112 * So, a per-CPU interrupt is enabled at the global level as soon
113 * as it is mapped. At run time, the masking/unmasking takes place
114 * at the per-CPU level.
115 */
116
117 /* Registers relative to main_int_base */
118 #define ARMADA_370_XP_INT_CONTROL (0x00)
119 #define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x04)
120 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
121 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
122 #define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
123 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
124 #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid)
125
126 /* Registers relative to per_cpu_int_base */
127 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x08)
128 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0x0c)
129 #define ARMADA_375_PPI_CAUSE (0x10)
130 #define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
131 #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
132 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
133 #define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54)
134 #define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu)
135
136 #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
137
138 #define IPI_DOORBELL_START (0)
139 #define IPI_DOORBELL_END (8)
140 #define IPI_DOORBELL_MASK 0xFF
141 #define PCI_MSI_DOORBELL_START (16)
142 #define PCI_MSI_DOORBELL_NR (16)
143 #define PCI_MSI_DOORBELL_END (32)
144 #define PCI_MSI_DOORBELL_MASK 0xFFFF0000
145
146 static void __iomem *per_cpu_int_base;
147 static void __iomem *main_int_base;
148 static struct irq_domain *armada_370_xp_mpic_domain;
149 static u32 doorbell_mask_reg;
150 static int parent_irq;
151 #ifdef CONFIG_PCI_MSI
152 static struct irq_domain *armada_370_xp_msi_domain;
153 static struct irq_domain *armada_370_xp_msi_inner_domain;
154 static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
155 static DEFINE_MUTEX(msi_used_lock);
156 static phys_addr_t msi_doorbell_addr;
157 #endif
158
is_percpu_irq(irq_hw_number_t irq)159 static inline bool is_percpu_irq(irq_hw_number_t irq)
160 {
161 if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS)
162 return true;
163
164 return false;
165 }
166
167 /*
168 * In SMP mode:
169 * For shared global interrupts, mask/unmask global enable bit
170 * For CPU interrupts, mask/unmask the calling CPU's bit
171 */
armada_370_xp_irq_mask(struct irq_data * d)172 static void armada_370_xp_irq_mask(struct irq_data *d)
173 {
174 irq_hw_number_t hwirq = irqd_to_hwirq(d);
175
176 if (!is_percpu_irq(hwirq))
177 writel(hwirq, main_int_base +
178 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
179 else
180 writel(hwirq, per_cpu_int_base +
181 ARMADA_370_XP_INT_SET_MASK_OFFS);
182 }
183
armada_370_xp_irq_unmask(struct irq_data * d)184 static void armada_370_xp_irq_unmask(struct irq_data *d)
185 {
186 irq_hw_number_t hwirq = irqd_to_hwirq(d);
187
188 if (!is_percpu_irq(hwirq))
189 writel(hwirq, main_int_base +
190 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
191 else
192 writel(hwirq, per_cpu_int_base +
193 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
194 }
195
196 #ifdef CONFIG_PCI_MSI
197
198 static struct irq_chip armada_370_xp_msi_irq_chip = {
199 .name = "MPIC MSI",
200 .irq_mask = pci_msi_mask_irq,
201 .irq_unmask = pci_msi_unmask_irq,
202 };
203
204 static struct msi_domain_info armada_370_xp_msi_domain_info = {
205 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
206 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
207 .chip = &armada_370_xp_msi_irq_chip,
208 };
209
armada_370_xp_compose_msi_msg(struct irq_data * data,struct msi_msg * msg)210 static void armada_370_xp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
211 {
212 msg->address_lo = lower_32_bits(msi_doorbell_addr);
213 msg->address_hi = upper_32_bits(msi_doorbell_addr);
214 msg->data = 0xf00 | (data->hwirq + PCI_MSI_DOORBELL_START);
215 }
216
armada_370_xp_msi_set_affinity(struct irq_data * irq_data,const struct cpumask * mask,bool force)217 static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data,
218 const struct cpumask *mask, bool force)
219 {
220 return -EINVAL;
221 }
222
223 static struct irq_chip armada_370_xp_msi_bottom_irq_chip = {
224 .name = "MPIC MSI",
225 .irq_compose_msi_msg = armada_370_xp_compose_msi_msg,
226 .irq_set_affinity = armada_370_xp_msi_set_affinity,
227 };
228
armada_370_xp_msi_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * args)229 static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq,
230 unsigned int nr_irqs, void *args)
231 {
232 int hwirq, i;
233
234 mutex_lock(&msi_used_lock);
235 hwirq = bitmap_find_free_region(msi_used, PCI_MSI_DOORBELL_NR,
236 order_base_2(nr_irqs));
237 mutex_unlock(&msi_used_lock);
238
239 if (hwirq < 0)
240 return -ENOSPC;
241
242 for (i = 0; i < nr_irqs; i++) {
243 irq_domain_set_info(domain, virq + i, hwirq + i,
244 &armada_370_xp_msi_bottom_irq_chip,
245 domain->host_data, handle_simple_irq,
246 NULL, NULL);
247 }
248
249 return 0;
250 }
251
armada_370_xp_msi_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)252 static void armada_370_xp_msi_free(struct irq_domain *domain,
253 unsigned int virq, unsigned int nr_irqs)
254 {
255 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
256
257 mutex_lock(&msi_used_lock);
258 bitmap_release_region(msi_used, d->hwirq, order_base_2(nr_irqs));
259 mutex_unlock(&msi_used_lock);
260 }
261
262 static const struct irq_domain_ops armada_370_xp_msi_domain_ops = {
263 .alloc = armada_370_xp_msi_alloc,
264 .free = armada_370_xp_msi_free,
265 };
266
armada_370_xp_msi_init(struct device_node * node,phys_addr_t main_int_phys_base)267 static int armada_370_xp_msi_init(struct device_node *node,
268 phys_addr_t main_int_phys_base)
269 {
270 u32 reg;
271
272 msi_doorbell_addr = main_int_phys_base +
273 ARMADA_370_XP_SW_TRIG_INT_OFFS;
274
275 armada_370_xp_msi_inner_domain =
276 irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
277 &armada_370_xp_msi_domain_ops, NULL);
278 if (!armada_370_xp_msi_inner_domain)
279 return -ENOMEM;
280
281 armada_370_xp_msi_domain =
282 pci_msi_create_irq_domain(of_node_to_fwnode(node),
283 &armada_370_xp_msi_domain_info,
284 armada_370_xp_msi_inner_domain);
285 if (!armada_370_xp_msi_domain) {
286 irq_domain_remove(armada_370_xp_msi_inner_domain);
287 return -ENOMEM;
288 }
289
290 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
291 | PCI_MSI_DOORBELL_MASK;
292
293 writel(reg, per_cpu_int_base +
294 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
295
296 /* Unmask IPI interrupt */
297 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
298
299 return 0;
300 }
301 #else
armada_370_xp_msi_init(struct device_node * node,phys_addr_t main_int_phys_base)302 static inline int armada_370_xp_msi_init(struct device_node *node,
303 phys_addr_t main_int_phys_base)
304 {
305 return 0;
306 }
307 #endif
308
309 #ifdef CONFIG_SMP
310 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
311
armada_xp_set_affinity(struct irq_data * d,const struct cpumask * mask_val,bool force)312 static int armada_xp_set_affinity(struct irq_data *d,
313 const struct cpumask *mask_val, bool force)
314 {
315 irq_hw_number_t hwirq = irqd_to_hwirq(d);
316 unsigned long reg, mask;
317 int cpu;
318
319 /* Select a single core from the affinity mask which is online */
320 cpu = cpumask_any_and(mask_val, cpu_online_mask);
321 mask = 1UL << cpu_logical_map(cpu);
322
323 raw_spin_lock(&irq_controller_lock);
324 reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
325 reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
326 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
327 raw_spin_unlock(&irq_controller_lock);
328
329 irq_data_update_effective_affinity(d, cpumask_of(cpu));
330
331 return IRQ_SET_MASK_OK;
332 }
333 #endif
334
335 static struct irq_chip armada_370_xp_irq_chip = {
336 .name = "MPIC",
337 .irq_mask = armada_370_xp_irq_mask,
338 .irq_mask_ack = armada_370_xp_irq_mask,
339 .irq_unmask = armada_370_xp_irq_unmask,
340 #ifdef CONFIG_SMP
341 .irq_set_affinity = armada_xp_set_affinity,
342 #endif
343 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
344 };
345
armada_370_xp_mpic_irq_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)346 static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
347 unsigned int virq, irq_hw_number_t hw)
348 {
349 armada_370_xp_irq_mask(irq_get_irq_data(virq));
350 if (!is_percpu_irq(hw))
351 writel(hw, per_cpu_int_base +
352 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
353 else
354 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
355 irq_set_status_flags(virq, IRQ_LEVEL);
356
357 if (is_percpu_irq(hw)) {
358 irq_set_percpu_devid(virq);
359 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
360 handle_percpu_devid_irq);
361 } else {
362 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
363 handle_level_irq);
364 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
365 }
366 irq_set_probe(virq);
367
368 return 0;
369 }
370
armada_xp_mpic_smp_cpu_init(void)371 static void armada_xp_mpic_smp_cpu_init(void)
372 {
373 u32 control;
374 int nr_irqs, i;
375
376 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
377 nr_irqs = (control >> 2) & 0x3ff;
378
379 for (i = 0; i < nr_irqs; i++)
380 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
381
382 /* Clear pending IPIs */
383 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
384
385 /* Enable first 8 IPIs */
386 writel(IPI_DOORBELL_MASK, per_cpu_int_base +
387 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
388
389 /* Unmask IPI interrupt */
390 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
391 }
392
armada_xp_mpic_perf_init(void)393 static void armada_xp_mpic_perf_init(void)
394 {
395 unsigned long cpuid;
396
397 /*
398 * This Performance Counter Overflow interrupt is specific for
399 * Armada 370 and XP. It is not available on Armada 375, 38x and 39x.
400 */
401 if (!of_machine_is_compatible("marvell,armada-370-xp"))
402 return;
403
404 cpuid = cpu_logical_map(smp_processor_id());
405
406 /* Enable Performance Counter Overflow interrupts */
407 writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
408 per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
409 }
410
411 #ifdef CONFIG_SMP
armada_mpic_send_doorbell(const struct cpumask * mask,unsigned int irq)412 static void armada_mpic_send_doorbell(const struct cpumask *mask,
413 unsigned int irq)
414 {
415 int cpu;
416 unsigned long map = 0;
417
418 /* Convert our logical CPU mask into a physical one. */
419 for_each_cpu(cpu, mask)
420 map |= 1 << cpu_logical_map(cpu);
421
422 /*
423 * Ensure that stores to Normal memory are visible to the
424 * other CPUs before issuing the IPI.
425 */
426 dsb();
427
428 /* submit softirq */
429 writel((map << 8) | irq, main_int_base +
430 ARMADA_370_XP_SW_TRIG_INT_OFFS);
431 }
432
armada_xp_mpic_reenable_percpu(void)433 static void armada_xp_mpic_reenable_percpu(void)
434 {
435 unsigned int irq;
436
437 /* Re-enable per-CPU interrupts that were enabled before suspend */
438 for (irq = 0; irq < ARMADA_370_XP_MAX_PER_CPU_IRQS; irq++) {
439 struct irq_data *data;
440 int virq;
441
442 virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
443 if (virq == 0)
444 continue;
445
446 data = irq_get_irq_data(virq);
447
448 if (!irq_percpu_is_enabled(virq))
449 continue;
450
451 armada_370_xp_irq_unmask(data);
452 }
453 }
454
armada_xp_mpic_starting_cpu(unsigned int cpu)455 static int armada_xp_mpic_starting_cpu(unsigned int cpu)
456 {
457 armada_xp_mpic_perf_init();
458 armada_xp_mpic_smp_cpu_init();
459 armada_xp_mpic_reenable_percpu();
460 return 0;
461 }
462
mpic_cascaded_starting_cpu(unsigned int cpu)463 static int mpic_cascaded_starting_cpu(unsigned int cpu)
464 {
465 armada_xp_mpic_perf_init();
466 armada_xp_mpic_reenable_percpu();
467 enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
468 return 0;
469 }
470 #endif
471
472 static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
473 .map = armada_370_xp_mpic_irq_map,
474 .xlate = irq_domain_xlate_onecell,
475 };
476
477 #ifdef CONFIG_PCI_MSI
armada_370_xp_handle_msi_irq(struct pt_regs * regs,bool is_chained)478 static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
479 {
480 u32 msimask, msinr;
481
482 msimask = readl_relaxed(per_cpu_int_base +
483 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
484 & PCI_MSI_DOORBELL_MASK;
485
486 writel(~msimask, per_cpu_int_base +
487 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
488
489 for (msinr = PCI_MSI_DOORBELL_START;
490 msinr < PCI_MSI_DOORBELL_END; msinr++) {
491 int irq;
492
493 if (!(msimask & BIT(msinr)))
494 continue;
495
496 if (is_chained) {
497 irq = irq_find_mapping(armada_370_xp_msi_inner_domain,
498 msinr - PCI_MSI_DOORBELL_START);
499 generic_handle_irq(irq);
500 } else {
501 irq = msinr - PCI_MSI_DOORBELL_START;
502 handle_domain_irq(armada_370_xp_msi_inner_domain,
503 irq, regs);
504 }
505 }
506 }
507 #else
armada_370_xp_handle_msi_irq(struct pt_regs * r,bool b)508 static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
509 #endif
510
armada_370_xp_mpic_handle_cascade_irq(struct irq_desc * desc)511 static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
512 {
513 struct irq_chip *chip = irq_desc_get_chip(desc);
514 unsigned long irqmap, irqn, irqsrc, cpuid;
515 unsigned int cascade_irq;
516
517 chained_irq_enter(chip, desc);
518
519 irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
520 cpuid = cpu_logical_map(smp_processor_id());
521
522 for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
523 irqsrc = readl_relaxed(main_int_base +
524 ARMADA_370_XP_INT_SOURCE_CTL(irqn));
525
526 /* Check if the interrupt is not masked on current CPU.
527 * Test IRQ (0-1) and FIQ (8-9) mask bits.
528 */
529 if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
530 continue;
531
532 if (irqn == 1) {
533 armada_370_xp_handle_msi_irq(NULL, true);
534 continue;
535 }
536
537 cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
538 generic_handle_irq(cascade_irq);
539 }
540
541 chained_irq_exit(chip, desc);
542 }
543
544 static void __exception_irq_entry
armada_370_xp_handle_irq(struct pt_regs * regs)545 armada_370_xp_handle_irq(struct pt_regs *regs)
546 {
547 u32 irqstat, irqnr;
548
549 do {
550 irqstat = readl_relaxed(per_cpu_int_base +
551 ARMADA_370_XP_CPU_INTACK_OFFS);
552 irqnr = irqstat & 0x3FF;
553
554 if (irqnr > 1022)
555 break;
556
557 if (irqnr > 1) {
558 handle_domain_irq(armada_370_xp_mpic_domain,
559 irqnr, regs);
560 continue;
561 }
562
563 /* MSI handling */
564 if (irqnr == 1)
565 armada_370_xp_handle_msi_irq(regs, false);
566
567 #ifdef CONFIG_SMP
568 /* IPI Handling */
569 if (irqnr == 0) {
570 u32 ipimask, ipinr;
571
572 ipimask = readl_relaxed(per_cpu_int_base +
573 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
574 & IPI_DOORBELL_MASK;
575
576 writel(~ipimask, per_cpu_int_base +
577 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
578
579 /* Handle all pending doorbells */
580 for (ipinr = IPI_DOORBELL_START;
581 ipinr < IPI_DOORBELL_END; ipinr++) {
582 if (ipimask & (0x1 << ipinr))
583 handle_IPI(ipinr, regs);
584 }
585 continue;
586 }
587 #endif
588
589 } while (1);
590 }
591
armada_370_xp_mpic_suspend(void)592 static int armada_370_xp_mpic_suspend(void)
593 {
594 doorbell_mask_reg = readl(per_cpu_int_base +
595 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
596 return 0;
597 }
598
armada_370_xp_mpic_resume(void)599 static void armada_370_xp_mpic_resume(void)
600 {
601 int nirqs;
602 irq_hw_number_t irq;
603
604 /* Re-enable interrupts */
605 nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
606 for (irq = 0; irq < nirqs; irq++) {
607 struct irq_data *data;
608 int virq;
609
610 virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
611 if (virq == 0)
612 continue;
613
614 data = irq_get_irq_data(virq);
615
616 if (!is_percpu_irq(irq)) {
617 /* Non per-CPU interrupts */
618 writel(irq, per_cpu_int_base +
619 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
620 if (!irqd_irq_disabled(data))
621 armada_370_xp_irq_unmask(data);
622 } else {
623 /* Per-CPU interrupts */
624 writel(irq, main_int_base +
625 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
626
627 /*
628 * Re-enable on the current CPU,
629 * armada_xp_mpic_reenable_percpu() will take
630 * care of secondary CPUs when they come up.
631 */
632 if (irq_percpu_is_enabled(virq))
633 armada_370_xp_irq_unmask(data);
634 }
635 }
636
637 /* Reconfigure doorbells for IPIs and MSIs */
638 writel(doorbell_mask_reg,
639 per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
640 if (doorbell_mask_reg & IPI_DOORBELL_MASK)
641 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
642 if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
643 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
644 }
645
646 static struct syscore_ops armada_370_xp_mpic_syscore_ops = {
647 .suspend = armada_370_xp_mpic_suspend,
648 .resume = armada_370_xp_mpic_resume,
649 };
650
armada_370_xp_mpic_of_init(struct device_node * node,struct device_node * parent)651 static int __init armada_370_xp_mpic_of_init(struct device_node *node,
652 struct device_node *parent)
653 {
654 struct resource main_int_res, per_cpu_int_res;
655 int nr_irqs, i;
656 u32 control;
657
658 BUG_ON(of_address_to_resource(node, 0, &main_int_res));
659 BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
660
661 BUG_ON(!request_mem_region(main_int_res.start,
662 resource_size(&main_int_res),
663 node->full_name));
664 BUG_ON(!request_mem_region(per_cpu_int_res.start,
665 resource_size(&per_cpu_int_res),
666 node->full_name));
667
668 main_int_base = ioremap(main_int_res.start,
669 resource_size(&main_int_res));
670 BUG_ON(!main_int_base);
671
672 per_cpu_int_base = ioremap(per_cpu_int_res.start,
673 resource_size(&per_cpu_int_res));
674 BUG_ON(!per_cpu_int_base);
675
676 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
677 nr_irqs = (control >> 2) & 0x3ff;
678
679 for (i = 0; i < nr_irqs; i++)
680 writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
681
682 armada_370_xp_mpic_domain =
683 irq_domain_add_linear(node, nr_irqs,
684 &armada_370_xp_mpic_irq_ops, NULL);
685 BUG_ON(!armada_370_xp_mpic_domain);
686 irq_domain_update_bus_token(armada_370_xp_mpic_domain, DOMAIN_BUS_WIRED);
687
688 /* Setup for the boot CPU */
689 armada_xp_mpic_perf_init();
690 armada_xp_mpic_smp_cpu_init();
691
692 armada_370_xp_msi_init(node, main_int_res.start);
693
694 parent_irq = irq_of_parse_and_map(node, 0);
695 if (parent_irq <= 0) {
696 irq_set_default_host(armada_370_xp_mpic_domain);
697 set_handle_irq(armada_370_xp_handle_irq);
698 #ifdef CONFIG_SMP
699 set_smp_cross_call(armada_mpic_send_doorbell);
700 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
701 "irqchip/armada/ipi:starting",
702 armada_xp_mpic_starting_cpu, NULL);
703 #endif
704 } else {
705 #ifdef CONFIG_SMP
706 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
707 "irqchip/armada/cascade:starting",
708 mpic_cascaded_starting_cpu, NULL);
709 #endif
710 irq_set_chained_handler(parent_irq,
711 armada_370_xp_mpic_handle_cascade_irq);
712 }
713
714 register_syscore_ops(&armada_370_xp_mpic_syscore_ops);
715
716 return 0;
717 }
718
719 IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);
720