1 /*
2 * Broadcom BCM7038 style Level 1 interrupt controller driver
3 *
4 * Copyright (C) 2014 Broadcom Corporation
5 * Author: Kevin Cernekee
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14 #include <linux/bitops.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/ioport.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/module.h>
23 #include <linux/of.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_address.h>
26 #include <linux/of_platform.h>
27 #include <linux/platform_device.h>
28 #include <linux/slab.h>
29 #include <linux/smp.h>
30 #include <linux/types.h>
31 #include <linux/irqchip.h>
32 #include <linux/irqchip/chained_irq.h>
33
34 #define IRQS_PER_WORD 32
35 #define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 4)
36 #define MAX_WORDS 8
37
38 struct bcm7038_l1_cpu;
39
40 struct bcm7038_l1_chip {
41 raw_spinlock_t lock;
42 unsigned int n_words;
43 struct irq_domain *domain;
44 struct bcm7038_l1_cpu *cpus[NR_CPUS];
45 u8 affinity[MAX_WORDS * IRQS_PER_WORD];
46 };
47
48 struct bcm7038_l1_cpu {
49 void __iomem *map_base;
50 u32 mask_cache[0];
51 };
52
53 /*
54 * STATUS/MASK_STATUS/MASK_SET/MASK_CLEAR are packed one right after another:
55 *
56 * 7038:
57 * 0x1000_1400: W0_STATUS
58 * 0x1000_1404: W1_STATUS
59 * 0x1000_1408: W0_MASK_STATUS
60 * 0x1000_140c: W1_MASK_STATUS
61 * 0x1000_1410: W0_MASK_SET
62 * 0x1000_1414: W1_MASK_SET
63 * 0x1000_1418: W0_MASK_CLEAR
64 * 0x1000_141c: W1_MASK_CLEAR
65 *
66 * 7445:
67 * 0xf03e_1500: W0_STATUS
68 * 0xf03e_1504: W1_STATUS
69 * 0xf03e_1508: W2_STATUS
70 * 0xf03e_150c: W3_STATUS
71 * 0xf03e_1510: W4_STATUS
72 * 0xf03e_1514: W0_MASK_STATUS
73 * 0xf03e_1518: W1_MASK_STATUS
74 * [...]
75 */
76
reg_status(struct bcm7038_l1_chip * intc,unsigned int word)77 static inline unsigned int reg_status(struct bcm7038_l1_chip *intc,
78 unsigned int word)
79 {
80 return (0 * intc->n_words + word) * sizeof(u32);
81 }
82
reg_mask_status(struct bcm7038_l1_chip * intc,unsigned int word)83 static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc,
84 unsigned int word)
85 {
86 return (1 * intc->n_words + word) * sizeof(u32);
87 }
88
reg_mask_set(struct bcm7038_l1_chip * intc,unsigned int word)89 static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc,
90 unsigned int word)
91 {
92 return (2 * intc->n_words + word) * sizeof(u32);
93 }
94
reg_mask_clr(struct bcm7038_l1_chip * intc,unsigned int word)95 static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc,
96 unsigned int word)
97 {
98 return (3 * intc->n_words + word) * sizeof(u32);
99 }
100
l1_readl(void __iomem * reg)101 static inline u32 l1_readl(void __iomem *reg)
102 {
103 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
104 return ioread32be(reg);
105 else
106 return readl(reg);
107 }
108
l1_writel(u32 val,void __iomem * reg)109 static inline void l1_writel(u32 val, void __iomem *reg)
110 {
111 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
112 iowrite32be(val, reg);
113 else
114 writel(val, reg);
115 }
116
bcm7038_l1_irq_handle(struct irq_desc * desc)117 static void bcm7038_l1_irq_handle(struct irq_desc *desc)
118 {
119 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc);
120 struct bcm7038_l1_cpu *cpu;
121 struct irq_chip *chip = irq_desc_get_chip(desc);
122 unsigned int idx;
123
124 #ifdef CONFIG_SMP
125 cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
126 #else
127 cpu = intc->cpus[0];
128 #endif
129
130 chained_irq_enter(chip, desc);
131
132 for (idx = 0; idx < intc->n_words; idx++) {
133 int base = idx * IRQS_PER_WORD;
134 unsigned long pending, flags;
135 int hwirq;
136
137 raw_spin_lock_irqsave(&intc->lock, flags);
138 pending = l1_readl(cpu->map_base + reg_status(intc, idx)) &
139 ~cpu->mask_cache[idx];
140 raw_spin_unlock_irqrestore(&intc->lock, flags);
141
142 for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
143 generic_handle_irq(irq_find_mapping(intc->domain,
144 base + hwirq));
145 }
146 }
147
148 chained_irq_exit(chip, desc);
149 }
150
__bcm7038_l1_unmask(struct irq_data * d,unsigned int cpu_idx)151 static void __bcm7038_l1_unmask(struct irq_data *d, unsigned int cpu_idx)
152 {
153 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
154 u32 word = d->hwirq / IRQS_PER_WORD;
155 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
156
157 intc->cpus[cpu_idx]->mask_cache[word] &= ~mask;
158 l1_writel(mask, intc->cpus[cpu_idx]->map_base +
159 reg_mask_clr(intc, word));
160 }
161
__bcm7038_l1_mask(struct irq_data * d,unsigned int cpu_idx)162 static void __bcm7038_l1_mask(struct irq_data *d, unsigned int cpu_idx)
163 {
164 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
165 u32 word = d->hwirq / IRQS_PER_WORD;
166 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
167
168 intc->cpus[cpu_idx]->mask_cache[word] |= mask;
169 l1_writel(mask, intc->cpus[cpu_idx]->map_base +
170 reg_mask_set(intc, word));
171 }
172
bcm7038_l1_unmask(struct irq_data * d)173 static void bcm7038_l1_unmask(struct irq_data *d)
174 {
175 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
176 unsigned long flags;
177
178 raw_spin_lock_irqsave(&intc->lock, flags);
179 __bcm7038_l1_unmask(d, intc->affinity[d->hwirq]);
180 raw_spin_unlock_irqrestore(&intc->lock, flags);
181 }
182
bcm7038_l1_mask(struct irq_data * d)183 static void bcm7038_l1_mask(struct irq_data *d)
184 {
185 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
186 unsigned long flags;
187
188 raw_spin_lock_irqsave(&intc->lock, flags);
189 __bcm7038_l1_mask(d, intc->affinity[d->hwirq]);
190 raw_spin_unlock_irqrestore(&intc->lock, flags);
191 }
192
bcm7038_l1_set_affinity(struct irq_data * d,const struct cpumask * dest,bool force)193 static int bcm7038_l1_set_affinity(struct irq_data *d,
194 const struct cpumask *dest,
195 bool force)
196 {
197 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
198 unsigned long flags;
199 irq_hw_number_t hw = d->hwirq;
200 u32 word = hw / IRQS_PER_WORD;
201 u32 mask = BIT(hw % IRQS_PER_WORD);
202 unsigned int first_cpu = cpumask_any_and(dest, cpu_online_mask);
203 bool was_disabled;
204
205 raw_spin_lock_irqsave(&intc->lock, flags);
206
207 was_disabled = !!(intc->cpus[intc->affinity[hw]]->mask_cache[word] &
208 mask);
209 __bcm7038_l1_mask(d, intc->affinity[hw]);
210 intc->affinity[hw] = first_cpu;
211 if (!was_disabled)
212 __bcm7038_l1_unmask(d, first_cpu);
213
214 raw_spin_unlock_irqrestore(&intc->lock, flags);
215 irq_data_update_effective_affinity(d, cpumask_of(first_cpu));
216
217 return 0;
218 }
219
220 #ifdef CONFIG_SMP
bcm7038_l1_cpu_offline(struct irq_data * d)221 static void bcm7038_l1_cpu_offline(struct irq_data *d)
222 {
223 struct cpumask *mask = irq_data_get_affinity_mask(d);
224 int cpu = smp_processor_id();
225 cpumask_t new_affinity;
226
227 /* This CPU was not on the affinity mask */
228 if (!cpumask_test_cpu(cpu, mask))
229 return;
230
231 if (cpumask_weight(mask) > 1) {
232 /*
233 * Multiple CPU affinity, remove this CPU from the affinity
234 * mask
235 */
236 cpumask_copy(&new_affinity, mask);
237 cpumask_clear_cpu(cpu, &new_affinity);
238 } else {
239 /* Only CPU, put on the lowest online CPU */
240 cpumask_clear(&new_affinity);
241 cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
242 }
243 irq_set_affinity_locked(d, &new_affinity, false);
244 }
245 #endif
246
bcm7038_l1_init_one(struct device_node * dn,unsigned int idx,struct bcm7038_l1_chip * intc)247 static int __init bcm7038_l1_init_one(struct device_node *dn,
248 unsigned int idx,
249 struct bcm7038_l1_chip *intc)
250 {
251 struct resource res;
252 resource_size_t sz;
253 struct bcm7038_l1_cpu *cpu;
254 unsigned int i, n_words, parent_irq;
255
256 if (of_address_to_resource(dn, idx, &res))
257 return -EINVAL;
258 sz = resource_size(&res);
259 n_words = sz / REG_BYTES_PER_IRQ_WORD;
260
261 if (n_words > MAX_WORDS)
262 return -EINVAL;
263 else if (!intc->n_words)
264 intc->n_words = n_words;
265 else if (intc->n_words != n_words)
266 return -EINVAL;
267
268 cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
269 GFP_KERNEL);
270 if (!cpu)
271 return -ENOMEM;
272
273 cpu->map_base = ioremap(res.start, sz);
274 if (!cpu->map_base)
275 return -ENOMEM;
276
277 for (i = 0; i < n_words; i++) {
278 l1_writel(0xffffffff, cpu->map_base + reg_mask_set(intc, i));
279 cpu->mask_cache[i] = 0xffffffff;
280 }
281
282 parent_irq = irq_of_parse_and_map(dn, idx);
283 if (!parent_irq) {
284 pr_err("failed to map parent interrupt %d\n", parent_irq);
285 return -EINVAL;
286 }
287
288 if (of_property_read_bool(dn, "brcm,irq-can-wake"))
289 enable_irq_wake(parent_irq);
290
291 irq_set_chained_handler_and_data(parent_irq, bcm7038_l1_irq_handle,
292 intc);
293
294 return 0;
295 }
296
297 static struct irq_chip bcm7038_l1_irq_chip = {
298 .name = "bcm7038-l1",
299 .irq_mask = bcm7038_l1_mask,
300 .irq_unmask = bcm7038_l1_unmask,
301 .irq_set_affinity = bcm7038_l1_set_affinity,
302 #ifdef CONFIG_SMP
303 .irq_cpu_offline = bcm7038_l1_cpu_offline,
304 #endif
305 };
306
bcm7038_l1_map(struct irq_domain * d,unsigned int virq,irq_hw_number_t hw_irq)307 static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq,
308 irq_hw_number_t hw_irq)
309 {
310 irq_set_chip_and_handler(virq, &bcm7038_l1_irq_chip, handle_level_irq);
311 irq_set_chip_data(virq, d->host_data);
312 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
313 return 0;
314 }
315
316 static const struct irq_domain_ops bcm7038_l1_domain_ops = {
317 .xlate = irq_domain_xlate_onecell,
318 .map = bcm7038_l1_map,
319 };
320
bcm7038_l1_of_init(struct device_node * dn,struct device_node * parent)321 int __init bcm7038_l1_of_init(struct device_node *dn,
322 struct device_node *parent)
323 {
324 struct bcm7038_l1_chip *intc;
325 int idx, ret;
326
327 intc = kzalloc(sizeof(*intc), GFP_KERNEL);
328 if (!intc)
329 return -ENOMEM;
330
331 raw_spin_lock_init(&intc->lock);
332 for_each_possible_cpu(idx) {
333 ret = bcm7038_l1_init_one(dn, idx, intc);
334 if (ret < 0) {
335 if (idx)
336 break;
337 pr_err("failed to remap intc L1 registers\n");
338 goto out_free;
339 }
340 }
341
342 intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,
343 &bcm7038_l1_domain_ops,
344 intc);
345 if (!intc->domain) {
346 ret = -ENOMEM;
347 goto out_unmap;
348 }
349
350 return 0;
351
352 out_unmap:
353 for_each_possible_cpu(idx) {
354 struct bcm7038_l1_cpu *cpu = intc->cpus[idx];
355
356 if (cpu) {
357 if (cpu->map_base)
358 iounmap(cpu->map_base);
359 kfree(cpu);
360 }
361 }
362 out_free:
363 kfree(intc);
364 return ret;
365 }
366
367 IRQCHIP_DECLARE(bcm7038_l1, "brcm,bcm7038-l1-intc", bcm7038_l1_of_init);
368