1 /*
2 * Generic Broadcom Set Top Box Level 2 Interrupt controller driver
3 *
4 * Copyright (C) 2014-2017 Broadcom
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17
18 #include <linux/init.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/spinlock.h>
23 #include <linux/of.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_address.h>
26 #include <linux/of_platform.h>
27 #include <linux/interrupt.h>
28 #include <linux/irq.h>
29 #include <linux/io.h>
30 #include <linux/irqdomain.h>
31 #include <linux/irqchip.h>
32 #include <linux/irqchip/chained_irq.h>
33
34 struct brcmstb_intc_init_params {
35 irq_flow_handler_t handler;
36 int cpu_status;
37 int cpu_clear;
38 int cpu_mask_status;
39 int cpu_mask_set;
40 int cpu_mask_clear;
41 };
42
43 /* Register offsets in the L2 latched interrupt controller */
44 static const struct brcmstb_intc_init_params l2_edge_intc_init = {
45 .handler = handle_edge_irq,
46 .cpu_status = 0x00,
47 .cpu_clear = 0x08,
48 .cpu_mask_status = 0x0c,
49 .cpu_mask_set = 0x10,
50 .cpu_mask_clear = 0x14
51 };
52
53 /* Register offsets in the L2 level interrupt controller */
54 static const struct brcmstb_intc_init_params l2_lvl_intc_init = {
55 .handler = handle_level_irq,
56 .cpu_status = 0x00,
57 .cpu_clear = -1, /* Register not present */
58 .cpu_mask_status = 0x04,
59 .cpu_mask_set = 0x08,
60 .cpu_mask_clear = 0x0C
61 };
62
63 /* L2 intc private data structure */
64 struct brcmstb_l2_intc_data {
65 struct irq_domain *domain;
66 struct irq_chip_generic *gc;
67 int status_offset;
68 int mask_offset;
69 bool can_wake;
70 u32 saved_mask; /* for suspend/resume */
71 };
72
73 /**
74 * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt
75 * @d: irq_data
76 *
77 * Chip has separate enable/disable registers instead of a single mask
78 * register and pending interrupt is acknowledged by setting a bit.
79 *
80 * Note: This function is generic and could easily be added to the
81 * generic irqchip implementation if there ever becomes a will to do so.
82 * Perhaps with a name like irq_gc_mask_disable_and_ack_set().
83 *
84 * e.g.: https://patchwork.kernel.org/patch/9831047/
85 */
brcmstb_l2_mask_and_ack(struct irq_data * d)86 static void brcmstb_l2_mask_and_ack(struct irq_data *d)
87 {
88 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
89 struct irq_chip_type *ct = irq_data_get_chip_type(d);
90 u32 mask = d->mask;
91
92 irq_gc_lock(gc);
93 irq_reg_writel(gc, mask, ct->regs.disable);
94 *ct->mask_cache &= ~mask;
95 irq_reg_writel(gc, mask, ct->regs.ack);
96 irq_gc_unlock(gc);
97 }
98
brcmstb_l2_intc_irq_handle(struct irq_desc * desc)99 static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc)
100 {
101 struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
102 struct irq_chip *chip = irq_desc_get_chip(desc);
103 unsigned int irq;
104 u32 status;
105
106 chained_irq_enter(chip, desc);
107
108 status = irq_reg_readl(b->gc, b->status_offset) &
109 ~(irq_reg_readl(b->gc, b->mask_offset));
110
111 if (status == 0) {
112 raw_spin_lock(&desc->lock);
113 handle_bad_irq(desc);
114 raw_spin_unlock(&desc->lock);
115 goto out;
116 }
117
118 do {
119 irq = ffs(status) - 1;
120 status &= ~(1 << irq);
121 generic_handle_irq(irq_linear_revmap(b->domain, irq));
122 } while (status);
123 out:
124 chained_irq_exit(chip, desc);
125 }
126
brcmstb_l2_intc_suspend(struct irq_data * d)127 static void brcmstb_l2_intc_suspend(struct irq_data *d)
128 {
129 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
130 struct irq_chip_type *ct = irq_data_get_chip_type(d);
131 struct brcmstb_l2_intc_data *b = gc->private;
132 unsigned long flags;
133
134 irq_gc_lock_irqsave(gc, flags);
135 /* Save the current mask */
136 b->saved_mask = irq_reg_readl(gc, ct->regs.mask);
137
138 if (b->can_wake) {
139 /* Program the wakeup mask */
140 irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);
141 irq_reg_writel(gc, gc->wake_active, ct->regs.enable);
142 }
143 irq_gc_unlock_irqrestore(gc, flags);
144 }
145
brcmstb_l2_intc_resume(struct irq_data * d)146 static void brcmstb_l2_intc_resume(struct irq_data *d)
147 {
148 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
149 struct irq_chip_type *ct = irq_data_get_chip_type(d);
150 struct brcmstb_l2_intc_data *b = gc->private;
151 unsigned long flags;
152
153 irq_gc_lock_irqsave(gc, flags);
154 if (ct->chip.irq_ack) {
155 /* Clear unmasked non-wakeup interrupts */
156 irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,
157 ct->regs.ack);
158 }
159
160 /* Restore the saved mask */
161 irq_reg_writel(gc, b->saved_mask, ct->regs.disable);
162 irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);
163 irq_gc_unlock_irqrestore(gc, flags);
164 }
165
brcmstb_l2_intc_of_init(struct device_node * np,struct device_node * parent,const struct brcmstb_intc_init_params * init_params)166 static int __init brcmstb_l2_intc_of_init(struct device_node *np,
167 struct device_node *parent,
168 const struct brcmstb_intc_init_params
169 *init_params)
170 {
171 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
172 unsigned int set = 0;
173 struct brcmstb_l2_intc_data *data;
174 struct irq_chip_type *ct;
175 int ret;
176 unsigned int flags;
177 int parent_irq;
178 void __iomem *base;
179
180 data = kzalloc(sizeof(*data), GFP_KERNEL);
181 if (!data)
182 return -ENOMEM;
183
184 base = of_iomap(np, 0);
185 if (!base) {
186 pr_err("failed to remap intc L2 registers\n");
187 ret = -ENOMEM;
188 goto out_free;
189 }
190
191 /* Disable all interrupts by default */
192 writel(0xffffffff, base + init_params->cpu_mask_set);
193
194 /* Wakeup interrupts may be retained from S5 (cold boot) */
195 data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake");
196 if (!data->can_wake && (init_params->cpu_clear >= 0))
197 writel(0xffffffff, base + init_params->cpu_clear);
198
199 parent_irq = irq_of_parse_and_map(np, 0);
200 if (!parent_irq) {
201 pr_err("failed to find parent interrupt\n");
202 ret = -EINVAL;
203 goto out_unmap;
204 }
205
206 data->domain = irq_domain_add_linear(np, 32,
207 &irq_generic_chip_ops, NULL);
208 if (!data->domain) {
209 ret = -ENOMEM;
210 goto out_unmap;
211 }
212
213 /* MIPS chips strapped for BE will automagically configure the
214 * peripheral registers for CPU-native byte order.
215 */
216 flags = 0;
217 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
218 flags |= IRQ_GC_BE_IO;
219
220 if (init_params->handler == handle_level_irq)
221 set |= IRQ_LEVEL;
222
223 /* Allocate a single Generic IRQ chip for this node */
224 ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
225 np->full_name, init_params->handler, clr, set, flags);
226 if (ret) {
227 pr_err("failed to allocate generic irq chip\n");
228 goto out_free_domain;
229 }
230
231 /* Set the IRQ chaining logic */
232 irq_set_chained_handler_and_data(parent_irq,
233 brcmstb_l2_intc_irq_handle, data);
234
235 data->gc = irq_get_domain_generic_chip(data->domain, 0);
236 data->gc->reg_base = base;
237 data->gc->private = data;
238 data->status_offset = init_params->cpu_status;
239 data->mask_offset = init_params->cpu_mask_status;
240
241 ct = data->gc->chip_types;
242
243 if (init_params->cpu_clear >= 0) {
244 ct->regs.ack = init_params->cpu_clear;
245 ct->chip.irq_ack = irq_gc_ack_set_bit;
246 ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack;
247 } else {
248 /* No Ack - but still slightly more efficient to define this */
249 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
250 }
251
252 ct->chip.irq_mask = irq_gc_mask_disable_reg;
253 ct->regs.disable = init_params->cpu_mask_set;
254 ct->regs.mask = init_params->cpu_mask_status;
255
256 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
257 ct->regs.enable = init_params->cpu_mask_clear;
258
259 ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
260 ct->chip.irq_resume = brcmstb_l2_intc_resume;
261 ct->chip.irq_pm_shutdown = brcmstb_l2_intc_suspend;
262
263 if (data->can_wake) {
264 /* This IRQ chip can wake the system, set all child interrupts
265 * in wake_enabled mask
266 */
267 data->gc->wake_enabled = 0xffffffff;
268 ct->chip.irq_set_wake = irq_gc_set_wake;
269 }
270
271 return 0;
272
273 out_free_domain:
274 irq_domain_remove(data->domain);
275 out_unmap:
276 iounmap(base);
277 out_free:
278 kfree(data);
279 return ret;
280 }
281
brcmstb_l2_edge_intc_of_init(struct device_node * np,struct device_node * parent)282 int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
283 struct device_node *parent)
284 {
285 return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init);
286 }
287 IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init);
288
brcmstb_l2_lvl_intc_of_init(struct device_node * np,struct device_node * parent)289 int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
290 struct device_node *parent)
291 {
292 return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
293 }
294 IRQCHIP_DECLARE(bcm7271_l2_intc, "brcm,bcm7271-l2-intc",
295 brcmstb_l2_lvl_intc_of_init);
296