1 /*
2 * Copyright (c) 2015 Endless Mobile, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 * Copyright (c) 2016 BayLibre, SAS.
5 * Author: Jerome Brunet <jbrunet@baylibre.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution
19 * in the file called COPYING.
20 */
21
22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23
24 #include <linux/io.h>
25 #include <linux/module.h>
26 #include <linux/irq.h>
27 #include <linux/irqdomain.h>
28 #include <linux/irqchip.h>
29 #include <linux/of.h>
30 #include <linux/of_address.h>
31
32 #define NUM_CHANNEL 8
33 #define MAX_INPUT_MUX 256
34
35 #define REG_EDGE_POL 0x00
36 #define REG_PIN_03_SEL 0x04
37 #define REG_PIN_47_SEL 0x08
38 #define REG_FILTER_SEL 0x0c
39
40 #define REG_EDGE_POL_MASK(x) (BIT(x) | BIT(16 + (x)))
41 #define REG_EDGE_POL_EDGE(x) BIT(x)
42 #define REG_EDGE_POL_LOW(x) BIT(16 + (x))
43 #define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8)
44 #define REG_FILTER_SEL_SHIFT(x) ((x) * 4)
45
46 struct meson_gpio_irq_params {
47 unsigned int nr_hwirq;
48 };
49
50 static const struct meson_gpio_irq_params meson8_params = {
51 .nr_hwirq = 134,
52 };
53
54 static const struct meson_gpio_irq_params meson8b_params = {
55 .nr_hwirq = 119,
56 };
57
58 static const struct meson_gpio_irq_params gxbb_params = {
59 .nr_hwirq = 133,
60 };
61
62 static const struct meson_gpio_irq_params gxl_params = {
63 .nr_hwirq = 110,
64 };
65
66 static const struct meson_gpio_irq_params axg_params = {
67 .nr_hwirq = 100,
68 };
69
70 static const struct of_device_id meson_irq_gpio_matches[] __maybe_unused = {
71 { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
72 { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
73 { .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params },
74 { .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
75 { .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
76 { .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params },
77 { }
78 };
79
80 struct meson_gpio_irq_controller {
81 unsigned int nr_hwirq;
82 void __iomem *base;
83 u32 channel_irqs[NUM_CHANNEL];
84 DECLARE_BITMAP(channel_map, NUM_CHANNEL);
85 spinlock_t lock;
86 };
87
meson_gpio_irq_update_bits(struct meson_gpio_irq_controller * ctl,unsigned int reg,u32 mask,u32 val)88 static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl,
89 unsigned int reg, u32 mask, u32 val)
90 {
91 u32 tmp;
92
93 tmp = readl_relaxed(ctl->base + reg);
94 tmp &= ~mask;
95 tmp |= val;
96 writel_relaxed(tmp, ctl->base + reg);
97 }
98
meson_gpio_irq_channel_to_reg(unsigned int channel)99 static unsigned int meson_gpio_irq_channel_to_reg(unsigned int channel)
100 {
101 return (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL;
102 }
103
104 static int
meson_gpio_irq_request_channel(struct meson_gpio_irq_controller * ctl,unsigned long hwirq,u32 ** channel_hwirq)105 meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
106 unsigned long hwirq,
107 u32 **channel_hwirq)
108 {
109 unsigned int reg, idx;
110
111 spin_lock(&ctl->lock);
112
113 /* Find a free channel */
114 idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL);
115 if (idx >= NUM_CHANNEL) {
116 spin_unlock(&ctl->lock);
117 pr_err("No channel available\n");
118 return -ENOSPC;
119 }
120
121 /* Mark the channel as used */
122 set_bit(idx, ctl->channel_map);
123
124 /*
125 * Setup the mux of the channel to route the signal of the pad
126 * to the appropriate input of the GIC
127 */
128 reg = meson_gpio_irq_channel_to_reg(idx);
129 meson_gpio_irq_update_bits(ctl, reg,
130 0xff << REG_PIN_SEL_SHIFT(idx),
131 hwirq << REG_PIN_SEL_SHIFT(idx));
132
133 /*
134 * Get the hwirq number assigned to this channel through
135 * a pointer the channel_irq table. The added benifit of this
136 * method is that we can also retrieve the channel index with
137 * it, using the table base.
138 */
139 *channel_hwirq = &(ctl->channel_irqs[idx]);
140
141 spin_unlock(&ctl->lock);
142
143 pr_debug("hwirq %lu assigned to channel %d - irq %u\n",
144 hwirq, idx, **channel_hwirq);
145
146 return 0;
147 }
148
149 static unsigned int
meson_gpio_irq_get_channel_idx(struct meson_gpio_irq_controller * ctl,u32 * channel_hwirq)150 meson_gpio_irq_get_channel_idx(struct meson_gpio_irq_controller *ctl,
151 u32 *channel_hwirq)
152 {
153 return channel_hwirq - ctl->channel_irqs;
154 }
155
156 static void
meson_gpio_irq_release_channel(struct meson_gpio_irq_controller * ctl,u32 * channel_hwirq)157 meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl,
158 u32 *channel_hwirq)
159 {
160 unsigned int idx;
161
162 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
163 clear_bit(idx, ctl->channel_map);
164 }
165
meson_gpio_irq_type_setup(struct meson_gpio_irq_controller * ctl,unsigned int type,u32 * channel_hwirq)166 static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,
167 unsigned int type,
168 u32 *channel_hwirq)
169 {
170 u32 val = 0;
171 unsigned int idx;
172
173 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
174
175 /*
176 * The controller has a filter block to operate in either LEVEL or
177 * EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW and
178 * EDGE_FALLING support (which the GIC does not support), the filter
179 * block is also able to invert the input signal it gets before
180 * providing it to the GIC.
181 */
182 type &= IRQ_TYPE_SENSE_MASK;
183
184 if (type == IRQ_TYPE_EDGE_BOTH)
185 return -EINVAL;
186
187 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
188 val |= REG_EDGE_POL_EDGE(idx);
189
190 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
191 val |= REG_EDGE_POL_LOW(idx);
192
193 spin_lock(&ctl->lock);
194
195 meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
196 REG_EDGE_POL_MASK(idx), val);
197
198 spin_unlock(&ctl->lock);
199
200 return 0;
201 }
202
meson_gpio_irq_type_output(unsigned int type)203 static unsigned int meson_gpio_irq_type_output(unsigned int type)
204 {
205 unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
206
207 type &= ~IRQ_TYPE_SENSE_MASK;
208
209 /*
210 * The polarity of the signal provided to the GIC should always
211 * be high.
212 */
213 if (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
214 type |= IRQ_TYPE_LEVEL_HIGH;
215 else if (sense & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
216 type |= IRQ_TYPE_EDGE_RISING;
217
218 return type;
219 }
220
meson_gpio_irq_set_type(struct irq_data * data,unsigned int type)221 static int meson_gpio_irq_set_type(struct irq_data *data, unsigned int type)
222 {
223 struct meson_gpio_irq_controller *ctl = data->domain->host_data;
224 u32 *channel_hwirq = irq_data_get_irq_chip_data(data);
225 int ret;
226
227 ret = meson_gpio_irq_type_setup(ctl, type, channel_hwirq);
228 if (ret)
229 return ret;
230
231 return irq_chip_set_type_parent(data,
232 meson_gpio_irq_type_output(type));
233 }
234
235 static struct irq_chip meson_gpio_irq_chip = {
236 .name = "meson-gpio-irqchip",
237 .irq_mask = irq_chip_mask_parent,
238 .irq_unmask = irq_chip_unmask_parent,
239 .irq_eoi = irq_chip_eoi_parent,
240 .irq_set_type = meson_gpio_irq_set_type,
241 .irq_retrigger = irq_chip_retrigger_hierarchy,
242 #ifdef CONFIG_SMP
243 .irq_set_affinity = irq_chip_set_affinity_parent,
244 #endif
245 .flags = IRQCHIP_SET_TYPE_MASKED,
246 };
247
meson_gpio_irq_domain_translate(struct irq_domain * domain,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)248 static int meson_gpio_irq_domain_translate(struct irq_domain *domain,
249 struct irq_fwspec *fwspec,
250 unsigned long *hwirq,
251 unsigned int *type)
252 {
253 if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
254 *hwirq = fwspec->param[0];
255 *type = fwspec->param[1];
256 return 0;
257 }
258
259 return -EINVAL;
260 }
261
meson_gpio_irq_allocate_gic_irq(struct irq_domain * domain,unsigned int virq,u32 hwirq,unsigned int type)262 static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain,
263 unsigned int virq,
264 u32 hwirq,
265 unsigned int type)
266 {
267 struct irq_fwspec fwspec;
268
269 fwspec.fwnode = domain->parent->fwnode;
270 fwspec.param_count = 3;
271 fwspec.param[0] = 0; /* SPI */
272 fwspec.param[1] = hwirq;
273 fwspec.param[2] = meson_gpio_irq_type_output(type);
274
275 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
276 }
277
meson_gpio_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * data)278 static int meson_gpio_irq_domain_alloc(struct irq_domain *domain,
279 unsigned int virq,
280 unsigned int nr_irqs,
281 void *data)
282 {
283 struct irq_fwspec *fwspec = data;
284 struct meson_gpio_irq_controller *ctl = domain->host_data;
285 unsigned long hwirq;
286 u32 *channel_hwirq;
287 unsigned int type;
288 int ret;
289
290 if (WARN_ON(nr_irqs != 1))
291 return -EINVAL;
292
293 ret = meson_gpio_irq_domain_translate(domain, fwspec, &hwirq, &type);
294 if (ret)
295 return ret;
296
297 ret = meson_gpio_irq_request_channel(ctl, hwirq, &channel_hwirq);
298 if (ret)
299 return ret;
300
301 ret = meson_gpio_irq_allocate_gic_irq(domain, virq,
302 *channel_hwirq, type);
303 if (ret < 0) {
304 pr_err("failed to allocate gic irq %u\n", *channel_hwirq);
305 meson_gpio_irq_release_channel(ctl, channel_hwirq);
306 return ret;
307 }
308
309 irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
310 &meson_gpio_irq_chip, channel_hwirq);
311
312 return 0;
313 }
314
meson_gpio_irq_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)315 static void meson_gpio_irq_domain_free(struct irq_domain *domain,
316 unsigned int virq,
317 unsigned int nr_irqs)
318 {
319 struct meson_gpio_irq_controller *ctl = domain->host_data;
320 struct irq_data *irq_data;
321 u32 *channel_hwirq;
322
323 if (WARN_ON(nr_irqs != 1))
324 return;
325
326 irq_domain_free_irqs_parent(domain, virq, 1);
327
328 irq_data = irq_domain_get_irq_data(domain, virq);
329 channel_hwirq = irq_data_get_irq_chip_data(irq_data);
330
331 meson_gpio_irq_release_channel(ctl, channel_hwirq);
332 }
333
334 static const struct irq_domain_ops meson_gpio_irq_domain_ops = {
335 .alloc = meson_gpio_irq_domain_alloc,
336 .free = meson_gpio_irq_domain_free,
337 .translate = meson_gpio_irq_domain_translate,
338 };
339
meson_gpio_irq_parse_dt(struct device_node * node,struct meson_gpio_irq_controller * ctl)340 static int __init meson_gpio_irq_parse_dt(struct device_node *node,
341 struct meson_gpio_irq_controller *ctl)
342 {
343 const struct of_device_id *match;
344 const struct meson_gpio_irq_params *params;
345 int ret;
346
347 match = of_match_node(meson_irq_gpio_matches, node);
348 if (!match)
349 return -ENODEV;
350
351 params = match->data;
352 ctl->nr_hwirq = params->nr_hwirq;
353
354 ret = of_property_read_variable_u32_array(node,
355 "amlogic,channel-interrupts",
356 ctl->channel_irqs,
357 NUM_CHANNEL,
358 NUM_CHANNEL);
359 if (ret < 0) {
360 pr_err("can't get %d channel interrupts\n", NUM_CHANNEL);
361 return ret;
362 }
363
364 return 0;
365 }
366
meson_gpio_irq_of_init(struct device_node * node,struct device_node * parent)367 static int __init meson_gpio_irq_of_init(struct device_node *node,
368 struct device_node *parent)
369 {
370 struct irq_domain *domain, *parent_domain;
371 struct meson_gpio_irq_controller *ctl;
372 int ret;
373
374 if (!parent) {
375 pr_err("missing parent interrupt node\n");
376 return -ENODEV;
377 }
378
379 parent_domain = irq_find_host(parent);
380 if (!parent_domain) {
381 pr_err("unable to obtain parent domain\n");
382 return -ENXIO;
383 }
384
385 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
386 if (!ctl)
387 return -ENOMEM;
388
389 spin_lock_init(&ctl->lock);
390
391 ctl->base = of_iomap(node, 0);
392 if (!ctl->base) {
393 ret = -ENOMEM;
394 goto free_ctl;
395 }
396
397 ret = meson_gpio_irq_parse_dt(node, ctl);
398 if (ret)
399 goto free_channel_irqs;
400
401 domain = irq_domain_create_hierarchy(parent_domain, 0, ctl->nr_hwirq,
402 of_node_to_fwnode(node),
403 &meson_gpio_irq_domain_ops,
404 ctl);
405 if (!domain) {
406 pr_err("failed to add domain\n");
407 ret = -ENODEV;
408 goto free_channel_irqs;
409 }
410
411 pr_info("%d to %d gpio interrupt mux initialized\n",
412 ctl->nr_hwirq, NUM_CHANNEL);
413
414 return 0;
415
416 free_channel_irqs:
417 iounmap(ctl->base);
418 free_ctl:
419 kfree(ctl);
420
421 return ret;
422 }
423
424 IRQCHIP_DECLARE(meson_gpio_intc, "amlogic,meson-gpio-intc",
425 meson_gpio_irq_of_init);
426