1 /*
2 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
3 * Copyright (C) 2014 Stefan Kristansson <stefan.kristiansson@saunalahti.fi>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11 #include <linux/irq.h>
12 #include <linux/irqchip.h>
13 #include <linux/of.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_address.h>
16
17 /* OR1K PIC implementation */
18
19 struct or1k_pic_dev {
20 struct irq_chip chip;
21 irq_flow_handler_t handle;
22 unsigned long flags;
23 };
24
25 /*
26 * We're a couple of cycles faster than the generic implementations with
27 * these 'fast' versions.
28 */
29
or1k_pic_mask(struct irq_data * data)30 static void or1k_pic_mask(struct irq_data *data)
31 {
32 mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
33 }
34
or1k_pic_unmask(struct irq_data * data)35 static void or1k_pic_unmask(struct irq_data *data)
36 {
37 mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (1UL << data->hwirq));
38 }
39
or1k_pic_ack(struct irq_data * data)40 static void or1k_pic_ack(struct irq_data *data)
41 {
42 mtspr(SPR_PICSR, (1UL << data->hwirq));
43 }
44
or1k_pic_mask_ack(struct irq_data * data)45 static void or1k_pic_mask_ack(struct irq_data *data)
46 {
47 mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
48 mtspr(SPR_PICSR, (1UL << data->hwirq));
49 }
50
51 /*
52 * There are two oddities with the OR1200 PIC implementation:
53 * i) LEVEL-triggered interrupts are latched and need to be cleared
54 * ii) the interrupt latch is cleared by writing a 0 to the bit,
55 * as opposed to a 1 as mandated by the spec
56 */
or1k_pic_or1200_ack(struct irq_data * data)57 static void or1k_pic_or1200_ack(struct irq_data *data)
58 {
59 mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));
60 }
61
or1k_pic_or1200_mask_ack(struct irq_data * data)62 static void or1k_pic_or1200_mask_ack(struct irq_data *data)
63 {
64 mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
65 mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));
66 }
67
68 static struct or1k_pic_dev or1k_pic_level = {
69 .chip = {
70 .name = "or1k-PIC-level",
71 .irq_unmask = or1k_pic_unmask,
72 .irq_mask = or1k_pic_mask,
73 },
74 .handle = handle_level_irq,
75 .flags = IRQ_LEVEL | IRQ_NOPROBE,
76 };
77
78 static struct or1k_pic_dev or1k_pic_edge = {
79 .chip = {
80 .name = "or1k-PIC-edge",
81 .irq_unmask = or1k_pic_unmask,
82 .irq_mask = or1k_pic_mask,
83 .irq_ack = or1k_pic_ack,
84 .irq_mask_ack = or1k_pic_mask_ack,
85 },
86 .handle = handle_edge_irq,
87 .flags = IRQ_LEVEL | IRQ_NOPROBE,
88 };
89
90 static struct or1k_pic_dev or1k_pic_or1200 = {
91 .chip = {
92 .name = "or1200-PIC",
93 .irq_unmask = or1k_pic_unmask,
94 .irq_mask = or1k_pic_mask,
95 .irq_ack = or1k_pic_or1200_ack,
96 .irq_mask_ack = or1k_pic_or1200_mask_ack,
97 },
98 .handle = handle_level_irq,
99 .flags = IRQ_LEVEL | IRQ_NOPROBE,
100 };
101
102 static struct irq_domain *root_domain;
103
pic_get_irq(int first)104 static inline int pic_get_irq(int first)
105 {
106 int hwirq;
107
108 hwirq = ffs(mfspr(SPR_PICSR) >> first);
109 if (!hwirq)
110 return NO_IRQ;
111 else
112 hwirq = hwirq + first - 1;
113
114 return hwirq;
115 }
116
or1k_pic_handle_irq(struct pt_regs * regs)117 static void or1k_pic_handle_irq(struct pt_regs *regs)
118 {
119 int irq = -1;
120
121 while ((irq = pic_get_irq(irq + 1)) != NO_IRQ)
122 handle_domain_irq(root_domain, irq, regs);
123 }
124
or1k_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)125 static int or1k_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
126 {
127 struct or1k_pic_dev *pic = d->host_data;
128
129 irq_set_chip_and_handler(irq, &pic->chip, pic->handle);
130 irq_set_status_flags(irq, pic->flags);
131
132 return 0;
133 }
134
135 static const struct irq_domain_ops or1k_irq_domain_ops = {
136 .xlate = irq_domain_xlate_onecell,
137 .map = or1k_map,
138 };
139
140 /*
141 * This sets up the IRQ domain for the PIC built in to the OpenRISC
142 * 1000 CPU. This is the "root" domain as these are the interrupts
143 * that directly trigger an exception in the CPU.
144 */
or1k_pic_init(struct device_node * node,struct or1k_pic_dev * pic)145 static int __init or1k_pic_init(struct device_node *node,
146 struct or1k_pic_dev *pic)
147 {
148 /* Disable all interrupts until explicitly requested */
149 mtspr(SPR_PICMR, (0UL));
150
151 root_domain = irq_domain_add_linear(node, 32, &or1k_irq_domain_ops,
152 pic);
153
154 set_handle_irq(or1k_pic_handle_irq);
155
156 return 0;
157 }
158
or1k_pic_or1200_init(struct device_node * node,struct device_node * parent)159 static int __init or1k_pic_or1200_init(struct device_node *node,
160 struct device_node *parent)
161 {
162 return or1k_pic_init(node, &or1k_pic_or1200);
163 }
164 IRQCHIP_DECLARE(or1k_pic_or1200, "opencores,or1200-pic", or1k_pic_or1200_init);
165 IRQCHIP_DECLARE(or1k_pic, "opencores,or1k-pic", or1k_pic_or1200_init);
166
or1k_pic_level_init(struct device_node * node,struct device_node * parent)167 static int __init or1k_pic_level_init(struct device_node *node,
168 struct device_node *parent)
169 {
170 return or1k_pic_init(node, &or1k_pic_level);
171 }
172 IRQCHIP_DECLARE(or1k_pic_level, "opencores,or1k-pic-level",
173 or1k_pic_level_init);
174
or1k_pic_edge_init(struct device_node * node,struct device_node * parent)175 static int __init or1k_pic_edge_init(struct device_node *node,
176 struct device_node *parent)
177 {
178 return or1k_pic_init(node, &or1k_pic_edge);
179 }
180 IRQCHIP_DECLARE(or1k_pic_edge, "opencores,or1k-pic-edge", or1k_pic_edge_init);
181