1 /*
2 * S3C24XX IRQ handling
3 *
4 * Copyright (c) 2003-2004 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 #include <linux/init.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/io.h>
23 #include <linux/err.h>
24 #include <linux/interrupt.h>
25 #include <linux/ioport.h>
26 #include <linux/device.h>
27 #include <linux/irqdomain.h>
28 #include <linux/irqchip.h>
29 #include <linux/irqchip/chained_irq.h>
30 #include <linux/of.h>
31 #include <linux/of_irq.h>
32 #include <linux/of_address.h>
33
34 #include <asm/exception.h>
35 #include <asm/mach/irq.h>
36
37 #include <mach/regs-irq.h>
38 #include <mach/regs-gpio.h>
39
40 #include <plat/cpu.h>
41 #include <plat/regs-irqtype.h>
42 #include <plat/pm.h>
43
44 #define S3C_IRQTYPE_NONE 0
45 #define S3C_IRQTYPE_EINT 1
46 #define S3C_IRQTYPE_EDGE 2
47 #define S3C_IRQTYPE_LEVEL 3
48
49 struct s3c_irq_data {
50 unsigned int type;
51 unsigned long offset;
52 unsigned long parent_irq;
53
54 /* data gets filled during init */
55 struct s3c_irq_intc *intc;
56 unsigned long sub_bits;
57 struct s3c_irq_intc *sub_intc;
58 };
59
60 /*
61 * Sructure holding the controller data
62 * @reg_pending register holding pending irqs
63 * @reg_intpnd special register intpnd in main intc
64 * @reg_mask mask register
65 * @domain irq_domain of the controller
66 * @parent parent controller for ext and sub irqs
67 * @irqs irq-data, always s3c_irq_data[32]
68 */
69 struct s3c_irq_intc {
70 void __iomem *reg_pending;
71 void __iomem *reg_intpnd;
72 void __iomem *reg_mask;
73 struct irq_domain *domain;
74 struct s3c_irq_intc *parent;
75 struct s3c_irq_data *irqs;
76 };
77
78 /*
79 * Array holding pointers to the global controller structs
80 * [0] ... main_intc
81 * [1] ... sub_intc
82 * [2] ... main_intc2 on s3c2416
83 */
84 static struct s3c_irq_intc *s3c_intc[3];
85
s3c_irq_mask(struct irq_data * data)86 static void s3c_irq_mask(struct irq_data *data)
87 {
88 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
89 struct s3c_irq_intc *intc = irq_data->intc;
90 struct s3c_irq_intc *parent_intc = intc->parent;
91 struct s3c_irq_data *parent_data;
92 unsigned long mask;
93 unsigned int irqno;
94
95 mask = readl_relaxed(intc->reg_mask);
96 mask |= (1UL << irq_data->offset);
97 writel_relaxed(mask, intc->reg_mask);
98
99 if (parent_intc) {
100 parent_data = &parent_intc->irqs[irq_data->parent_irq];
101
102 /* check to see if we need to mask the parent IRQ
103 * The parent_irq is always in main_intc, so the hwirq
104 * for find_mapping does not need an offset in any case.
105 */
106 if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
107 irqno = irq_find_mapping(parent_intc->domain,
108 irq_data->parent_irq);
109 s3c_irq_mask(irq_get_irq_data(irqno));
110 }
111 }
112 }
113
s3c_irq_unmask(struct irq_data * data)114 static void s3c_irq_unmask(struct irq_data *data)
115 {
116 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
117 struct s3c_irq_intc *intc = irq_data->intc;
118 struct s3c_irq_intc *parent_intc = intc->parent;
119 unsigned long mask;
120 unsigned int irqno;
121
122 mask = readl_relaxed(intc->reg_mask);
123 mask &= ~(1UL << irq_data->offset);
124 writel_relaxed(mask, intc->reg_mask);
125
126 if (parent_intc) {
127 irqno = irq_find_mapping(parent_intc->domain,
128 irq_data->parent_irq);
129 s3c_irq_unmask(irq_get_irq_data(irqno));
130 }
131 }
132
s3c_irq_ack(struct irq_data * data)133 static inline void s3c_irq_ack(struct irq_data *data)
134 {
135 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
136 struct s3c_irq_intc *intc = irq_data->intc;
137 unsigned long bitval = 1UL << irq_data->offset;
138
139 writel_relaxed(bitval, intc->reg_pending);
140 if (intc->reg_intpnd)
141 writel_relaxed(bitval, intc->reg_intpnd);
142 }
143
s3c_irq_type(struct irq_data * data,unsigned int type)144 static int s3c_irq_type(struct irq_data *data, unsigned int type)
145 {
146 switch (type) {
147 case IRQ_TYPE_NONE:
148 break;
149 case IRQ_TYPE_EDGE_RISING:
150 case IRQ_TYPE_EDGE_FALLING:
151 case IRQ_TYPE_EDGE_BOTH:
152 irq_set_handler(data->irq, handle_edge_irq);
153 break;
154 case IRQ_TYPE_LEVEL_LOW:
155 case IRQ_TYPE_LEVEL_HIGH:
156 irq_set_handler(data->irq, handle_level_irq);
157 break;
158 default:
159 pr_err("No such irq type %d\n", type);
160 return -EINVAL;
161 }
162
163 return 0;
164 }
165
s3c_irqext_type_set(void __iomem * gpcon_reg,void __iomem * extint_reg,unsigned long gpcon_offset,unsigned long extint_offset,unsigned int type)166 static int s3c_irqext_type_set(void __iomem *gpcon_reg,
167 void __iomem *extint_reg,
168 unsigned long gpcon_offset,
169 unsigned long extint_offset,
170 unsigned int type)
171 {
172 unsigned long newvalue = 0, value;
173
174 /* Set the GPIO to external interrupt mode */
175 value = readl_relaxed(gpcon_reg);
176 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
177 writel_relaxed(value, gpcon_reg);
178
179 /* Set the external interrupt to pointed trigger type */
180 switch (type)
181 {
182 case IRQ_TYPE_NONE:
183 pr_warn("No edge setting!\n");
184 break;
185
186 case IRQ_TYPE_EDGE_RISING:
187 newvalue = S3C2410_EXTINT_RISEEDGE;
188 break;
189
190 case IRQ_TYPE_EDGE_FALLING:
191 newvalue = S3C2410_EXTINT_FALLEDGE;
192 break;
193
194 case IRQ_TYPE_EDGE_BOTH:
195 newvalue = S3C2410_EXTINT_BOTHEDGE;
196 break;
197
198 case IRQ_TYPE_LEVEL_LOW:
199 newvalue = S3C2410_EXTINT_LOWLEV;
200 break;
201
202 case IRQ_TYPE_LEVEL_HIGH:
203 newvalue = S3C2410_EXTINT_HILEV;
204 break;
205
206 default:
207 pr_err("No such irq type %d\n", type);
208 return -EINVAL;
209 }
210
211 value = readl_relaxed(extint_reg);
212 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
213 writel_relaxed(value, extint_reg);
214
215 return 0;
216 }
217
s3c_irqext_type(struct irq_data * data,unsigned int type)218 static int s3c_irqext_type(struct irq_data *data, unsigned int type)
219 {
220 void __iomem *extint_reg;
221 void __iomem *gpcon_reg;
222 unsigned long gpcon_offset, extint_offset;
223
224 if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
225 gpcon_reg = S3C2410_GPFCON;
226 extint_reg = S3C24XX_EXTINT0;
227 gpcon_offset = (data->hwirq) * 2;
228 extint_offset = (data->hwirq) * 4;
229 } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
230 gpcon_reg = S3C2410_GPGCON;
231 extint_reg = S3C24XX_EXTINT1;
232 gpcon_offset = (data->hwirq - 8) * 2;
233 extint_offset = (data->hwirq - 8) * 4;
234 } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
235 gpcon_reg = S3C2410_GPGCON;
236 extint_reg = S3C24XX_EXTINT2;
237 gpcon_offset = (data->hwirq - 8) * 2;
238 extint_offset = (data->hwirq - 16) * 4;
239 } else {
240 return -EINVAL;
241 }
242
243 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
244 extint_offset, type);
245 }
246
s3c_irqext0_type(struct irq_data * data,unsigned int type)247 static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
248 {
249 void __iomem *extint_reg;
250 void __iomem *gpcon_reg;
251 unsigned long gpcon_offset, extint_offset;
252
253 if (data->hwirq <= 3) {
254 gpcon_reg = S3C2410_GPFCON;
255 extint_reg = S3C24XX_EXTINT0;
256 gpcon_offset = (data->hwirq) * 2;
257 extint_offset = (data->hwirq) * 4;
258 } else {
259 return -EINVAL;
260 }
261
262 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
263 extint_offset, type);
264 }
265
266 static struct irq_chip s3c_irq_chip = {
267 .name = "s3c",
268 .irq_ack = s3c_irq_ack,
269 .irq_mask = s3c_irq_mask,
270 .irq_unmask = s3c_irq_unmask,
271 .irq_set_type = s3c_irq_type,
272 .irq_set_wake = s3c_irq_wake
273 };
274
275 static struct irq_chip s3c_irq_level_chip = {
276 .name = "s3c-level",
277 .irq_mask = s3c_irq_mask,
278 .irq_unmask = s3c_irq_unmask,
279 .irq_ack = s3c_irq_ack,
280 .irq_set_type = s3c_irq_type,
281 };
282
283 static struct irq_chip s3c_irqext_chip = {
284 .name = "s3c-ext",
285 .irq_mask = s3c_irq_mask,
286 .irq_unmask = s3c_irq_unmask,
287 .irq_ack = s3c_irq_ack,
288 .irq_set_type = s3c_irqext_type,
289 .irq_set_wake = s3c_irqext_wake
290 };
291
292 static struct irq_chip s3c_irq_eint0t4 = {
293 .name = "s3c-ext0",
294 .irq_ack = s3c_irq_ack,
295 .irq_mask = s3c_irq_mask,
296 .irq_unmask = s3c_irq_unmask,
297 .irq_set_wake = s3c_irq_wake,
298 .irq_set_type = s3c_irqext0_type,
299 };
300
s3c_irq_demux(struct irq_desc * desc)301 static void s3c_irq_demux(struct irq_desc *desc)
302 {
303 struct irq_chip *chip = irq_desc_get_chip(desc);
304 struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc);
305 struct s3c_irq_intc *intc = irq_data->intc;
306 struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
307 unsigned int n, offset, irq;
308 unsigned long src, msk;
309
310 /* we're using individual domains for the non-dt case
311 * and one big domain for the dt case where the subintc
312 * starts at hwirq number 32.
313 */
314 offset = irq_domain_get_of_node(intc->domain) ? 32 : 0;
315
316 chained_irq_enter(chip, desc);
317
318 src = readl_relaxed(sub_intc->reg_pending);
319 msk = readl_relaxed(sub_intc->reg_mask);
320
321 src &= ~msk;
322 src &= irq_data->sub_bits;
323
324 while (src) {
325 n = __ffs(src);
326 src &= ~(1 << n);
327 irq = irq_find_mapping(sub_intc->domain, offset + n);
328 generic_handle_irq(irq);
329 }
330
331 chained_irq_exit(chip, desc);
332 }
333
s3c24xx_handle_intc(struct s3c_irq_intc * intc,struct pt_regs * regs,int intc_offset)334 static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
335 struct pt_regs *regs, int intc_offset)
336 {
337 int pnd;
338 int offset;
339
340 pnd = readl_relaxed(intc->reg_intpnd);
341 if (!pnd)
342 return false;
343
344 /* non-dt machines use individual domains */
345 if (!irq_domain_get_of_node(intc->domain))
346 intc_offset = 0;
347
348 /* We have a problem that the INTOFFSET register does not always
349 * show one interrupt. Occasionally we get two interrupts through
350 * the prioritiser, and this causes the INTOFFSET register to show
351 * what looks like the logical-or of the two interrupt numbers.
352 *
353 * Thanks to Klaus, Shannon, et al for helping to debug this problem
354 */
355 offset = readl_relaxed(intc->reg_intpnd + 4);
356
357 /* Find the bit manually, when the offset is wrong.
358 * The pending register only ever contains the one bit of the next
359 * interrupt to handle.
360 */
361 if (!(pnd & (1 << offset)))
362 offset = __ffs(pnd);
363
364 handle_domain_irq(intc->domain, intc_offset + offset, regs);
365 return true;
366 }
367
s3c24xx_handle_irq(struct pt_regs * regs)368 asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs)
369 {
370 do {
371 /*
372 * For platform based machines, neither ERR nor NULL can happen here.
373 * The s3c24xx_handle_irq() will be set as IRQ handler iff this succeeds:
374 *
375 * s3c_intc[0] = s3c24xx_init_intc()
376 *
377 * If this fails, the next calls to s3c24xx_init_intc() won't be executed.
378 *
379 * For DT machine, s3c_init_intc_of() could set the IRQ handler without
380 * setting s3c_intc[0] only if it was called with num_ctrl=0. There is no
381 * such code path, so again the s3c_intc[0] will have a valid pointer if
382 * set_handle_irq() is called.
383 *
384 * Therefore in s3c24xx_handle_irq(), the s3c_intc[0] is always something.
385 */
386 if (s3c24xx_handle_intc(s3c_intc[0], regs, 0))
387 continue;
388
389 if (!IS_ERR_OR_NULL(s3c_intc[2]))
390 if (s3c24xx_handle_intc(s3c_intc[2], regs, 64))
391 continue;
392
393 break;
394 } while (1);
395 }
396
397 #ifdef CONFIG_FIQ
398 /**
399 * s3c24xx_set_fiq - set the FIQ routing
400 * @irq: IRQ number to route to FIQ on processor.
401 * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
402 *
403 * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
404 * @on is true, the @irq is checked to see if it can be routed and the
405 * interrupt controller updated to route the IRQ. If @on is false, the FIQ
406 * routing is cleared, regardless of which @irq is specified.
407 */
s3c24xx_set_fiq(unsigned int irq,bool on)408 int s3c24xx_set_fiq(unsigned int irq, bool on)
409 {
410 u32 intmod;
411 unsigned offs;
412
413 if (on) {
414 offs = irq - FIQ_START;
415 if (offs > 31)
416 return -EINVAL;
417
418 intmod = 1 << offs;
419 } else {
420 intmod = 0;
421 }
422
423 writel_relaxed(intmod, S3C2410_INTMOD);
424 return 0;
425 }
426
427 EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
428 #endif
429
s3c24xx_irq_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)430 static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
431 irq_hw_number_t hw)
432 {
433 struct s3c_irq_intc *intc = h->host_data;
434 struct s3c_irq_data *irq_data = &intc->irqs[hw];
435 struct s3c_irq_intc *parent_intc;
436 struct s3c_irq_data *parent_irq_data;
437 unsigned int irqno;
438
439 /* attach controller pointer to irq_data */
440 irq_data->intc = intc;
441 irq_data->offset = hw;
442
443 parent_intc = intc->parent;
444
445 /* set handler and flags */
446 switch (irq_data->type) {
447 case S3C_IRQTYPE_NONE:
448 return 0;
449 case S3C_IRQTYPE_EINT:
450 /* On the S3C2412, the EINT0to3 have a parent irq
451 * but need the s3c_irq_eint0t4 chip
452 */
453 if (parent_intc && (!soc_is_s3c2412() || hw >= 4))
454 irq_set_chip_and_handler(virq, &s3c_irqext_chip,
455 handle_edge_irq);
456 else
457 irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
458 handle_edge_irq);
459 break;
460 case S3C_IRQTYPE_EDGE:
461 if (parent_intc || intc->reg_pending == S3C2416_SRCPND2)
462 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
463 handle_edge_irq);
464 else
465 irq_set_chip_and_handler(virq, &s3c_irq_chip,
466 handle_edge_irq);
467 break;
468 case S3C_IRQTYPE_LEVEL:
469 if (parent_intc)
470 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
471 handle_level_irq);
472 else
473 irq_set_chip_and_handler(virq, &s3c_irq_chip,
474 handle_level_irq);
475 break;
476 default:
477 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
478 return -EINVAL;
479 }
480
481 irq_set_chip_data(virq, irq_data);
482
483 if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) {
484 if (irq_data->parent_irq > 31) {
485 pr_err("irq-s3c24xx: parent irq %lu is out of range\n",
486 irq_data->parent_irq);
487 return -EINVAL;
488 }
489
490 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
491 parent_irq_data->sub_intc = intc;
492 parent_irq_data->sub_bits |= (1UL << hw);
493
494 /* attach the demuxer to the parent irq */
495 irqno = irq_find_mapping(parent_intc->domain,
496 irq_data->parent_irq);
497 if (!irqno) {
498 pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
499 irq_data->parent_irq);
500 return -EINVAL;
501 }
502 irq_set_chained_handler(irqno, s3c_irq_demux);
503 }
504
505 return 0;
506 }
507
508 static const struct irq_domain_ops s3c24xx_irq_ops = {
509 .map = s3c24xx_irq_map,
510 .xlate = irq_domain_xlate_twocell,
511 };
512
s3c24xx_clear_intc(struct s3c_irq_intc * intc)513 static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
514 {
515 void __iomem *reg_source;
516 unsigned long pend;
517 unsigned long last;
518 int i;
519
520 /* if intpnd is set, read the next pending irq from there */
521 reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
522
523 last = 0;
524 for (i = 0; i < 4; i++) {
525 pend = readl_relaxed(reg_source);
526
527 if (pend == 0 || pend == last)
528 break;
529
530 writel_relaxed(pend, intc->reg_pending);
531 if (intc->reg_intpnd)
532 writel_relaxed(pend, intc->reg_intpnd);
533
534 pr_info("irq: clearing pending status %08x\n", (int)pend);
535 last = pend;
536 }
537 }
538
s3c24xx_init_intc(struct device_node * np,struct s3c_irq_data * irq_data,struct s3c_irq_intc * parent,unsigned long address)539 static struct s3c_irq_intc * __init s3c24xx_init_intc(struct device_node *np,
540 struct s3c_irq_data *irq_data,
541 struct s3c_irq_intc *parent,
542 unsigned long address)
543 {
544 struct s3c_irq_intc *intc;
545 void __iomem *base = (void *)0xf6000000; /* static mapping */
546 int irq_num;
547 int irq_start;
548 int ret;
549
550 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
551 if (!intc)
552 return ERR_PTR(-ENOMEM);
553
554 intc->irqs = irq_data;
555
556 if (parent)
557 intc->parent = parent;
558
559 /* select the correct data for the controller.
560 * Need to hard code the irq num start and offset
561 * to preserve the static mapping for now
562 */
563 switch (address) {
564 case 0x4a000000:
565 pr_debug("irq: found main intc\n");
566 intc->reg_pending = base;
567 intc->reg_mask = base + 0x08;
568 intc->reg_intpnd = base + 0x10;
569 irq_num = 32;
570 irq_start = S3C2410_IRQ(0);
571 break;
572 case 0x4a000018:
573 pr_debug("irq: found subintc\n");
574 intc->reg_pending = base + 0x18;
575 intc->reg_mask = base + 0x1c;
576 irq_num = 29;
577 irq_start = S3C2410_IRQSUB(0);
578 break;
579 case 0x4a000040:
580 pr_debug("irq: found intc2\n");
581 intc->reg_pending = base + 0x40;
582 intc->reg_mask = base + 0x48;
583 intc->reg_intpnd = base + 0x50;
584 irq_num = 8;
585 irq_start = S3C2416_IRQ(0);
586 break;
587 case 0x560000a4:
588 pr_debug("irq: found eintc\n");
589 base = (void *)0xfd000000;
590
591 intc->reg_mask = base + 0xa4;
592 intc->reg_pending = base + 0xa8;
593 irq_num = 24;
594 irq_start = S3C2410_IRQ(32);
595 break;
596 default:
597 pr_err("irq: unsupported controller address\n");
598 ret = -EINVAL;
599 goto err;
600 }
601
602 /* now that all the data is complete, init the irq-domain */
603 s3c24xx_clear_intc(intc);
604 intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
605 0, &s3c24xx_irq_ops,
606 intc);
607 if (!intc->domain) {
608 pr_err("irq: could not create irq-domain\n");
609 ret = -EINVAL;
610 goto err;
611 }
612
613 set_handle_irq(s3c24xx_handle_irq);
614
615 return intc;
616
617 err:
618 kfree(intc);
619 return ERR_PTR(ret);
620 }
621
622 static struct s3c_irq_data __maybe_unused init_eint[32] = {
623 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
624 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
625 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
626 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
627 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
628 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
629 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
630 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
631 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
632 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
633 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
634 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
635 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
636 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
637 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
638 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
639 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
640 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
641 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
642 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
643 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
644 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
645 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
646 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
647 };
648
649 #ifdef CONFIG_CPU_S3C2410
650 static struct s3c_irq_data init_s3c2410base[32] = {
651 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
652 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
653 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
654 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
655 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
656 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
657 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
658 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
659 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
660 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
661 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
662 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
663 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
664 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
665 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
666 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
667 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
668 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
669 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
670 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
671 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
672 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
673 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
674 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
675 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
676 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
677 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
678 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
679 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
680 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
681 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
682 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
683 };
684
685 static struct s3c_irq_data init_s3c2410subint[32] = {
686 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
687 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
688 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
689 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
690 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
691 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
692 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
693 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
694 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
695 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
696 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
697 };
698
s3c2410_init_irq(void)699 void __init s3c2410_init_irq(void)
700 {
701 #ifdef CONFIG_FIQ
702 init_FIQ(FIQ_START);
703 #endif
704
705 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL,
706 0x4a000000);
707 if (IS_ERR(s3c_intc[0])) {
708 pr_err("irq: could not create main interrupt controller\n");
709 return;
710 }
711
712 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0],
713 s3c_intc[0], 0x4a000018);
714 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
715 }
716 #endif
717
718 #ifdef CONFIG_CPU_S3C2412
719 static struct s3c_irq_data init_s3c2412base[32] = {
720 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */
721 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */
722 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */
723 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */
724 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
725 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
726 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
727 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
728 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
729 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
730 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
731 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
732 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
733 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
734 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
735 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
736 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
737 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
738 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
739 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
740 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
741 { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */
742 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
743 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
744 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
745 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
746 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
747 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
748 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
749 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
750 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
751 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
752 };
753
754 static struct s3c_irq_data init_s3c2412eint[32] = {
755 { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */
756 { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */
757 { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */
758 { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */
759 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
760 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
761 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
762 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
763 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
764 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
765 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
766 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
767 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
768 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
769 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
770 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
771 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
772 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
773 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
774 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
775 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
776 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
777 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
778 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
779 };
780
781 static struct s3c_irq_data init_s3c2412subint[32] = {
782 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
783 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
784 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
785 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
786 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
787 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
788 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
789 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
790 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
791 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
792 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
793 { .type = S3C_IRQTYPE_NONE, },
794 { .type = S3C_IRQTYPE_NONE, },
795 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */
796 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */
797 };
798
s3c2412_init_irq(void)799 void __init s3c2412_init_irq(void)
800 {
801 pr_info("S3C2412: IRQ Support\n");
802
803 #ifdef CONFIG_FIQ
804 init_FIQ(FIQ_START);
805 #endif
806
807 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL,
808 0x4a000000);
809 if (IS_ERR(s3c_intc[0])) {
810 pr_err("irq: could not create main interrupt controller\n");
811 return;
812 }
813
814 s3c24xx_init_intc(NULL, &init_s3c2412eint[0], s3c_intc[0], 0x560000a4);
815 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2412subint[0],
816 s3c_intc[0], 0x4a000018);
817 }
818 #endif
819
820 #ifdef CONFIG_CPU_S3C2416
821 static struct s3c_irq_data init_s3c2416base[32] = {
822 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
823 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
824 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
825 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
826 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
827 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
828 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
829 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
830 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
831 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
832 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
833 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
834 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
835 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
836 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
837 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
838 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
839 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
840 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
841 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
842 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
843 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
844 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
845 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
846 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
847 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
848 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
849 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
850 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
851 { .type = S3C_IRQTYPE_NONE, },
852 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
853 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
854 };
855
856 static struct s3c_irq_data init_s3c2416subint[32] = {
857 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
858 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
859 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
860 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
861 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
862 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
863 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
864 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
865 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
866 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
867 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
868 { .type = S3C_IRQTYPE_NONE }, /* reserved */
869 { .type = S3C_IRQTYPE_NONE }, /* reserved */
870 { .type = S3C_IRQTYPE_NONE }, /* reserved */
871 { .type = S3C_IRQTYPE_NONE }, /* reserved */
872 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
873 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
874 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
875 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
876 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
877 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
878 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
879 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
880 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
881 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
882 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
883 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
884 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
885 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
886 };
887
888 static struct s3c_irq_data init_s3c2416_second[32] = {
889 { .type = S3C_IRQTYPE_EDGE }, /* 2D */
890 { .type = S3C_IRQTYPE_NONE }, /* reserved */
891 { .type = S3C_IRQTYPE_NONE }, /* reserved */
892 { .type = S3C_IRQTYPE_NONE }, /* reserved */
893 { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
894 { .type = S3C_IRQTYPE_NONE }, /* reserved */
895 { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
896 };
897
s3c2416_init_irq(void)898 void __init s3c2416_init_irq(void)
899 {
900 pr_info("S3C2416: IRQ Support\n");
901
902 #ifdef CONFIG_FIQ
903 init_FIQ(FIQ_START);
904 #endif
905
906 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL,
907 0x4a000000);
908 if (IS_ERR(s3c_intc[0])) {
909 pr_err("irq: could not create main interrupt controller\n");
910 return;
911 }
912
913 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
914 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0],
915 s3c_intc[0], 0x4a000018);
916
917 s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0],
918 NULL, 0x4a000040);
919 }
920
921 #endif
922
923 #ifdef CONFIG_CPU_S3C2440
924 static struct s3c_irq_data init_s3c2440base[32] = {
925 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
926 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
927 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
928 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
929 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
930 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
931 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
932 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
933 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
934 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
935 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
936 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
937 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
938 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
939 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
940 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
941 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
942 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
943 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
944 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
945 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
946 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
947 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
948 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
949 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
950 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
951 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
952 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
953 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
954 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
955 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
956 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
957 };
958
959 static struct s3c_irq_data init_s3c2440subint[32] = {
960 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
961 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
962 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
963 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
964 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
965 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
966 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
967 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
968 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
969 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
970 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
971 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
972 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
973 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
974 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
975 };
976
s3c2440_init_irq(void)977 void __init s3c2440_init_irq(void)
978 {
979 pr_info("S3C2440: IRQ Support\n");
980
981 #ifdef CONFIG_FIQ
982 init_FIQ(FIQ_START);
983 #endif
984
985 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL,
986 0x4a000000);
987 if (IS_ERR(s3c_intc[0])) {
988 pr_err("irq: could not create main interrupt controller\n");
989 return;
990 }
991
992 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
993 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2440subint[0],
994 s3c_intc[0], 0x4a000018);
995 }
996 #endif
997
998 #ifdef CONFIG_CPU_S3C2442
999 static struct s3c_irq_data init_s3c2442base[32] = {
1000 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
1001 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
1002 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
1003 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
1004 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
1005 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
1006 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
1007 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
1008 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
1009 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
1010 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
1011 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
1012 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
1013 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
1014 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
1015 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
1016 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
1017 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
1018 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
1019 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
1020 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
1021 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
1022 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1023 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1024 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
1025 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1026 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1027 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1028 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1029 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1030 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1031 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
1032 };
1033
1034 static struct s3c_irq_data init_s3c2442subint[32] = {
1035 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1036 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1037 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1038 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1039 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1040 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1041 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1042 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1043 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1044 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1045 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1046 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1047 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1048 };
1049
s3c2442_init_irq(void)1050 void __init s3c2442_init_irq(void)
1051 {
1052 pr_info("S3C2442: IRQ Support\n");
1053
1054 #ifdef CONFIG_FIQ
1055 init_FIQ(FIQ_START);
1056 #endif
1057
1058 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL,
1059 0x4a000000);
1060 if (IS_ERR(s3c_intc[0])) {
1061 pr_err("irq: could not create main interrupt controller\n");
1062 return;
1063 }
1064
1065 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
1066 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2442subint[0],
1067 s3c_intc[0], 0x4a000018);
1068 }
1069 #endif
1070
1071 #ifdef CONFIG_CPU_S3C2443
1072 static struct s3c_irq_data init_s3c2443base[32] = {
1073 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
1074 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
1075 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
1076 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
1077 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
1078 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
1079 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
1080 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
1081 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
1082 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
1083 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
1084 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
1085 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
1086 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
1087 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
1088 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
1089 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
1090 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
1091 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
1092 { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
1093 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
1094 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
1095 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1096 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1097 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
1098 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1099 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1100 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1101 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1102 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1103 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1104 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
1105 };
1106
1107
1108 static struct s3c_irq_data init_s3c2443subint[32] = {
1109 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1110 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1111 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1112 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1113 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1114 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1115 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1116 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1117 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1118 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1119 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1120 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1121 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1122 { .type = S3C_IRQTYPE_NONE }, /* reserved */
1123 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
1124 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
1125 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
1126 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
1127 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
1128 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
1129 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
1130 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
1131 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
1132 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
1133 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
1134 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
1135 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
1136 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
1137 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
1138 };
1139
s3c2443_init_irq(void)1140 void __init s3c2443_init_irq(void)
1141 {
1142 pr_info("S3C2443: IRQ Support\n");
1143
1144 #ifdef CONFIG_FIQ
1145 init_FIQ(FIQ_START);
1146 #endif
1147
1148 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL,
1149 0x4a000000);
1150 if (IS_ERR(s3c_intc[0])) {
1151 pr_err("irq: could not create main interrupt controller\n");
1152 return;
1153 }
1154
1155 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
1156 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2443subint[0],
1157 s3c_intc[0], 0x4a000018);
1158 }
1159 #endif
1160
1161 #ifdef CONFIG_OF
s3c24xx_irq_map_of(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)1162 static int s3c24xx_irq_map_of(struct irq_domain *h, unsigned int virq,
1163 irq_hw_number_t hw)
1164 {
1165 unsigned int ctrl_num = hw / 32;
1166 unsigned int intc_hw = hw % 32;
1167 struct s3c_irq_intc *intc = s3c_intc[ctrl_num];
1168 struct s3c_irq_intc *parent_intc = intc->parent;
1169 struct s3c_irq_data *irq_data = &intc->irqs[intc_hw];
1170
1171 /* attach controller pointer to irq_data */
1172 irq_data->intc = intc;
1173 irq_data->offset = intc_hw;
1174
1175 if (!parent_intc)
1176 irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_edge_irq);
1177 else
1178 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
1179 handle_edge_irq);
1180
1181 irq_set_chip_data(virq, irq_data);
1182
1183 return 0;
1184 }
1185
1186 /* Translate our of irq notation
1187 * format: <ctrl_num ctrl_irq parent_irq type>
1188 */
s3c24xx_irq_xlate_of(struct irq_domain * d,struct device_node * n,const u32 * intspec,unsigned int intsize,irq_hw_number_t * out_hwirq,unsigned int * out_type)1189 static int s3c24xx_irq_xlate_of(struct irq_domain *d, struct device_node *n,
1190 const u32 *intspec, unsigned int intsize,
1191 irq_hw_number_t *out_hwirq, unsigned int *out_type)
1192 {
1193 struct s3c_irq_intc *intc;
1194 struct s3c_irq_intc *parent_intc;
1195 struct s3c_irq_data *irq_data;
1196 struct s3c_irq_data *parent_irq_data;
1197 int irqno;
1198
1199 if (WARN_ON(intsize < 4))
1200 return -EINVAL;
1201
1202 if (intspec[0] > 2 || !s3c_intc[intspec[0]]) {
1203 pr_err("controller number %d invalid\n", intspec[0]);
1204 return -EINVAL;
1205 }
1206 intc = s3c_intc[intspec[0]];
1207
1208 *out_hwirq = intspec[0] * 32 + intspec[2];
1209 *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
1210
1211 parent_intc = intc->parent;
1212 if (parent_intc) {
1213 irq_data = &intc->irqs[intspec[2]];
1214 irq_data->parent_irq = intspec[1];
1215 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
1216 parent_irq_data->sub_intc = intc;
1217 parent_irq_data->sub_bits |= (1UL << intspec[2]);
1218
1219 /* parent_intc is always s3c_intc[0], so no offset */
1220 irqno = irq_create_mapping(parent_intc->domain, intspec[1]);
1221 if (irqno < 0) {
1222 pr_err("irq: could not map parent interrupt\n");
1223 return irqno;
1224 }
1225
1226 irq_set_chained_handler(irqno, s3c_irq_demux);
1227 }
1228
1229 return 0;
1230 }
1231
1232 static const struct irq_domain_ops s3c24xx_irq_ops_of = {
1233 .map = s3c24xx_irq_map_of,
1234 .xlate = s3c24xx_irq_xlate_of,
1235 };
1236
1237 struct s3c24xx_irq_of_ctrl {
1238 char *name;
1239 unsigned long offset;
1240 struct s3c_irq_intc **handle;
1241 struct s3c_irq_intc **parent;
1242 struct irq_domain_ops *ops;
1243 };
1244
s3c_init_intc_of(struct device_node * np,struct device_node * interrupt_parent,struct s3c24xx_irq_of_ctrl * s3c_ctrl,int num_ctrl)1245 static int __init s3c_init_intc_of(struct device_node *np,
1246 struct device_node *interrupt_parent,
1247 struct s3c24xx_irq_of_ctrl *s3c_ctrl, int num_ctrl)
1248 {
1249 struct s3c_irq_intc *intc;
1250 struct s3c24xx_irq_of_ctrl *ctrl;
1251 struct irq_domain *domain;
1252 void __iomem *reg_base;
1253 int i;
1254
1255 reg_base = of_iomap(np, 0);
1256 if (!reg_base) {
1257 pr_err("irq-s3c24xx: could not map irq registers\n");
1258 return -EINVAL;
1259 }
1260
1261 domain = irq_domain_add_linear(np, num_ctrl * 32,
1262 &s3c24xx_irq_ops_of, NULL);
1263 if (!domain) {
1264 pr_err("irq: could not create irq-domain\n");
1265 return -EINVAL;
1266 }
1267
1268 for (i = 0; i < num_ctrl; i++) {
1269 ctrl = &s3c_ctrl[i];
1270
1271 pr_debug("irq: found controller %s\n", ctrl->name);
1272
1273 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
1274 if (!intc)
1275 return -ENOMEM;
1276
1277 intc->domain = domain;
1278 intc->irqs = kcalloc(32, sizeof(struct s3c_irq_data),
1279 GFP_KERNEL);
1280 if (!intc->irqs) {
1281 kfree(intc);
1282 return -ENOMEM;
1283 }
1284
1285 if (ctrl->parent) {
1286 intc->reg_pending = reg_base + ctrl->offset;
1287 intc->reg_mask = reg_base + ctrl->offset + 0x4;
1288
1289 if (*(ctrl->parent)) {
1290 intc->parent = *(ctrl->parent);
1291 } else {
1292 pr_warn("irq: parent of %s missing\n",
1293 ctrl->name);
1294 kfree(intc->irqs);
1295 kfree(intc);
1296 continue;
1297 }
1298 } else {
1299 intc->reg_pending = reg_base + ctrl->offset;
1300 intc->reg_mask = reg_base + ctrl->offset + 0x08;
1301 intc->reg_intpnd = reg_base + ctrl->offset + 0x10;
1302 }
1303
1304 s3c24xx_clear_intc(intc);
1305 s3c_intc[i] = intc;
1306 }
1307
1308 set_handle_irq(s3c24xx_handle_irq);
1309
1310 return 0;
1311 }
1312
1313 static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = {
1314 {
1315 .name = "intc",
1316 .offset = 0,
1317 }, {
1318 .name = "subintc",
1319 .offset = 0x18,
1320 .parent = &s3c_intc[0],
1321 }
1322 };
1323
s3c2410_init_intc_of(struct device_node * np,struct device_node * interrupt_parent)1324 int __init s3c2410_init_intc_of(struct device_node *np,
1325 struct device_node *interrupt_parent)
1326 {
1327 return s3c_init_intc_of(np, interrupt_parent,
1328 s3c2410_ctrl, ARRAY_SIZE(s3c2410_ctrl));
1329 }
1330 IRQCHIP_DECLARE(s3c2410_irq, "samsung,s3c2410-irq", s3c2410_init_intc_of);
1331
1332 static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = {
1333 {
1334 .name = "intc",
1335 .offset = 0,
1336 }, {
1337 .name = "subintc",
1338 .offset = 0x18,
1339 .parent = &s3c_intc[0],
1340 }, {
1341 .name = "intc2",
1342 .offset = 0x40,
1343 }
1344 };
1345
s3c2416_init_intc_of(struct device_node * np,struct device_node * interrupt_parent)1346 int __init s3c2416_init_intc_of(struct device_node *np,
1347 struct device_node *interrupt_parent)
1348 {
1349 return s3c_init_intc_of(np, interrupt_parent,
1350 s3c2416_ctrl, ARRAY_SIZE(s3c2416_ctrl));
1351 }
1352 IRQCHIP_DECLARE(s3c2416_irq, "samsung,s3c2416-irq", s3c2416_init_intc_of);
1353 #endif
1354