1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/err.h>
7 #include <linux/init.h>
8 #include <linux/irq.h>
9 #include <linux/irqchip.h>
10 #include <linux/irqdomain.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/of.h>
14 #include <linux/of_address.h>
15 #include <linux/of_device.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/types.h>
20
21 #define PDC_MAX_IRQS 126
22
23 #define CLEAR_INTR(reg, intr) (reg & ~(1 << intr))
24 #define ENABLE_INTR(reg, intr) (reg | (1 << intr))
25
26 #define IRQ_ENABLE_BANK 0x10
27 #define IRQ_i_CFG 0x110
28
29 struct pdc_pin_region {
30 u32 pin_base;
31 u32 parent_base;
32 u32 cnt;
33 };
34
35 static DEFINE_RAW_SPINLOCK(pdc_lock);
36 static void __iomem *pdc_base;
37 static struct pdc_pin_region *pdc_region;
38 static int pdc_region_cnt;
39
pdc_reg_write(int reg,u32 i,u32 val)40 static void pdc_reg_write(int reg, u32 i, u32 val)
41 {
42 writel_relaxed(val, pdc_base + reg + i * sizeof(u32));
43 }
44
pdc_reg_read(int reg,u32 i)45 static u32 pdc_reg_read(int reg, u32 i)
46 {
47 return readl_relaxed(pdc_base + reg + i * sizeof(u32));
48 }
49
pdc_enable_intr(struct irq_data * d,bool on)50 static void pdc_enable_intr(struct irq_data *d, bool on)
51 {
52 int pin_out = d->hwirq;
53 unsigned long flags;
54 u32 index, mask;
55 u32 enable;
56
57 index = pin_out / 32;
58 mask = pin_out % 32;
59
60 raw_spin_lock_irqsave(&pdc_lock, flags);
61 enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
62 enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);
63 pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
64 raw_spin_unlock_irqrestore(&pdc_lock, flags);
65 }
66
qcom_pdc_gic_mask(struct irq_data * d)67 static void qcom_pdc_gic_mask(struct irq_data *d)
68 {
69 pdc_enable_intr(d, false);
70 irq_chip_mask_parent(d);
71 }
72
qcom_pdc_gic_unmask(struct irq_data * d)73 static void qcom_pdc_gic_unmask(struct irq_data *d)
74 {
75 pdc_enable_intr(d, true);
76 irq_chip_unmask_parent(d);
77 }
78
79 /*
80 * GIC does not handle falling edge or active low. To allow falling edge and
81 * active low interrupts to be handled at GIC, PDC has an inverter that inverts
82 * falling edge into a rising edge and active low into an active high.
83 * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to
84 * set as per the table below.
85 * Level sensitive active low LOW
86 * Rising edge sensitive NOT USED
87 * Falling edge sensitive LOW
88 * Dual Edge sensitive NOT USED
89 * Level sensitive active High HIGH
90 * Falling Edge sensitive NOT USED
91 * Rising edge sensitive HIGH
92 * Dual Edge sensitive HIGH
93 */
94 enum pdc_irq_config_bits {
95 PDC_LEVEL_LOW = 0b000,
96 PDC_EDGE_FALLING = 0b010,
97 PDC_LEVEL_HIGH = 0b100,
98 PDC_EDGE_RISING = 0b110,
99 PDC_EDGE_DUAL = 0b111,
100 };
101
102 /**
103 * qcom_pdc_gic_set_type: Configure PDC for the interrupt
104 *
105 * @d: the interrupt data
106 * @type: the interrupt type
107 *
108 * If @type is edge triggered, forward that as Rising edge as PDC
109 * takes care of converting falling edge to rising edge signal
110 * If @type is level, then forward that as level high as PDC
111 * takes care of converting falling edge to rising edge signal
112 */
qcom_pdc_gic_set_type(struct irq_data * d,unsigned int type)113 static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
114 {
115 int pin_out = d->hwirq;
116 enum pdc_irq_config_bits pdc_type;
117
118 switch (type) {
119 case IRQ_TYPE_EDGE_RISING:
120 pdc_type = PDC_EDGE_RISING;
121 break;
122 case IRQ_TYPE_EDGE_FALLING:
123 pdc_type = PDC_EDGE_FALLING;
124 type = IRQ_TYPE_EDGE_RISING;
125 break;
126 case IRQ_TYPE_EDGE_BOTH:
127 pdc_type = PDC_EDGE_DUAL;
128 type = IRQ_TYPE_EDGE_RISING;
129 break;
130 case IRQ_TYPE_LEVEL_HIGH:
131 pdc_type = PDC_LEVEL_HIGH;
132 break;
133 case IRQ_TYPE_LEVEL_LOW:
134 pdc_type = PDC_LEVEL_LOW;
135 type = IRQ_TYPE_LEVEL_HIGH;
136 break;
137 default:
138 WARN_ON(1);
139 return -EINVAL;
140 }
141
142 pdc_reg_write(IRQ_i_CFG, pin_out, pdc_type);
143
144 return irq_chip_set_type_parent(d, type);
145 }
146
147 static struct irq_chip qcom_pdc_gic_chip = {
148 .name = "PDC",
149 .irq_eoi = irq_chip_eoi_parent,
150 .irq_mask = qcom_pdc_gic_mask,
151 .irq_unmask = qcom_pdc_gic_unmask,
152 .irq_retrigger = irq_chip_retrigger_hierarchy,
153 .irq_set_type = qcom_pdc_gic_set_type,
154 .flags = IRQCHIP_MASK_ON_SUSPEND |
155 IRQCHIP_SET_TYPE_MASKED |
156 IRQCHIP_SKIP_SET_WAKE,
157 .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
158 .irq_set_affinity = irq_chip_set_affinity_parent,
159 };
160
get_parent_hwirq(int pin)161 static irq_hw_number_t get_parent_hwirq(int pin)
162 {
163 int i;
164 struct pdc_pin_region *region;
165
166 for (i = 0; i < pdc_region_cnt; i++) {
167 region = &pdc_region[i];
168 if (pin >= region->pin_base &&
169 pin < region->pin_base + region->cnt)
170 return (region->parent_base + pin - region->pin_base);
171 }
172
173 WARN_ON(1);
174 return ~0UL;
175 }
176
qcom_pdc_translate(struct irq_domain * d,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)177 static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
178 unsigned long *hwirq, unsigned int *type)
179 {
180 if (is_of_node(fwspec->fwnode)) {
181 if (fwspec->param_count != 2)
182 return -EINVAL;
183
184 *hwirq = fwspec->param[0];
185 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
186 return 0;
187 }
188
189 return -EINVAL;
190 }
191
qcom_pdc_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * data)192 static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
193 unsigned int nr_irqs, void *data)
194 {
195 struct irq_fwspec *fwspec = data;
196 struct irq_fwspec parent_fwspec;
197 irq_hw_number_t hwirq, parent_hwirq;
198 unsigned int type;
199 int ret;
200
201 ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
202 if (ret)
203 return -EINVAL;
204
205 parent_hwirq = get_parent_hwirq(hwirq);
206 if (parent_hwirq == ~0UL)
207 return -EINVAL;
208
209 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
210 &qcom_pdc_gic_chip, NULL);
211 if (ret)
212 return ret;
213
214 if (type & IRQ_TYPE_EDGE_BOTH)
215 type = IRQ_TYPE_EDGE_RISING;
216
217 if (type & IRQ_TYPE_LEVEL_MASK)
218 type = IRQ_TYPE_LEVEL_HIGH;
219
220 parent_fwspec.fwnode = domain->parent->fwnode;
221 parent_fwspec.param_count = 3;
222 parent_fwspec.param[0] = 0;
223 parent_fwspec.param[1] = parent_hwirq;
224 parent_fwspec.param[2] = type;
225
226 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
227 &parent_fwspec);
228 }
229
230 static const struct irq_domain_ops qcom_pdc_ops = {
231 .translate = qcom_pdc_translate,
232 .alloc = qcom_pdc_alloc,
233 .free = irq_domain_free_irqs_common,
234 };
235
pdc_setup_pin_mapping(struct device_node * np)236 static int pdc_setup_pin_mapping(struct device_node *np)
237 {
238 int ret, n;
239
240 n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));
241 if (n <= 0 || n % 3)
242 return -EINVAL;
243
244 pdc_region_cnt = n / 3;
245 pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL);
246 if (!pdc_region) {
247 pdc_region_cnt = 0;
248 return -ENOMEM;
249 }
250
251 for (n = 0; n < pdc_region_cnt; n++) {
252 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
253 n * 3 + 0,
254 &pdc_region[n].pin_base);
255 if (ret)
256 return ret;
257 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
258 n * 3 + 1,
259 &pdc_region[n].parent_base);
260 if (ret)
261 return ret;
262 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
263 n * 3 + 2,
264 &pdc_region[n].cnt);
265 if (ret)
266 return ret;
267 }
268
269 return 0;
270 }
271
qcom_pdc_init(struct device_node * node,struct device_node * parent)272 static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
273 {
274 struct irq_domain *parent_domain, *pdc_domain;
275 int ret;
276
277 pdc_base = of_iomap(node, 0);
278 if (!pdc_base) {
279 pr_err("%pOF: unable to map PDC registers\n", node);
280 return -ENXIO;
281 }
282
283 parent_domain = irq_find_host(parent);
284 if (!parent_domain) {
285 pr_err("%pOF: unable to find PDC's parent domain\n", node);
286 ret = -ENXIO;
287 goto fail;
288 }
289
290 ret = pdc_setup_pin_mapping(node);
291 if (ret) {
292 pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);
293 goto fail;
294 }
295
296 pdc_domain = irq_domain_create_hierarchy(parent_domain, 0, PDC_MAX_IRQS,
297 of_fwnode_handle(node),
298 &qcom_pdc_ops, NULL);
299 if (!pdc_domain) {
300 pr_err("%pOF: GIC domain add failed\n", node);
301 ret = -ENOMEM;
302 goto fail;
303 }
304
305 return 0;
306
307 fail:
308 kfree(pdc_region);
309 iounmap(pdc_base);
310 return ret;
311 }
312
313 IRQCHIP_DECLARE(pdc_sdm845, "qcom,sdm845-pdc", qcom_pdc_init);
314