1 /* $Id: avm_pci.c,v 1.29.2.4 2004/02/11 13:21:32 keil Exp $
2 *
3 * low level stuff for AVM Fritz!PCI and ISA PnP isdn cards
4 *
5 * Author Karsten Keil
6 * Copyright by Karsten Keil <keil@isdn4linux.de>
7 *
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
10 *
11 * Thanks to AVM, Berlin for information
12 *
13 */
14
15 #include <linux/init.h>
16 #include "hisax.h"
17 #include "isac.h"
18 #include "isdnl1.h"
19 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/isapnp.h>
22 #include <linux/interrupt.h>
23
24 static const char *avm_pci_rev = "$Revision: 1.29.2.4 $";
25
26 #define AVM_FRITZ_PCI 1
27 #define AVM_FRITZ_PNP 2
28
29 #define HDLC_FIFO 0x0
30 #define HDLC_STATUS 0x4
31
32 #define AVM_HDLC_1 0x00
33 #define AVM_HDLC_2 0x01
34 #define AVM_ISAC_FIFO 0x02
35 #define AVM_ISAC_REG_LOW 0x04
36 #define AVM_ISAC_REG_HIGH 0x06
37
38 #define AVM_STATUS0_IRQ_ISAC 0x01
39 #define AVM_STATUS0_IRQ_HDLC 0x02
40 #define AVM_STATUS0_IRQ_TIMER 0x04
41 #define AVM_STATUS0_IRQ_MASK 0x07
42
43 #define AVM_STATUS0_RESET 0x01
44 #define AVM_STATUS0_DIS_TIMER 0x02
45 #define AVM_STATUS0_RES_TIMER 0x04
46 #define AVM_STATUS0_ENA_IRQ 0x08
47 #define AVM_STATUS0_TESTBIT 0x10
48
49 #define AVM_STATUS1_INT_SEL 0x0f
50 #define AVM_STATUS1_ENA_IOM 0x80
51
52 #define HDLC_MODE_ITF_FLG 0x01
53 #define HDLC_MODE_TRANS 0x02
54 #define HDLC_MODE_CCR_7 0x04
55 #define HDLC_MODE_CCR_16 0x08
56 #define HDLC_MODE_TESTLOOP 0x80
57
58 #define HDLC_INT_XPR 0x80
59 #define HDLC_INT_XDU 0x40
60 #define HDLC_INT_RPR 0x20
61 #define HDLC_INT_MASK 0xE0
62
63 #define HDLC_STAT_RME 0x01
64 #define HDLC_STAT_RDO 0x10
65 #define HDLC_STAT_CRCVFRRAB 0x0E
66 #define HDLC_STAT_CRCVFR 0x06
67 #define HDLC_STAT_RML_MASK 0x3f00
68
69 #define HDLC_CMD_XRS 0x80
70 #define HDLC_CMD_XME 0x01
71 #define HDLC_CMD_RRS 0x20
72 #define HDLC_CMD_XML_MASK 0x3f00
73
74
75 /* Interface functions */
76
77 static u_char
ReadISAC(struct IsdnCardState * cs,u_char offset)78 ReadISAC(struct IsdnCardState *cs, u_char offset)
79 {
80 register u_char idx = (offset > 0x2f) ? AVM_ISAC_REG_HIGH : AVM_ISAC_REG_LOW;
81 register u_char val;
82
83 outb(idx, cs->hw.avm.cfg_reg + 4);
84 val = inb(cs->hw.avm.isac + (offset & 0xf));
85 return (val);
86 }
87
88 static void
WriteISAC(struct IsdnCardState * cs,u_char offset,u_char value)89 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
90 {
91 register u_char idx = (offset > 0x2f) ? AVM_ISAC_REG_HIGH : AVM_ISAC_REG_LOW;
92
93 outb(idx, cs->hw.avm.cfg_reg + 4);
94 outb(value, cs->hw.avm.isac + (offset & 0xf));
95 }
96
97 static void
ReadISACfifo(struct IsdnCardState * cs,u_char * data,int size)98 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size)
99 {
100 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4);
101 insb(cs->hw.avm.isac, data, size);
102 }
103
104 static void
WriteISACfifo(struct IsdnCardState * cs,u_char * data,int size)105 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size)
106 {
107 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4);
108 outsb(cs->hw.avm.isac, data, size);
109 }
110
111 static inline u_int
ReadHDLCPCI(struct IsdnCardState * cs,int chan,u_char offset)112 ReadHDLCPCI(struct IsdnCardState *cs, int chan, u_char offset)
113 {
114 register u_int idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
115 register u_int val;
116
117 outl(idx, cs->hw.avm.cfg_reg + 4);
118 val = inl(cs->hw.avm.isac + offset);
119 return (val);
120 }
121
122 static inline void
WriteHDLCPCI(struct IsdnCardState * cs,int chan,u_char offset,u_int value)123 WriteHDLCPCI(struct IsdnCardState *cs, int chan, u_char offset, u_int value)
124 {
125 register u_int idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
126
127 outl(idx, cs->hw.avm.cfg_reg + 4);
128 outl(value, cs->hw.avm.isac + offset);
129 }
130
131 static inline u_char
ReadHDLCPnP(struct IsdnCardState * cs,int chan,u_char offset)132 ReadHDLCPnP(struct IsdnCardState *cs, int chan, u_char offset)
133 {
134 register u_char idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
135 register u_char val;
136
137 outb(idx, cs->hw.avm.cfg_reg + 4);
138 val = inb(cs->hw.avm.isac + offset);
139 return (val);
140 }
141
142 static inline void
WriteHDLCPnP(struct IsdnCardState * cs,int chan,u_char offset,u_char value)143 WriteHDLCPnP(struct IsdnCardState *cs, int chan, u_char offset, u_char value)
144 {
145 register u_char idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
146
147 outb(idx, cs->hw.avm.cfg_reg + 4);
148 outb(value, cs->hw.avm.isac + offset);
149 }
150
151 static u_char
ReadHDLC_s(struct IsdnCardState * cs,int chan,u_char offset)152 ReadHDLC_s(struct IsdnCardState *cs, int chan, u_char offset)
153 {
154 return (0xff & ReadHDLCPCI(cs, chan, offset));
155 }
156
157 static void
WriteHDLC_s(struct IsdnCardState * cs,int chan,u_char offset,u_char value)158 WriteHDLC_s(struct IsdnCardState *cs, int chan, u_char offset, u_char value)
159 {
160 WriteHDLCPCI(cs, chan, offset, value);
161 }
162
163 static inline
Sel_BCS(struct IsdnCardState * cs,int channel)164 struct BCState *Sel_BCS(struct IsdnCardState *cs, int channel)
165 {
166 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
167 return (&cs->bcs[0]);
168 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
169 return (&cs->bcs[1]);
170 else
171 return (NULL);
172 }
173
174 static void
write_ctrl(struct BCState * bcs,int which)175 write_ctrl(struct BCState *bcs, int which) {
176
177 if (bcs->cs->debug & L1_DEB_HSCX)
178 debugl1(bcs->cs, "hdlc %c wr%x ctrl %x",
179 'A' + bcs->channel, which, bcs->hw.hdlc.ctrl.ctrl);
180 if (bcs->cs->subtyp == AVM_FRITZ_PCI) {
181 WriteHDLCPCI(bcs->cs, bcs->channel, HDLC_STATUS, bcs->hw.hdlc.ctrl.ctrl);
182 } else {
183 if (which & 4)
184 WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS + 2,
185 bcs->hw.hdlc.ctrl.sr.mode);
186 if (which & 2)
187 WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS + 1,
188 bcs->hw.hdlc.ctrl.sr.xml);
189 if (which & 1)
190 WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS,
191 bcs->hw.hdlc.ctrl.sr.cmd);
192 }
193 }
194
195 static void
modehdlc(struct BCState * bcs,int mode,int bc)196 modehdlc(struct BCState *bcs, int mode, int bc)
197 {
198 struct IsdnCardState *cs = bcs->cs;
199 int hdlc = bcs->channel;
200
201 if (cs->debug & L1_DEB_HSCX)
202 debugl1(cs, "hdlc %c mode %d --> %d ichan %d --> %d",
203 'A' + hdlc, bcs->mode, mode, hdlc, bc);
204 bcs->hw.hdlc.ctrl.ctrl = 0;
205 switch (mode) {
206 case (-1): /* used for init */
207 bcs->mode = 1;
208 bcs->channel = bc;
209 bc = 0;
210 /* fall through */
211 case (L1_MODE_NULL):
212 if (bcs->mode == L1_MODE_NULL)
213 return;
214 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
215 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_TRANS;
216 write_ctrl(bcs, 5);
217 bcs->mode = L1_MODE_NULL;
218 bcs->channel = bc;
219 break;
220 case (L1_MODE_TRANS):
221 bcs->mode = mode;
222 bcs->channel = bc;
223 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
224 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_TRANS;
225 write_ctrl(bcs, 5);
226 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS;
227 write_ctrl(bcs, 1);
228 bcs->hw.hdlc.ctrl.sr.cmd = 0;
229 schedule_event(bcs, B_XMTBUFREADY);
230 break;
231 case (L1_MODE_HDLC):
232 bcs->mode = mode;
233 bcs->channel = bc;
234 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
235 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_ITF_FLG;
236 write_ctrl(bcs, 5);
237 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS;
238 write_ctrl(bcs, 1);
239 bcs->hw.hdlc.ctrl.sr.cmd = 0;
240 schedule_event(bcs, B_XMTBUFREADY);
241 break;
242 }
243 }
244
245 static inline void
hdlc_empty_fifo(struct BCState * bcs,int count)246 hdlc_empty_fifo(struct BCState *bcs, int count)
247 {
248 register u_int *ptr;
249 u_char *p;
250 u_char idx = bcs->channel ? AVM_HDLC_2 : AVM_HDLC_1;
251 int cnt = 0;
252 struct IsdnCardState *cs = bcs->cs;
253
254 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
255 debugl1(cs, "hdlc_empty_fifo %d", count);
256 if (bcs->hw.hdlc.rcvidx + count > HSCX_BUFMAX) {
257 if (cs->debug & L1_DEB_WARN)
258 debugl1(cs, "hdlc_empty_fifo: incoming packet too large");
259 return;
260 }
261 p = bcs->hw.hdlc.rcvbuf + bcs->hw.hdlc.rcvidx;
262 ptr = (u_int *)p;
263 bcs->hw.hdlc.rcvidx += count;
264 if (cs->subtyp == AVM_FRITZ_PCI) {
265 outl(idx, cs->hw.avm.cfg_reg + 4);
266 while (cnt < count) {
267 #ifdef __powerpc__
268 *ptr++ = in_be32((unsigned *)(cs->hw.avm.isac + _IO_BASE));
269 #else
270 *ptr++ = inl(cs->hw.avm.isac);
271 #endif /* __powerpc__ */
272 cnt += 4;
273 }
274 } else {
275 outb(idx, cs->hw.avm.cfg_reg + 4);
276 while (cnt < count) {
277 *p++ = inb(cs->hw.avm.isac);
278 cnt++;
279 }
280 }
281 if (cs->debug & L1_DEB_HSCX_FIFO) {
282 char *t = bcs->blog;
283
284 if (cs->subtyp == AVM_FRITZ_PNP)
285 p = (u_char *) ptr;
286 t += sprintf(t, "hdlc_empty_fifo %c cnt %d",
287 bcs->channel ? 'B' : 'A', count);
288 QuickHex(t, p, count);
289 debugl1(cs, "%s", bcs->blog);
290 }
291 }
292
293 static inline void
hdlc_fill_fifo(struct BCState * bcs)294 hdlc_fill_fifo(struct BCState *bcs)
295 {
296 struct IsdnCardState *cs = bcs->cs;
297 int count, cnt = 0;
298 int fifo_size = 32;
299 u_char *p;
300 u_int *ptr;
301
302 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
303 debugl1(cs, "hdlc_fill_fifo");
304 if (!bcs->tx_skb)
305 return;
306 if (bcs->tx_skb->len <= 0)
307 return;
308
309 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_XME;
310 if (bcs->tx_skb->len > fifo_size) {
311 count = fifo_size;
312 } else {
313 count = bcs->tx_skb->len;
314 if (bcs->mode != L1_MODE_TRANS)
315 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_XME;
316 }
317 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
318 debugl1(cs, "hdlc_fill_fifo %d/%u", count, bcs->tx_skb->len);
319 p = bcs->tx_skb->data;
320 ptr = (u_int *)p;
321 skb_pull(bcs->tx_skb, count);
322 bcs->tx_cnt -= count;
323 bcs->hw.hdlc.count += count;
324 bcs->hw.hdlc.ctrl.sr.xml = ((count == fifo_size) ? 0 : count);
325 write_ctrl(bcs, 3); /* sets the correct index too */
326 if (cs->subtyp == AVM_FRITZ_PCI) {
327 while (cnt < count) {
328 #ifdef __powerpc__
329 out_be32((unsigned *)(cs->hw.avm.isac + _IO_BASE), *ptr++);
330 #else
331 outl(*ptr++, cs->hw.avm.isac);
332 #endif /* __powerpc__ */
333 cnt += 4;
334 }
335 } else {
336 while (cnt < count) {
337 outb(*p++, cs->hw.avm.isac);
338 cnt++;
339 }
340 }
341 if (cs->debug & L1_DEB_HSCX_FIFO) {
342 char *t = bcs->blog;
343
344 if (cs->subtyp == AVM_FRITZ_PNP)
345 p = (u_char *) ptr;
346 t += sprintf(t, "hdlc_fill_fifo %c cnt %d",
347 bcs->channel ? 'B' : 'A', count);
348 QuickHex(t, p, count);
349 debugl1(cs, "%s", bcs->blog);
350 }
351 }
352
353 static void
HDLC_irq(struct BCState * bcs,u_int stat)354 HDLC_irq(struct BCState *bcs, u_int stat) {
355 int len;
356 struct sk_buff *skb;
357
358 if (bcs->cs->debug & L1_DEB_HSCX)
359 debugl1(bcs->cs, "ch%d stat %#x", bcs->channel, stat);
360 if (stat & HDLC_INT_RPR) {
361 if (stat & HDLC_STAT_RDO) {
362 if (bcs->cs->debug & L1_DEB_HSCX)
363 debugl1(bcs->cs, "RDO");
364 else
365 debugl1(bcs->cs, "ch%d stat %#x", bcs->channel, stat);
366 bcs->hw.hdlc.ctrl.sr.xml = 0;
367 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_RRS;
368 write_ctrl(bcs, 1);
369 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_RRS;
370 write_ctrl(bcs, 1);
371 bcs->hw.hdlc.rcvidx = 0;
372 } else {
373 if (!(len = (stat & HDLC_STAT_RML_MASK) >> 8))
374 len = 32;
375 hdlc_empty_fifo(bcs, len);
376 if ((stat & HDLC_STAT_RME) || (bcs->mode == L1_MODE_TRANS)) {
377 if (((stat & HDLC_STAT_CRCVFRRAB) == HDLC_STAT_CRCVFR) ||
378 (bcs->mode == L1_MODE_TRANS)) {
379 if (!(skb = dev_alloc_skb(bcs->hw.hdlc.rcvidx)))
380 printk(KERN_WARNING "HDLC: receive out of memory\n");
381 else {
382 skb_put_data(skb,
383 bcs->hw.hdlc.rcvbuf,
384 bcs->hw.hdlc.rcvidx);
385 skb_queue_tail(&bcs->rqueue, skb);
386 }
387 bcs->hw.hdlc.rcvidx = 0;
388 schedule_event(bcs, B_RCVBUFREADY);
389 } else {
390 if (bcs->cs->debug & L1_DEB_HSCX)
391 debugl1(bcs->cs, "invalid frame");
392 else
393 debugl1(bcs->cs, "ch%d invalid frame %#x", bcs->channel, stat);
394 bcs->hw.hdlc.rcvidx = 0;
395 }
396 }
397 }
398 }
399 if (stat & HDLC_INT_XDU) {
400 /* Here we lost an TX interrupt, so
401 * restart transmitting the whole frame.
402 */
403 if (bcs->tx_skb) {
404 skb_push(bcs->tx_skb, bcs->hw.hdlc.count);
405 bcs->tx_cnt += bcs->hw.hdlc.count;
406 bcs->hw.hdlc.count = 0;
407 if (bcs->cs->debug & L1_DEB_WARN)
408 debugl1(bcs->cs, "ch%d XDU", bcs->channel);
409 } else if (bcs->cs->debug & L1_DEB_WARN)
410 debugl1(bcs->cs, "ch%d XDU without skb", bcs->channel);
411 bcs->hw.hdlc.ctrl.sr.xml = 0;
412 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_XRS;
413 write_ctrl(bcs, 1);
414 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_XRS;
415 write_ctrl(bcs, 1);
416 hdlc_fill_fifo(bcs);
417 } else if (stat & HDLC_INT_XPR) {
418 if (bcs->tx_skb) {
419 if (bcs->tx_skb->len) {
420 hdlc_fill_fifo(bcs);
421 return;
422 } else {
423 if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
424 (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
425 u_long flags;
426 spin_lock_irqsave(&bcs->aclock, flags);
427 bcs->ackcnt += bcs->hw.hdlc.count;
428 spin_unlock_irqrestore(&bcs->aclock, flags);
429 schedule_event(bcs, B_ACKPENDING);
430 }
431 dev_kfree_skb_irq(bcs->tx_skb);
432 bcs->hw.hdlc.count = 0;
433 bcs->tx_skb = NULL;
434 }
435 }
436 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
437 bcs->hw.hdlc.count = 0;
438 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
439 hdlc_fill_fifo(bcs);
440 } else {
441 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
442 schedule_event(bcs, B_XMTBUFREADY);
443 }
444 }
445 }
446
447 static inline void
HDLC_irq_main(struct IsdnCardState * cs)448 HDLC_irq_main(struct IsdnCardState *cs)
449 {
450 u_int stat;
451 struct BCState *bcs;
452
453 if (cs->subtyp == AVM_FRITZ_PCI) {
454 stat = ReadHDLCPCI(cs, 0, HDLC_STATUS);
455 } else {
456 stat = ReadHDLCPnP(cs, 0, HDLC_STATUS);
457 if (stat & HDLC_INT_RPR)
458 stat |= (ReadHDLCPnP(cs, 0, HDLC_STATUS + 1)) << 8;
459 }
460 if (stat & HDLC_INT_MASK) {
461 if (!(bcs = Sel_BCS(cs, 0))) {
462 if (cs->debug)
463 debugl1(cs, "hdlc spurious channel 0 IRQ");
464 } else
465 HDLC_irq(bcs, stat);
466 }
467 if (cs->subtyp == AVM_FRITZ_PCI) {
468 stat = ReadHDLCPCI(cs, 1, HDLC_STATUS);
469 } else {
470 stat = ReadHDLCPnP(cs, 1, HDLC_STATUS);
471 if (stat & HDLC_INT_RPR)
472 stat |= (ReadHDLCPnP(cs, 1, HDLC_STATUS + 1)) << 8;
473 }
474 if (stat & HDLC_INT_MASK) {
475 if (!(bcs = Sel_BCS(cs, 1))) {
476 if (cs->debug)
477 debugl1(cs, "hdlc spurious channel 1 IRQ");
478 } else
479 HDLC_irq(bcs, stat);
480 }
481 }
482
483 static void
hdlc_l2l1(struct PStack * st,int pr,void * arg)484 hdlc_l2l1(struct PStack *st, int pr, void *arg)
485 {
486 struct BCState *bcs = st->l1.bcs;
487 struct sk_buff *skb = arg;
488 u_long flags;
489
490 switch (pr) {
491 case (PH_DATA | REQUEST):
492 spin_lock_irqsave(&bcs->cs->lock, flags);
493 if (bcs->tx_skb) {
494 skb_queue_tail(&bcs->squeue, skb);
495 } else {
496 bcs->tx_skb = skb;
497 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
498 bcs->hw.hdlc.count = 0;
499 bcs->cs->BC_Send_Data(bcs);
500 }
501 spin_unlock_irqrestore(&bcs->cs->lock, flags);
502 break;
503 case (PH_PULL | INDICATION):
504 spin_lock_irqsave(&bcs->cs->lock, flags);
505 if (bcs->tx_skb) {
506 printk(KERN_WARNING "hdlc_l2l1: this shouldn't happen\n");
507 } else {
508 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
509 bcs->tx_skb = skb;
510 bcs->hw.hdlc.count = 0;
511 bcs->cs->BC_Send_Data(bcs);
512 }
513 spin_unlock_irqrestore(&bcs->cs->lock, flags);
514 break;
515 case (PH_PULL | REQUEST):
516 if (!bcs->tx_skb) {
517 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
518 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
519 } else
520 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
521 break;
522 case (PH_ACTIVATE | REQUEST):
523 spin_lock_irqsave(&bcs->cs->lock, flags);
524 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
525 modehdlc(bcs, st->l1.mode, st->l1.bc);
526 spin_unlock_irqrestore(&bcs->cs->lock, flags);
527 l1_msg_b(st, pr, arg);
528 break;
529 case (PH_DEACTIVATE | REQUEST):
530 l1_msg_b(st, pr, arg);
531 break;
532 case (PH_DEACTIVATE | CONFIRM):
533 spin_lock_irqsave(&bcs->cs->lock, flags);
534 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
535 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
536 modehdlc(bcs, 0, st->l1.bc);
537 spin_unlock_irqrestore(&bcs->cs->lock, flags);
538 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
539 break;
540 }
541 }
542
543 static void
close_hdlcstate(struct BCState * bcs)544 close_hdlcstate(struct BCState *bcs)
545 {
546 modehdlc(bcs, 0, 0);
547 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
548 kfree(bcs->hw.hdlc.rcvbuf);
549 bcs->hw.hdlc.rcvbuf = NULL;
550 kfree(bcs->blog);
551 bcs->blog = NULL;
552 skb_queue_purge(&bcs->rqueue);
553 skb_queue_purge(&bcs->squeue);
554 if (bcs->tx_skb) {
555 dev_kfree_skb_any(bcs->tx_skb);
556 bcs->tx_skb = NULL;
557 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
558 }
559 }
560 }
561
562 static int
open_hdlcstate(struct IsdnCardState * cs,struct BCState * bcs)563 open_hdlcstate(struct IsdnCardState *cs, struct BCState *bcs)
564 {
565 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
566 if (!(bcs->hw.hdlc.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
567 printk(KERN_WARNING
568 "HiSax: No memory for hdlc.rcvbuf\n");
569 return (1);
570 }
571 if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
572 printk(KERN_WARNING
573 "HiSax: No memory for bcs->blog\n");
574 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
575 kfree(bcs->hw.hdlc.rcvbuf);
576 bcs->hw.hdlc.rcvbuf = NULL;
577 return (2);
578 }
579 skb_queue_head_init(&bcs->rqueue);
580 skb_queue_head_init(&bcs->squeue);
581 }
582 bcs->tx_skb = NULL;
583 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
584 bcs->event = 0;
585 bcs->hw.hdlc.rcvidx = 0;
586 bcs->tx_cnt = 0;
587 return (0);
588 }
589
590 static int
setstack_hdlc(struct PStack * st,struct BCState * bcs)591 setstack_hdlc(struct PStack *st, struct BCState *bcs)
592 {
593 bcs->channel = st->l1.bc;
594 if (open_hdlcstate(st->l1.hardware, bcs))
595 return (-1);
596 st->l1.bcs = bcs;
597 st->l2.l2l1 = hdlc_l2l1;
598 setstack_manager(st);
599 bcs->st = st;
600 setstack_l1_B(st);
601 return (0);
602 }
603
604 #if 0
605 void __init
606 clear_pending_hdlc_ints(struct IsdnCardState *cs)
607 {
608 u_int val;
609
610 if (cs->subtyp == AVM_FRITZ_PCI) {
611 val = ReadHDLCPCI(cs, 0, HDLC_STATUS);
612 debugl1(cs, "HDLC 1 STA %x", val);
613 val = ReadHDLCPCI(cs, 1, HDLC_STATUS);
614 debugl1(cs, "HDLC 2 STA %x", val);
615 } else {
616 val = ReadHDLCPnP(cs, 0, HDLC_STATUS);
617 debugl1(cs, "HDLC 1 STA %x", val);
618 val = ReadHDLCPnP(cs, 0, HDLC_STATUS + 1);
619 debugl1(cs, "HDLC 1 RML %x", val);
620 val = ReadHDLCPnP(cs, 0, HDLC_STATUS + 2);
621 debugl1(cs, "HDLC 1 MODE %x", val);
622 val = ReadHDLCPnP(cs, 0, HDLC_STATUS + 3);
623 debugl1(cs, "HDLC 1 VIN %x", val);
624 val = ReadHDLCPnP(cs, 1, HDLC_STATUS);
625 debugl1(cs, "HDLC 2 STA %x", val);
626 val = ReadHDLCPnP(cs, 1, HDLC_STATUS + 1);
627 debugl1(cs, "HDLC 2 RML %x", val);
628 val = ReadHDLCPnP(cs, 1, HDLC_STATUS + 2);
629 debugl1(cs, "HDLC 2 MODE %x", val);
630 val = ReadHDLCPnP(cs, 1, HDLC_STATUS + 3);
631 debugl1(cs, "HDLC 2 VIN %x", val);
632 }
633 }
634 #endif /* 0 */
635
636 static void
inithdlc(struct IsdnCardState * cs)637 inithdlc(struct IsdnCardState *cs)
638 {
639 cs->bcs[0].BC_SetStack = setstack_hdlc;
640 cs->bcs[1].BC_SetStack = setstack_hdlc;
641 cs->bcs[0].BC_Close = close_hdlcstate;
642 cs->bcs[1].BC_Close = close_hdlcstate;
643 modehdlc(cs->bcs, -1, 0);
644 modehdlc(cs->bcs + 1, -1, 1);
645 }
646
647 static irqreturn_t
avm_pcipnp_interrupt(int intno,void * dev_id)648 avm_pcipnp_interrupt(int intno, void *dev_id)
649 {
650 struct IsdnCardState *cs = dev_id;
651 u_long flags;
652 u_char val;
653 u_char sval;
654
655 spin_lock_irqsave(&cs->lock, flags);
656 sval = inb(cs->hw.avm.cfg_reg + 2);
657 if ((sval & AVM_STATUS0_IRQ_MASK) == AVM_STATUS0_IRQ_MASK) {
658 /* possible a shared IRQ reqest */
659 spin_unlock_irqrestore(&cs->lock, flags);
660 return IRQ_NONE;
661 }
662 if (!(sval & AVM_STATUS0_IRQ_ISAC)) {
663 val = ReadISAC(cs, ISAC_ISTA);
664 isac_interrupt(cs, val);
665 }
666 if (!(sval & AVM_STATUS0_IRQ_HDLC)) {
667 HDLC_irq_main(cs);
668 }
669 WriteISAC(cs, ISAC_MASK, 0xFF);
670 WriteISAC(cs, ISAC_MASK, 0x0);
671 spin_unlock_irqrestore(&cs->lock, flags);
672 return IRQ_HANDLED;
673 }
674
675 static void
reset_avmpcipnp(struct IsdnCardState * cs)676 reset_avmpcipnp(struct IsdnCardState *cs)
677 {
678 printk(KERN_INFO "AVM PCI/PnP: reset\n");
679 outb(AVM_STATUS0_RESET | AVM_STATUS0_DIS_TIMER, cs->hw.avm.cfg_reg + 2);
680 mdelay(10);
681 outb(AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER | AVM_STATUS0_ENA_IRQ, cs->hw.avm.cfg_reg + 2);
682 outb(AVM_STATUS1_ENA_IOM | cs->irq, cs->hw.avm.cfg_reg + 3);
683 mdelay(10);
684 printk(KERN_INFO "AVM PCI/PnP: S1 %x\n", inb(cs->hw.avm.cfg_reg + 3));
685 }
686
687 static int
AVM_card_msg(struct IsdnCardState * cs,int mt,void * arg)688 AVM_card_msg(struct IsdnCardState *cs, int mt, void *arg)
689 {
690 u_long flags;
691
692 switch (mt) {
693 case CARD_RESET:
694 spin_lock_irqsave(&cs->lock, flags);
695 reset_avmpcipnp(cs);
696 spin_unlock_irqrestore(&cs->lock, flags);
697 return (0);
698 case CARD_RELEASE:
699 outb(0, cs->hw.avm.cfg_reg + 2);
700 release_region(cs->hw.avm.cfg_reg, 32);
701 return (0);
702 case CARD_INIT:
703 spin_lock_irqsave(&cs->lock, flags);
704 reset_avmpcipnp(cs);
705 clear_pending_isac_ints(cs);
706 initisac(cs);
707 inithdlc(cs);
708 outb(AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER,
709 cs->hw.avm.cfg_reg + 2);
710 WriteISAC(cs, ISAC_MASK, 0);
711 outb(AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER |
712 AVM_STATUS0_ENA_IRQ, cs->hw.avm.cfg_reg + 2);
713 /* RESET Receiver and Transmitter */
714 WriteISAC(cs, ISAC_CMDR, 0x41);
715 spin_unlock_irqrestore(&cs->lock, flags);
716 return (0);
717 case CARD_TEST:
718 return (0);
719 }
720 return (0);
721 }
722
avm_setup_rest(struct IsdnCardState * cs)723 static int avm_setup_rest(struct IsdnCardState *cs)
724 {
725 u_int val, ver;
726
727 cs->hw.avm.isac = cs->hw.avm.cfg_reg + 0x10;
728 if (!request_region(cs->hw.avm.cfg_reg, 32,
729 (cs->subtyp == AVM_FRITZ_PCI) ? "avm PCI" : "avm PnP")) {
730 printk(KERN_WARNING
731 "HiSax: Fritz!PCI/PNP config port %x-%x already in use\n",
732 cs->hw.avm.cfg_reg,
733 cs->hw.avm.cfg_reg + 31);
734 return (0);
735 }
736 switch (cs->subtyp) {
737 case AVM_FRITZ_PCI:
738 val = inl(cs->hw.avm.cfg_reg);
739 printk(KERN_INFO "AVM PCI: stat %#x\n", val);
740 printk(KERN_INFO "AVM PCI: Class %X Rev %d\n",
741 val & 0xff, (val >> 8) & 0xff);
742 cs->BC_Read_Reg = &ReadHDLC_s;
743 cs->BC_Write_Reg = &WriteHDLC_s;
744 break;
745 case AVM_FRITZ_PNP:
746 val = inb(cs->hw.avm.cfg_reg);
747 ver = inb(cs->hw.avm.cfg_reg + 1);
748 printk(KERN_INFO "AVM PnP: Class %X Rev %d\n", val, ver);
749 cs->BC_Read_Reg = &ReadHDLCPnP;
750 cs->BC_Write_Reg = &WriteHDLCPnP;
751 break;
752 default:
753 printk(KERN_WARNING "AVM unknown subtype %d\n", cs->subtyp);
754 return (0);
755 }
756 printk(KERN_INFO "HiSax: %s config irq:%d base:0x%X\n",
757 (cs->subtyp == AVM_FRITZ_PCI) ? "AVM Fritz!PCI" : "AVM Fritz!PnP",
758 cs->irq, cs->hw.avm.cfg_reg);
759
760 setup_isac(cs);
761 cs->readisac = &ReadISAC;
762 cs->writeisac = &WriteISAC;
763 cs->readisacfifo = &ReadISACfifo;
764 cs->writeisacfifo = &WriteISACfifo;
765 cs->BC_Send_Data = &hdlc_fill_fifo;
766 cs->cardmsg = &AVM_card_msg;
767 cs->irq_func = &avm_pcipnp_interrupt;
768 cs->writeisac(cs, ISAC_MASK, 0xFF);
769 ISACVersion(cs, (cs->subtyp == AVM_FRITZ_PCI) ? "AVM PCI:" : "AVM PnP:");
770 return (1);
771 }
772
773 #ifndef __ISAPNP__
774
avm_pnp_setup(struct IsdnCardState * cs)775 static int avm_pnp_setup(struct IsdnCardState *cs)
776 {
777 return (1); /* no-op: success */
778 }
779
780 #else
781
782 static struct pnp_card *pnp_avm_c = NULL;
783
avm_pnp_setup(struct IsdnCardState * cs)784 static int avm_pnp_setup(struct IsdnCardState *cs)
785 {
786 struct pnp_dev *pnp_avm_d = NULL;
787
788 if (!isapnp_present())
789 return (1); /* no-op: success */
790
791 if ((pnp_avm_c = pnp_find_card(
792 ISAPNP_VENDOR('A', 'V', 'M'),
793 ISAPNP_FUNCTION(0x0900), pnp_avm_c))) {
794 if ((pnp_avm_d = pnp_find_dev(pnp_avm_c,
795 ISAPNP_VENDOR('A', 'V', 'M'),
796 ISAPNP_FUNCTION(0x0900), pnp_avm_d))) {
797 int err;
798
799 pnp_disable_dev(pnp_avm_d);
800 err = pnp_activate_dev(pnp_avm_d);
801 if (err < 0) {
802 printk(KERN_WARNING "%s: pnp_activate_dev ret(%d)\n",
803 __func__, err);
804 return (0);
805 }
806 cs->hw.avm.cfg_reg =
807 pnp_port_start(pnp_avm_d, 0);
808 cs->irq = pnp_irq(pnp_avm_d, 0);
809 if (cs->irq == -1) {
810 printk(KERN_ERR "FritzPnP:No IRQ\n");
811 return (0);
812 }
813 if (!cs->hw.avm.cfg_reg) {
814 printk(KERN_ERR "FritzPnP:No IO address\n");
815 return (0);
816 }
817 cs->subtyp = AVM_FRITZ_PNP;
818
819 return (2); /* goto 'ready' label */
820 }
821 }
822
823 return (1);
824 }
825
826 #endif /* __ISAPNP__ */
827
828 #ifndef CONFIG_PCI
829
avm_pci_setup(struct IsdnCardState * cs)830 static int avm_pci_setup(struct IsdnCardState *cs)
831 {
832 return (1); /* no-op: success */
833 }
834
835 #else
836
837 static struct pci_dev *dev_avm = NULL;
838
avm_pci_setup(struct IsdnCardState * cs)839 static int avm_pci_setup(struct IsdnCardState *cs)
840 {
841 if ((dev_avm = hisax_find_pci_device(PCI_VENDOR_ID_AVM,
842 PCI_DEVICE_ID_AVM_A1, dev_avm))) {
843
844 if (pci_enable_device(dev_avm))
845 return (0);
846
847 cs->irq = dev_avm->irq;
848 if (!cs->irq) {
849 printk(KERN_ERR "FritzPCI: No IRQ for PCI card found\n");
850 return (0);
851 }
852
853 cs->hw.avm.cfg_reg = pci_resource_start(dev_avm, 1);
854 if (!cs->hw.avm.cfg_reg) {
855 printk(KERN_ERR "FritzPCI: No IO-Adr for PCI card found\n");
856 return (0);
857 }
858
859 cs->subtyp = AVM_FRITZ_PCI;
860 } else {
861 printk(KERN_WARNING "FritzPCI: No PCI card found\n");
862 return (0);
863 }
864
865 cs->irq_flags |= IRQF_SHARED;
866
867 return (1);
868 }
869
870 #endif /* CONFIG_PCI */
871
setup_avm_pcipnp(struct IsdnCard * card)872 int setup_avm_pcipnp(struct IsdnCard *card)
873 {
874 struct IsdnCardState *cs = card->cs;
875 char tmp[64];
876 int rc;
877
878 strcpy(tmp, avm_pci_rev);
879 printk(KERN_INFO "HiSax: AVM PCI driver Rev. %s\n", HiSax_getrev(tmp));
880
881 if (cs->typ != ISDN_CTYPE_FRITZPCI)
882 return (0);
883
884 if (card->para[1]) {
885 /* old manual method */
886 cs->hw.avm.cfg_reg = card->para[1];
887 cs->irq = card->para[0];
888 cs->subtyp = AVM_FRITZ_PNP;
889 goto ready;
890 }
891
892 rc = avm_pnp_setup(cs);
893 if (rc < 1)
894 return (0);
895 if (rc == 2)
896 goto ready;
897
898 rc = avm_pci_setup(cs);
899 if (rc < 1)
900 return (0);
901
902 ready:
903 return avm_setup_rest(cs);
904 }
905