1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /***************************************************************/ 3 /* $Id: hfc4s8s_l1.h,v 1.1 2005/02/02 17:28:55 martinb1 Exp $ */ 4 /* */ 5 /* This file is a minimal required extraction of hfc48scu.h */ 6 /* (Genero 3.2, HFC XML 1.7a for HFC-E1, HFC-4S and HFC-8S) */ 7 /* */ 8 /* To get this complete register description contact */ 9 /* Cologne Chip AG : */ 10 /* Internet: http://www.colognechip.com/ */ 11 /* E-Mail: info@colognechip.com */ 12 /***************************************************************/ 13 14 #ifndef _HFC4S8S_L1_H_ 15 #define _HFC4S8S_L1_H_ 16 17 18 /* 19 * include Genero generated HFC-4S/8S header file hfc48scu.h 20 * for complete register description. This will define _HFC48SCU_H_ 21 * to prevent redefinitions 22 */ 23 24 // #include "hfc48scu.h" 25 26 #ifndef _HFC48SCU_H_ 27 #define _HFC48SCU_H_ 28 29 #ifndef PCI_VENDOR_ID_CCD 30 #define PCI_VENDOR_ID_CCD 0x1397 31 #endif 32 33 #define CHIP_ID_4S 0x0C 34 #define CHIP_ID_8S 0x08 35 #define PCI_DEVICE_ID_4S 0x08B4 36 #define PCI_DEVICE_ID_8S 0x16B8 37 38 #define R_IRQ_MISC 0x11 39 #define M_TI_IRQ 0x02 40 #define A_ST_RD_STA 0x30 41 #define A_ST_WR_STA 0x30 42 #define M_SET_G2_G3 0x80 43 #define A_ST_CTRL0 0x31 44 #define A_ST_CTRL2 0x33 45 #define A_ST_CLK_DLY 0x37 46 #define A_Z1 0x04 47 #define A_Z2 0x06 48 #define R_CIRM 0x00 49 #define M_SRES 0x08 50 #define R_CTRL 0x01 51 #define R_BRG_PCM_CFG 0x02 52 #define M_PCM_CLK 0x20 53 #define R_RAM_MISC 0x0C 54 #define M_FZ_MD 0x80 55 #define R_FIFO_MD 0x0D 56 #define A_INC_RES_FIFO 0x0E 57 #define R_FIFO 0x0F 58 #define A_F1 0x0C 59 #define A_F2 0x0D 60 #define R_IRQ_OVIEW 0x10 61 #define R_CHIP_ID 0x16 62 #define R_STATUS 0x1C 63 #define M_BUSY 0x01 64 #define M_MISC_IRQSTA 0x40 65 #define M_FR_IRQSTA 0x80 66 #define R_CHIP_RV 0x1F 67 #define R_IRQ_CTRL 0x13 68 #define M_FIFO_IRQ 0x01 69 #define M_GLOB_IRQ_EN 0x08 70 #define R_PCM_MD0 0x14 71 #define M_PCM_MD 0x01 72 #define A_FIFO_DATA0 0x80 73 #define R_TI_WD 0x1A 74 #define R_PWM1 0x39 75 #define R_PWM_MD 0x46 76 #define R_IRQ_FIFO_BL0 0xC8 77 #define A_CON_HDLC 0xFA 78 #define A_SUBCH_CFG 0xFB 79 #define A_IRQ_MSK 0xFF 80 #define R_SCI_MSK 0x12 81 #define R_ST_SEL 0x16 82 #define R_ST_SYNC 0x17 83 #define M_AUTO_SYNC 0x08 84 #define R_SCI 0x12 85 #define R_IRQMSK_MISC 0x11 86 #define M_TI_IRQMSK 0x02 87 88 #endif /* _HFC4S8S_L1_H_ */ 89 #endif /* _HFC48SCU_H_ */ 90