1 /*
2 * Auvitek AU8522 QAM/8VSB demodulator driver and video decoder
3 *
4 * Copyright (C) 2009 Devin Heitmueller <dheitmueller@linuxtv.org>
5 * Copyright (C) 2005-2008 Auvitek International, Ltd.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * As published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 /* Developer notes:
19 *
20 * Enough is implemented here for CVBS and S-Video inputs, but the actual
21 * analog demodulator code isn't implemented (not needed for xc5000 since it
22 * has its own demodulator and outputs CVBS)
23 *
24 */
25
26 #include <linux/kernel.h>
27 #include <linux/slab.h>
28 #include <linux/videodev2.h>
29 #include <linux/i2c.h>
30 #include <linux/delay.h>
31 #include <media/v4l2-common.h>
32 #include <media/v4l2-device.h>
33 #include "au8522.h"
34 #include "au8522_priv.h"
35
36 MODULE_AUTHOR("Devin Heitmueller");
37 MODULE_LICENSE("GPL");
38
39 static int au8522_analog_debug;
40
41
42 module_param_named(analog_debug, au8522_analog_debug, int, 0644);
43
44 MODULE_PARM_DESC(analog_debug,
45 "Analog debugging messages [0=Off (default) 1=On]");
46
47 struct au8522_register_config {
48 u16 reg_name;
49 u8 reg_val[8];
50 };
51
52
53 /* Video Decoder Filter Coefficients
54 The values are as follows from left to right
55 0="ATV RF" 1="ATV RF13" 2="CVBS" 3="S-Video" 4="PAL" 5=CVBS13" 6="SVideo13"
56 */
57 static const struct au8522_register_config filter_coef[] = {
58 {AU8522_FILTER_COEF_R410, {0x25, 0x00, 0x25, 0x25, 0x00, 0x00, 0x00} },
59 {AU8522_FILTER_COEF_R411, {0x20, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00} },
60 {AU8522_FILTER_COEF_R412, {0x03, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00} },
61 {AU8522_FILTER_COEF_R413, {0xe6, 0x00, 0xe6, 0xe6, 0x00, 0x00, 0x00} },
62 {AU8522_FILTER_COEF_R414, {0x40, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00} },
63 {AU8522_FILTER_COEF_R415, {0x1b, 0x00, 0x1b, 0x1b, 0x00, 0x00, 0x00} },
64 {AU8522_FILTER_COEF_R416, {0xc0, 0x00, 0xc0, 0x04, 0x00, 0x00, 0x00} },
65 {AU8522_FILTER_COEF_R417, {0x04, 0x00, 0x04, 0x04, 0x00, 0x00, 0x00} },
66 {AU8522_FILTER_COEF_R418, {0x8c, 0x00, 0x8c, 0x8c, 0x00, 0x00, 0x00} },
67 {AU8522_FILTER_COEF_R419, {0xa0, 0x40, 0xa0, 0xa0, 0x40, 0x40, 0x40} },
68 {AU8522_FILTER_COEF_R41A, {0x21, 0x09, 0x21, 0x21, 0x09, 0x09, 0x09} },
69 {AU8522_FILTER_COEF_R41B, {0x6c, 0x38, 0x6c, 0x6c, 0x38, 0x38, 0x38} },
70 {AU8522_FILTER_COEF_R41C, {0x03, 0xff, 0x03, 0x03, 0xff, 0xff, 0xff} },
71 {AU8522_FILTER_COEF_R41D, {0xbf, 0xc7, 0xbf, 0xbf, 0xc7, 0xc7, 0xc7} },
72 {AU8522_FILTER_COEF_R41E, {0xa0, 0xdf, 0xa0, 0xa0, 0xdf, 0xdf, 0xdf} },
73 {AU8522_FILTER_COEF_R41F, {0x10, 0x06, 0x10, 0x10, 0x06, 0x06, 0x06} },
74 {AU8522_FILTER_COEF_R420, {0xae, 0x30, 0xae, 0xae, 0x30, 0x30, 0x30} },
75 {AU8522_FILTER_COEF_R421, {0xc4, 0x01, 0xc4, 0xc4, 0x01, 0x01, 0x01} },
76 {AU8522_FILTER_COEF_R422, {0x54, 0xdd, 0x54, 0x54, 0xdd, 0xdd, 0xdd} },
77 {AU8522_FILTER_COEF_R423, {0xd0, 0xaf, 0xd0, 0xd0, 0xaf, 0xaf, 0xaf} },
78 {AU8522_FILTER_COEF_R424, {0x1c, 0xf7, 0x1c, 0x1c, 0xf7, 0xf7, 0xf7} },
79 {AU8522_FILTER_COEF_R425, {0x76, 0xdb, 0x76, 0x76, 0xdb, 0xdb, 0xdb} },
80 {AU8522_FILTER_COEF_R426, {0x61, 0xc0, 0x61, 0x61, 0xc0, 0xc0, 0xc0} },
81 {AU8522_FILTER_COEF_R427, {0xd1, 0x2f, 0xd1, 0xd1, 0x2f, 0x2f, 0x2f} },
82 {AU8522_FILTER_COEF_R428, {0x84, 0xd8, 0x84, 0x84, 0xd8, 0xd8, 0xd8} },
83 {AU8522_FILTER_COEF_R429, {0x06, 0xfb, 0x06, 0x06, 0xfb, 0xfb, 0xfb} },
84 {AU8522_FILTER_COEF_R42A, {0x21, 0xd5, 0x21, 0x21, 0xd5, 0xd5, 0xd5} },
85 {AU8522_FILTER_COEF_R42B, {0x0a, 0x3e, 0x0a, 0x0a, 0x3e, 0x3e, 0x3e} },
86 {AU8522_FILTER_COEF_R42C, {0xe6, 0x15, 0xe6, 0xe6, 0x15, 0x15, 0x15} },
87 {AU8522_FILTER_COEF_R42D, {0x01, 0x34, 0x01, 0x01, 0x34, 0x34, 0x34} },
88
89 };
90 #define NUM_FILTER_COEF (sizeof(filter_coef)\
91 / sizeof(struct au8522_register_config))
92
93
94 /* Registers 0x060b through 0x0652 are the LP Filter coefficients
95 The values are as follows from left to right
96 0="SIF" 1="ATVRF/ATVRF13"
97 Note: the "ATVRF/ATVRF13" mode has never been tested
98 */
99 static const struct au8522_register_config lpfilter_coef[] = {
100 {0x060b, {0x21, 0x0b} },
101 {0x060c, {0xad, 0xad} },
102 {0x060d, {0x70, 0xf0} },
103 {0x060e, {0xea, 0xe9} },
104 {0x060f, {0xdd, 0xdd} },
105 {0x0610, {0x08, 0x64} },
106 {0x0611, {0x60, 0x60} },
107 {0x0612, {0xf8, 0xb2} },
108 {0x0613, {0x01, 0x02} },
109 {0x0614, {0xe4, 0xb4} },
110 {0x0615, {0x19, 0x02} },
111 {0x0616, {0xae, 0x2e} },
112 {0x0617, {0xee, 0xc5} },
113 {0x0618, {0x56, 0x56} },
114 {0x0619, {0x30, 0x58} },
115 {0x061a, {0xf9, 0xf8} },
116 {0x061b, {0x24, 0x64} },
117 {0x061c, {0x07, 0x07} },
118 {0x061d, {0x30, 0x30} },
119 {0x061e, {0xa9, 0xed} },
120 {0x061f, {0x09, 0x0b} },
121 {0x0620, {0x42, 0xc2} },
122 {0x0621, {0x1d, 0x2a} },
123 {0x0622, {0xd6, 0x56} },
124 {0x0623, {0x95, 0x8b} },
125 {0x0624, {0x2b, 0x2b} },
126 {0x0625, {0x30, 0x24} },
127 {0x0626, {0x3e, 0x3e} },
128 {0x0627, {0x62, 0xe2} },
129 {0x0628, {0xe9, 0xf5} },
130 {0x0629, {0x99, 0x19} },
131 {0x062a, {0xd4, 0x11} },
132 {0x062b, {0x03, 0x04} },
133 {0x062c, {0xb5, 0x85} },
134 {0x062d, {0x1e, 0x20} },
135 {0x062e, {0x2a, 0xea} },
136 {0x062f, {0xd7, 0xd2} },
137 {0x0630, {0x15, 0x15} },
138 {0x0631, {0xa3, 0xa9} },
139 {0x0632, {0x1f, 0x1f} },
140 {0x0633, {0xf9, 0xd1} },
141 {0x0634, {0xc0, 0xc3} },
142 {0x0635, {0x4d, 0x8d} },
143 {0x0636, {0x21, 0x31} },
144 {0x0637, {0x83, 0x83} },
145 {0x0638, {0x08, 0x8c} },
146 {0x0639, {0x19, 0x19} },
147 {0x063a, {0x45, 0xa5} },
148 {0x063b, {0xef, 0xec} },
149 {0x063c, {0x8a, 0x8a} },
150 {0x063d, {0xf4, 0xf6} },
151 {0x063e, {0x8f, 0x8f} },
152 {0x063f, {0x44, 0x0c} },
153 {0x0640, {0xef, 0xf0} },
154 {0x0641, {0x66, 0x66} },
155 {0x0642, {0xcc, 0xd2} },
156 {0x0643, {0x41, 0x41} },
157 {0x0644, {0x63, 0x93} },
158 {0x0645, {0x8e, 0x8e} },
159 {0x0646, {0xa2, 0x42} },
160 {0x0647, {0x7b, 0x7b} },
161 {0x0648, {0x04, 0x04} },
162 {0x0649, {0x00, 0x00} },
163 {0x064a, {0x40, 0x40} },
164 {0x064b, {0x8c, 0x98} },
165 {0x064c, {0x00, 0x00} },
166 {0x064d, {0x63, 0xc3} },
167 {0x064e, {0x04, 0x04} },
168 {0x064f, {0x20, 0x20} },
169 {0x0650, {0x00, 0x00} },
170 {0x0651, {0x40, 0x40} },
171 {0x0652, {0x01, 0x01} },
172 };
173 #define NUM_LPFILTER_COEF (sizeof(lpfilter_coef)\
174 / sizeof(struct au8522_register_config))
175
to_state(struct v4l2_subdev * sd)176 static inline struct au8522_state *to_state(struct v4l2_subdev *sd)
177 {
178 return container_of(sd, struct au8522_state, sd);
179 }
180
setup_decoder_defaults(struct au8522_state * state,bool is_svideo)181 static void setup_decoder_defaults(struct au8522_state *state, bool is_svideo)
182 {
183 int i;
184 int filter_coef_type;
185
186 /* Provide reasonable defaults for picture tuning values */
187 au8522_writereg(state, AU8522_TVDEC_SHARPNESSREG009H, 0x07);
188 au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH, 0xed);
189 au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH, 0x79);
190 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 0x80);
191 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 0x80);
192 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 0x00);
193 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 0x00);
194
195 /* Other decoder registers */
196 au8522_writereg(state, AU8522_TVDEC_INT_MASK_REG010H, 0x00);
197
198 if (is_svideo)
199 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x04);
200 else
201 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x00);
202
203 au8522_writereg(state, AU8522_TVDEC_PGA_REG012H,
204 AU8522_TVDEC_PGA_REG012H_CVBS);
205 au8522_writereg(state, AU8522_TVDEC_COMB_MODE_REG015H,
206 AU8522_TVDEC_COMB_MODE_REG015H_CVBS);
207 au8522_writereg(state, AU8522_TVDED_DBG_MODE_REG060H,
208 AU8522_TVDED_DBG_MODE_REG060H_CVBS);
209
210 if (state->std == V4L2_STD_PAL_M) {
211 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
212 AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 |
213 AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 |
214 AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_AUTO);
215 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
216 AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_PAL_M);
217 } else {
218 /* NTSC */
219 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
220 AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 |
221 AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 |
222 AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_MN);
223 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
224 AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_NTSC);
225 }
226 au8522_writereg(state, AU8522_TVDEC_VCR_DET_LLIM_REG063H,
227 AU8522_TVDEC_VCR_DET_LLIM_REG063H_CVBS);
228 au8522_writereg(state, AU8522_TVDEC_VCR_DET_HLIM_REG064H,
229 AU8522_TVDEC_VCR_DET_HLIM_REG064H_CVBS);
230 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR1_REG065H,
231 AU8522_TVDEC_COMB_VDIF_THR1_REG065H_CVBS);
232 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR2_REG066H,
233 AU8522_TVDEC_COMB_VDIF_THR2_REG066H_CVBS);
234 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR3_REG067H,
235 AU8522_TVDEC_COMB_VDIF_THR3_REG067H_CVBS);
236 au8522_writereg(state, AU8522_TVDEC_COMB_NOTCH_THR_REG068H,
237 AU8522_TVDEC_COMB_NOTCH_THR_REG068H_CVBS);
238 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR1_REG069H,
239 AU8522_TVDEC_COMB_HDIF_THR1_REG069H_CVBS);
240 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR2_REG06AH,
241 AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS);
242 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH,
243 AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS);
244 if (is_svideo) {
245 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
246 AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO);
247 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
248 AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO);
249 } else {
250 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
251 AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS);
252 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
253 AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS);
254 }
255 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH,
256 AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS);
257 au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH,
258 AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS);
259 au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H,
260 AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS);
261 au8522_writereg(state, AU8522_REG071H, AU8522_REG071H_CVBS);
262 au8522_writereg(state, AU8522_REG072H, AU8522_REG072H_CVBS);
263 au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H,
264 AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H_CVBS);
265 au8522_writereg(state, AU8522_REG074H, AU8522_REG074H_CVBS);
266 au8522_writereg(state, AU8522_REG075H, AU8522_REG075H_CVBS);
267 au8522_writereg(state, AU8522_TVDEC_DCAGC_CTRL_REG077H,
268 AU8522_TVDEC_DCAGC_CTRL_REG077H_CVBS);
269 au8522_writereg(state, AU8522_TVDEC_PIC_START_ADJ_REG078H,
270 AU8522_TVDEC_PIC_START_ADJ_REG078H_CVBS);
271 au8522_writereg(state, AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H,
272 AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H_CVBS);
273 au8522_writereg(state, AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH,
274 AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH_CVBS);
275 au8522_writereg(state, AU8522_TVDEC_INTRP_CTRL_REG07BH,
276 AU8522_TVDEC_INTRP_CTRL_REG07BH_CVBS);
277 au8522_writereg(state, AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H,
278 AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H_CVBS);
279 au8522_writereg(state, AU8522_TOREGAAGC_REG0E5H,
280 AU8522_TOREGAAGC_REG0E5H_CVBS);
281 au8522_writereg(state, AU8522_REG016H, AU8522_REG016H_CVBS);
282
283 /*
284 * Despite what the table says, for the HVR-950q we still need
285 * to be in CVBS mode for the S-Video input (reason unknown).
286 */
287 /* filter_coef_type = 3; */
288 filter_coef_type = 5;
289
290 /* Load the Video Decoder Filter Coefficients */
291 for (i = 0; i < NUM_FILTER_COEF; i++) {
292 au8522_writereg(state, filter_coef[i].reg_name,
293 filter_coef[i].reg_val[filter_coef_type]);
294 }
295
296 /* It's not clear what these registers are for, but they are always
297 set to the same value regardless of what mode we're in */
298 au8522_writereg(state, AU8522_REG42EH, 0x87);
299 au8522_writereg(state, AU8522_REG42FH, 0xa2);
300 au8522_writereg(state, AU8522_REG430H, 0xbf);
301 au8522_writereg(state, AU8522_REG431H, 0xcb);
302 au8522_writereg(state, AU8522_REG432H, 0xa1);
303 au8522_writereg(state, AU8522_REG433H, 0x41);
304 au8522_writereg(state, AU8522_REG434H, 0x88);
305 au8522_writereg(state, AU8522_REG435H, 0xc2);
306 au8522_writereg(state, AU8522_REG436H, 0x3c);
307 }
308
au8522_setup_cvbs_mode(struct au8522_state * state,u8 input_mode)309 static void au8522_setup_cvbs_mode(struct au8522_state *state, u8 input_mode)
310 {
311 /* here we're going to try the pre-programmed route */
312 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
313 AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
314
315 /* PGA in automatic mode */
316 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
317
318 /* Enable clamping control */
319 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
320
321 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
322
323 setup_decoder_defaults(state, false);
324
325 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
326 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
327 }
328
au8522_setup_cvbs_tuner_mode(struct au8522_state * state,u8 input_mode)329 static void au8522_setup_cvbs_tuner_mode(struct au8522_state *state,
330 u8 input_mode)
331 {
332 /* here we're going to try the pre-programmed route */
333 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
334 AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
335
336 /* It's not clear why we have to have the PGA in automatic mode while
337 enabling clamp control, but it's what Windows does */
338 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
339
340 /* Enable clamping control */
341 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x0e);
342
343 /* Disable automatic PGA (since the CVBS is coming from the tuner) */
344 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x10);
345
346 /* Set input mode to CVBS on channel 4 with SIF audio input enabled */
347 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
348
349 setup_decoder_defaults(state, false);
350
351 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
352 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
353 }
354
au8522_setup_svideo_mode(struct au8522_state * state,u8 input_mode)355 static void au8522_setup_svideo_mode(struct au8522_state *state,
356 u8 input_mode)
357 {
358 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
359 AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO);
360
361 /* Set input to Y on Channe1, C on Channel 3 */
362 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
363
364 /* PGA in automatic mode */
365 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
366
367 /* Enable clamping control */
368 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
369
370 setup_decoder_defaults(state, true);
371
372 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
373 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
374 }
375
376 /* ----------------------------------------------------------------------- */
377
disable_audio_input(struct au8522_state * state)378 static void disable_audio_input(struct au8522_state *state)
379 {
380 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
381 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
382 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
383
384 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x04);
385 au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0x02);
386
387 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
388 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO);
389 }
390
391 /* 0=disable, 1=SIF */
set_audio_input(struct au8522_state * state)392 static void set_audio_input(struct au8522_state *state)
393 {
394 int aud_input = state->aud_input;
395 int i;
396
397 /* Note that this function needs to be used in conjunction with setting
398 the input routing via register 0x81 */
399
400 if (aud_input == AU8522_AUDIO_NONE) {
401 disable_audio_input(state);
402 return;
403 }
404
405 if (aud_input != AU8522_AUDIO_SIF) {
406 /* The caller asked for a mode we don't currently support */
407 printk(KERN_ERR "Unsupported audio mode requested! mode=%d\n",
408 aud_input);
409 return;
410 }
411
412 /* Load the Audio Decoder Filter Coefficients */
413 for (i = 0; i < NUM_LPFILTER_COEF; i++) {
414 au8522_writereg(state, lpfilter_coef[i].reg_name,
415 lpfilter_coef[i].reg_val[0]);
416 }
417
418 /* Set the volume */
419 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
420 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
421 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0xff);
422
423 /* Not sure what this does */
424 au8522_writereg(state, AU8522_REG0F9H, AU8522_REG0F9H_AUDIO);
425
426 /* Setup the audio mode to stereo DBX */
427 au8522_writereg(state, AU8522_AUDIO_MODE_REG0F1H, 0x82);
428 msleep(70);
429
430 /* Start the audio processing module */
431 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 0x9d);
432
433 /* Set the audio frequency to 48 KHz */
434 au8522_writereg(state, AU8522_AUDIOFREQ_REG606H, 0x03);
435
436 /* Set the I2S parameters (WS, LSB, mode, sample rate */
437 au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0xc2);
438
439 /* Enable the I2S output */
440 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x09);
441 }
442
443 /* ----------------------------------------------------------------------- */
444
au8522_s_ctrl(struct v4l2_ctrl * ctrl)445 static int au8522_s_ctrl(struct v4l2_ctrl *ctrl)
446 {
447 struct au8522_state *state =
448 container_of(ctrl->handler, struct au8522_state, hdl);
449
450 switch (ctrl->id) {
451 case V4L2_CID_BRIGHTNESS:
452 au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH,
453 ctrl->val - 128);
454 break;
455 case V4L2_CID_CONTRAST:
456 au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH,
457 ctrl->val);
458 break;
459 case V4L2_CID_SATURATION:
460 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH,
461 ctrl->val);
462 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH,
463 ctrl->val);
464 break;
465 case V4L2_CID_HUE:
466 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH,
467 ctrl->val >> 8);
468 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH,
469 ctrl->val & 0xFF);
470 break;
471 default:
472 return -EINVAL;
473 }
474
475 return 0;
476 }
477
478 /* ----------------------------------------------------------------------- */
479
480 #ifdef CONFIG_VIDEO_ADV_DEBUG
au8522_g_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)481 static int au8522_g_register(struct v4l2_subdev *sd,
482 struct v4l2_dbg_register *reg)
483 {
484 struct au8522_state *state = to_state(sd);
485
486 reg->val = au8522_readreg(state, reg->reg & 0xffff);
487 return 0;
488 }
489
au8522_s_register(struct v4l2_subdev * sd,const struct v4l2_dbg_register * reg)490 static int au8522_s_register(struct v4l2_subdev *sd,
491 const struct v4l2_dbg_register *reg)
492 {
493 struct au8522_state *state = to_state(sd);
494
495 au8522_writereg(state, reg->reg, reg->val & 0xff);
496 return 0;
497 }
498 #endif
499
au8522_video_set(struct au8522_state * state)500 static void au8522_video_set(struct au8522_state *state)
501 {
502 u8 input_mode;
503
504 au8522_writereg(state, 0xa4, 1 << 5);
505
506 switch (state->vid_input) {
507 case AU8522_COMPOSITE_CH1:
508 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH1;
509 au8522_setup_cvbs_mode(state, input_mode);
510 break;
511 case AU8522_COMPOSITE_CH2:
512 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH2;
513 au8522_setup_cvbs_mode(state, input_mode);
514 break;
515 case AU8522_COMPOSITE_CH3:
516 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH3;
517 au8522_setup_cvbs_mode(state, input_mode);
518 break;
519 case AU8522_COMPOSITE_CH4:
520 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH4;
521 au8522_setup_cvbs_mode(state, input_mode);
522 break;
523 case AU8522_SVIDEO_CH13:
524 input_mode = AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13;
525 au8522_setup_svideo_mode(state, input_mode);
526 break;
527 case AU8522_SVIDEO_CH24:
528 input_mode = AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24;
529 au8522_setup_svideo_mode(state, input_mode);
530 break;
531 default:
532 case AU8522_COMPOSITE_CH4_SIF:
533 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF;
534 au8522_setup_cvbs_tuner_mode(state, input_mode);
535 break;
536 }
537 }
538
au8522_s_stream(struct v4l2_subdev * sd,int enable)539 static int au8522_s_stream(struct v4l2_subdev *sd, int enable)
540 {
541 struct au8522_state *state = to_state(sd);
542
543 if (enable) {
544 /*
545 * Clear out any state associated with the digital side of the
546 * chip, so that when it gets powered back up it won't think
547 * that it is already tuned
548 */
549 state->current_frequency = 0;
550
551 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
552 0x01);
553 msleep(10);
554
555 au8522_video_set(state);
556 set_audio_input(state);
557
558 state->operational_mode = AU8522_ANALOG_MODE;
559 } else {
560 /* This does not completely power down the device
561 (it only reduces it from around 140ma to 80ma) */
562 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
563 1 << 5);
564 state->operational_mode = AU8522_SUSPEND_MODE;
565 }
566 return 0;
567 }
568
au8522_s_video_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)569 static int au8522_s_video_routing(struct v4l2_subdev *sd,
570 u32 input, u32 output, u32 config)
571 {
572 struct au8522_state *state = to_state(sd);
573
574 switch(input) {
575 case AU8522_COMPOSITE_CH1:
576 case AU8522_SVIDEO_CH13:
577 case AU8522_COMPOSITE_CH4_SIF:
578 state->vid_input = input;
579 break;
580 default:
581 printk(KERN_ERR "au8522 mode not currently supported\n");
582 return -EINVAL;
583 }
584
585 if (state->operational_mode == AU8522_ANALOG_MODE)
586 au8522_video_set(state);
587
588 return 0;
589 }
590
au8522_s_std(struct v4l2_subdev * sd,v4l2_std_id std)591 static int au8522_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
592 {
593 struct au8522_state *state = to_state(sd);
594
595 if ((std & (V4L2_STD_PAL_M | V4L2_STD_NTSC_M)) == 0)
596 return -EINVAL;
597
598 state->std = std;
599
600 if (state->operational_mode == AU8522_ANALOG_MODE)
601 au8522_video_set(state);
602
603 return 0;
604 }
605
au8522_s_audio_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)606 static int au8522_s_audio_routing(struct v4l2_subdev *sd,
607 u32 input, u32 output, u32 config)
608 {
609 struct au8522_state *state = to_state(sd);
610
611 state->aud_input = input;
612
613 if (state->operational_mode == AU8522_ANALOG_MODE)
614 set_audio_input(state);
615
616 return 0;
617 }
618
au8522_g_tuner(struct v4l2_subdev * sd,struct v4l2_tuner * vt)619 static int au8522_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
620 {
621 int val = 0;
622 struct au8522_state *state = to_state(sd);
623 u8 lock_status;
624 u8 pll_status;
625
626 /* Interrogate the decoder to see if we are getting a real signal */
627 lock_status = au8522_readreg(state, 0x00);
628 pll_status = au8522_readreg(state, 0x7e);
629 if ((lock_status == 0xa2) && (pll_status & 0x10))
630 vt->signal = 0xffff;
631 else
632 vt->signal = 0x00;
633
634 vt->capability |=
635 V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
636 V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
637
638 val = V4L2_TUNER_SUB_MONO;
639 vt->rxsubchans = val;
640 vt->audmode = V4L2_TUNER_MODE_STEREO;
641 return 0;
642 }
643
644 /* ----------------------------------------------------------------------- */
645
646 static const struct v4l2_subdev_core_ops au8522_core_ops = {
647 .log_status = v4l2_ctrl_subdev_log_status,
648 #ifdef CONFIG_VIDEO_ADV_DEBUG
649 .g_register = au8522_g_register,
650 .s_register = au8522_s_register,
651 #endif
652 };
653
654 static const struct v4l2_subdev_tuner_ops au8522_tuner_ops = {
655 .g_tuner = au8522_g_tuner,
656 };
657
658 static const struct v4l2_subdev_audio_ops au8522_audio_ops = {
659 .s_routing = au8522_s_audio_routing,
660 };
661
662 static const struct v4l2_subdev_video_ops au8522_video_ops = {
663 .s_routing = au8522_s_video_routing,
664 .s_stream = au8522_s_stream,
665 .s_std = au8522_s_std,
666 };
667
668 static const struct v4l2_subdev_ops au8522_ops = {
669 .core = &au8522_core_ops,
670 .tuner = &au8522_tuner_ops,
671 .audio = &au8522_audio_ops,
672 .video = &au8522_video_ops,
673 };
674
675 static const struct v4l2_ctrl_ops au8522_ctrl_ops = {
676 .s_ctrl = au8522_s_ctrl,
677 };
678
679 /* ----------------------------------------------------------------------- */
680
au8522_probe(struct i2c_client * client,const struct i2c_device_id * did)681 static int au8522_probe(struct i2c_client *client,
682 const struct i2c_device_id *did)
683 {
684 struct au8522_state *state;
685 struct v4l2_ctrl_handler *hdl;
686 struct v4l2_subdev *sd;
687 int instance;
688 #ifdef CONFIG_MEDIA_CONTROLLER
689 int ret;
690 #endif
691
692 /* Check if the adapter supports the needed features */
693 if (!i2c_check_functionality(client->adapter,
694 I2C_FUNC_SMBUS_BYTE_DATA)) {
695 return -EIO;
696 }
697
698 /* allocate memory for the internal state */
699 instance = au8522_get_state(&state, client->adapter, client->addr);
700 switch (instance) {
701 case 0:
702 printk(KERN_ERR "au8522_decoder allocation failed\n");
703 return -EIO;
704 case 1:
705 /* new demod instance */
706 printk(KERN_INFO "au8522_decoder creating new instance...\n");
707 break;
708 default:
709 /* existing demod instance */
710 printk(KERN_INFO "au8522_decoder attach existing instance.\n");
711 break;
712 }
713
714 state->config.demod_address = 0x8e >> 1;
715 state->i2c = client->adapter;
716
717 sd = &state->sd;
718 v4l2_i2c_subdev_init(sd, client, &au8522_ops);
719 #if defined(CONFIG_MEDIA_CONTROLLER)
720
721 state->pads[DEMOD_PAD_IF_INPUT].flags = MEDIA_PAD_FL_SINK;
722 state->pads[DEMOD_PAD_VID_OUT].flags = MEDIA_PAD_FL_SOURCE;
723 state->pads[DEMOD_PAD_VBI_OUT].flags = MEDIA_PAD_FL_SOURCE;
724 state->pads[DEMOD_PAD_AUDIO_OUT].flags = MEDIA_PAD_FL_SOURCE;
725 sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
726
727 ret = media_entity_pads_init(&sd->entity, ARRAY_SIZE(state->pads),
728 state->pads);
729 if (ret < 0) {
730 v4l_info(client, "failed to initialize media entity!\n");
731 return ret;
732 }
733 #endif
734
735 hdl = &state->hdl;
736 v4l2_ctrl_handler_init(hdl, 4);
737 v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
738 V4L2_CID_BRIGHTNESS, 0, 255, 1, 109);
739 v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
740 V4L2_CID_CONTRAST, 0, 255, 1,
741 AU8522_TVDEC_CONTRAST_REG00BH_CVBS);
742 v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
743 V4L2_CID_SATURATION, 0, 255, 1, 128);
744 v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
745 V4L2_CID_HUE, -32768, 32767, 1, 0);
746 sd->ctrl_handler = hdl;
747 if (hdl->error) {
748 int err = hdl->error;
749
750 v4l2_ctrl_handler_free(hdl);
751 au8522_release_state(state);
752 return err;
753 }
754
755 state->c = client;
756 state->std = V4L2_STD_NTSC_M;
757 state->vid_input = AU8522_COMPOSITE_CH1;
758 state->aud_input = AU8522_AUDIO_NONE;
759 state->id = 8522;
760 state->rev = 0;
761
762 /* Jam open the i2c gate to the tuner */
763 au8522_writereg(state, 0x106, 1);
764
765 return 0;
766 }
767
au8522_remove(struct i2c_client * client)768 static int au8522_remove(struct i2c_client *client)
769 {
770 struct v4l2_subdev *sd = i2c_get_clientdata(client);
771 v4l2_device_unregister_subdev(sd);
772 v4l2_ctrl_handler_free(sd->ctrl_handler);
773 au8522_release_state(to_state(sd));
774 return 0;
775 }
776
777 static const struct i2c_device_id au8522_id[] = {
778 {"au8522", 0},
779 {}
780 };
781
782 MODULE_DEVICE_TABLE(i2c, au8522_id);
783
784 static struct i2c_driver au8522_driver = {
785 .driver = {
786 .name = "au8522",
787 },
788 .probe = au8522_probe,
789 .remove = au8522_remove,
790 .id_table = au8522_id,
791 };
792
793 module_i2c_driver(au8522_driver);
794