1 /*
2 * i.MX6 OCOTP fusebox driver
3 *
4 * Copyright (c) 2015 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
5 *
6 * Based on the barebox ocotp driver,
7 * Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>,
8 * Orex Computed Radiography
9 *
10 * Write support based on the fsl_otp driver,
11 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2
15 * as published by the Free Software Foundation.
16 *
17 * http://www.opensource.org/licenses/gpl-license.html
18 * http://www.gnu.org/copyleft/gpl.html
19 */
20
21 #include <linux/clk.h>
22 #include <linux/device.h>
23 #include <linux/io.h>
24 #include <linux/module.h>
25 #include <linux/nvmem-provider.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31
32 #define IMX_OCOTP_OFFSET_B0W0 0x400 /* Offset from base address of the
33 * OTP Bank0 Word0
34 */
35 #define IMX_OCOTP_OFFSET_PER_WORD 0x10 /* Offset between the start addr
36 * of two consecutive OTP words.
37 */
38
39 #define IMX_OCOTP_ADDR_CTRL 0x0000
40 #define IMX_OCOTP_ADDR_CTRL_SET 0x0004
41 #define IMX_OCOTP_ADDR_CTRL_CLR 0x0008
42 #define IMX_OCOTP_ADDR_TIMING 0x0010
43 #define IMX_OCOTP_ADDR_DATA0 0x0020
44 #define IMX_OCOTP_ADDR_DATA1 0x0030
45 #define IMX_OCOTP_ADDR_DATA2 0x0040
46 #define IMX_OCOTP_ADDR_DATA3 0x0050
47
48 #define IMX_OCOTP_BM_CTRL_ADDR 0x0000007F
49 #define IMX_OCOTP_BM_CTRL_BUSY 0x00000100
50 #define IMX_OCOTP_BM_CTRL_ERROR 0x00000200
51 #define IMX_OCOTP_BM_CTRL_REL_SHADOWS 0x00000400
52
53 #define TIMING_STROBE_PROG_US 10 /* Min time to blow a fuse */
54 #define TIMING_STROBE_READ_NS 37 /* Min time before read */
55 #define TIMING_RELAX_NS 17
56 #define DEF_FSOURCE 1001 /* > 1000 ns */
57 #define DEF_STROBE_PROG 10000 /* IPG clocks */
58 #define IMX_OCOTP_WR_UNLOCK 0x3E770000
59 #define IMX_OCOTP_READ_LOCKED_VAL 0xBADABADA
60
61 static DEFINE_MUTEX(ocotp_mutex);
62
63 struct ocotp_priv {
64 struct device *dev;
65 struct clk *clk;
66 void __iomem *base;
67 const struct ocotp_params *params;
68 struct nvmem_config *config;
69 };
70
71 struct ocotp_params {
72 unsigned int nregs;
73 unsigned int bank_address_words;
74 void (*set_timing)(struct ocotp_priv *priv);
75 };
76
imx_ocotp_wait_for_busy(void __iomem * base,u32 flags)77 static int imx_ocotp_wait_for_busy(void __iomem *base, u32 flags)
78 {
79 int count;
80 u32 c, mask;
81
82 mask = IMX_OCOTP_BM_CTRL_BUSY | IMX_OCOTP_BM_CTRL_ERROR | flags;
83
84 for (count = 10000; count >= 0; count--) {
85 c = readl(base + IMX_OCOTP_ADDR_CTRL);
86 if (!(c & mask))
87 break;
88 cpu_relax();
89 }
90
91 if (count < 0) {
92 /* HW_OCOTP_CTRL[ERROR] will be set under the following
93 * conditions:
94 * - A write is performed to a shadow register during a shadow
95 * reload (essentially, while HW_OCOTP_CTRL[RELOAD_SHADOWS] is
96 * set. In addition, the contents of the shadow register shall
97 * not be updated.
98 * - A write is performed to a shadow register which has been
99 * locked.
100 * - A read is performed to from a shadow register which has
101 * been read locked.
102 * - A program is performed to a fuse word which has been locked
103 * - A read is performed to from a fuse word which has been read
104 * locked.
105 */
106 if (c & IMX_OCOTP_BM_CTRL_ERROR)
107 return -EPERM;
108 return -ETIMEDOUT;
109 }
110
111 return 0;
112 }
113
imx_ocotp_clr_err_if_set(void __iomem * base)114 static void imx_ocotp_clr_err_if_set(void __iomem *base)
115 {
116 u32 c;
117
118 c = readl(base + IMX_OCOTP_ADDR_CTRL);
119 if (!(c & IMX_OCOTP_BM_CTRL_ERROR))
120 return;
121
122 writel(IMX_OCOTP_BM_CTRL_ERROR, base + IMX_OCOTP_ADDR_CTRL_CLR);
123 }
124
imx_ocotp_read(void * context,unsigned int offset,void * val,size_t bytes)125 static int imx_ocotp_read(void *context, unsigned int offset,
126 void *val, size_t bytes)
127 {
128 struct ocotp_priv *priv = context;
129 unsigned int count;
130 u32 *buf = val;
131 int i, ret;
132 u32 index;
133
134 index = offset >> 2;
135 count = bytes >> 2;
136
137 if (count > (priv->params->nregs - index))
138 count = priv->params->nregs - index;
139
140 mutex_lock(&ocotp_mutex);
141
142 ret = clk_prepare_enable(priv->clk);
143 if (ret < 0) {
144 mutex_unlock(&ocotp_mutex);
145 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
146 return ret;
147 }
148
149 ret = imx_ocotp_wait_for_busy(priv->base, 0);
150 if (ret < 0) {
151 dev_err(priv->dev, "timeout during read setup\n");
152 goto read_end;
153 }
154
155 for (i = index; i < (index + count); i++) {
156 *buf++ = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 +
157 i * IMX_OCOTP_OFFSET_PER_WORD);
158
159 /* 47.3.1.2
160 * For "read locked" registers 0xBADABADA will be returned and
161 * HW_OCOTP_CTRL[ERROR] will be set. It must be cleared by
162 * software before any new write, read or reload access can be
163 * issued
164 */
165 if (*(buf - 1) == IMX_OCOTP_READ_LOCKED_VAL)
166 imx_ocotp_clr_err_if_set(priv->base);
167 }
168 ret = 0;
169
170 read_end:
171 clk_disable_unprepare(priv->clk);
172 mutex_unlock(&ocotp_mutex);
173 return ret;
174 }
175
imx_ocotp_set_imx6_timing(struct ocotp_priv * priv)176 static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv)
177 {
178 unsigned long clk_rate = 0;
179 unsigned long strobe_read, relax, strobe_prog;
180 u32 timing = 0;
181
182 /* 47.3.1.3.1
183 * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX]
184 * fields with timing values to match the current frequency of the
185 * ipg_clk. OTP writes will work at maximum bus frequencies as long
186 * as the HW_OCOTP_TIMING parameters are set correctly.
187 *
188 * Note: there are minimum timings required to ensure an OTP fuse burns
189 * correctly that are independent of the ipg_clk. Those values are not
190 * formally documented anywhere however, working from the minimum
191 * timings given in u-boot we can say:
192 *
193 * - Minimum STROBE_PROG time is 10 microseconds. Intuitively 10
194 * microseconds feels about right as representative of a minimum time
195 * to physically burn out a fuse.
196 *
197 * - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before
198 * performing another read is 37 nanoseconds
199 *
200 * - Minimum RELAX timing is 17 nanoseconds. This final RELAX minimum
201 * timing is not entirely clear the documentation says "This
202 * count value specifies the time to add to all default timing
203 * parameters other than the Tpgm and Trd. It is given in number
204 * of ipg_clk periods." where Tpgm and Trd refer to STROBE_PROG
205 * and STROBE_READ respectively. What the other timing parameters
206 * are though, is not specified. Experience shows a zero RELAX
207 * value will mess up a re-load of the shadow registers post OTP
208 * burn.
209 */
210 clk_rate = clk_get_rate(priv->clk);
211
212 relax = DIV_ROUND_UP(clk_rate * TIMING_RELAX_NS, 1000000000) - 1;
213 strobe_read = DIV_ROUND_UP(clk_rate * TIMING_STROBE_READ_NS,
214 1000000000);
215 strobe_read += 2 * (relax + 1) - 1;
216 strobe_prog = DIV_ROUND_CLOSEST(clk_rate * TIMING_STROBE_PROG_US,
217 1000000);
218 strobe_prog += 2 * (relax + 1) - 1;
219
220 timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000;
221 timing |= strobe_prog & 0x00000FFF;
222 timing |= (relax << 12) & 0x0000F000;
223 timing |= (strobe_read << 16) & 0x003F0000;
224
225 writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
226 }
227
imx_ocotp_set_imx7_timing(struct ocotp_priv * priv)228 static void imx_ocotp_set_imx7_timing(struct ocotp_priv *priv)
229 {
230 unsigned long clk_rate = 0;
231 u64 fsource, strobe_prog;
232 u32 timing = 0;
233
234 /* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1
235 * 6.4.3.3
236 */
237 clk_rate = clk_get_rate(priv->clk);
238 fsource = DIV_ROUND_UP_ULL((u64)clk_rate * DEF_FSOURCE,
239 NSEC_PER_SEC) + 1;
240 strobe_prog = DIV_ROUND_CLOSEST_ULL((u64)clk_rate * DEF_STROBE_PROG,
241 NSEC_PER_SEC) + 1;
242
243 timing = strobe_prog & 0x00000FFF;
244 timing |= (fsource << 12) & 0x000FF000;
245
246 writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
247 }
248
imx_ocotp_write(void * context,unsigned int offset,void * val,size_t bytes)249 static int imx_ocotp_write(void *context, unsigned int offset, void *val,
250 size_t bytes)
251 {
252 struct ocotp_priv *priv = context;
253 u32 *buf = val;
254 int ret;
255
256 u32 ctrl;
257 u8 waddr;
258 u8 word = 0;
259
260 /* allow only writing one complete OTP word at a time */
261 if ((bytes != priv->config->word_size) ||
262 (offset % priv->config->word_size))
263 return -EINVAL;
264
265 mutex_lock(&ocotp_mutex);
266
267 ret = clk_prepare_enable(priv->clk);
268 if (ret < 0) {
269 mutex_unlock(&ocotp_mutex);
270 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
271 return ret;
272 }
273
274 /* Setup the write timing values */
275 priv->params->set_timing(priv);
276
277 /* 47.3.1.3.2
278 * Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear.
279 * Overlapped accesses are not supported by the controller. Any pending
280 * write or reload must be completed before a write access can be
281 * requested.
282 */
283 ret = imx_ocotp_wait_for_busy(priv->base, 0);
284 if (ret < 0) {
285 dev_err(priv->dev, "timeout during timing setup\n");
286 goto write_end;
287 }
288
289 /* 47.3.1.3.3
290 * Write the requested address to HW_OCOTP_CTRL[ADDR] and program the
291 * unlock code into HW_OCOTP_CTRL[WR_UNLOCK]. This must be programmed
292 * for each write access. The lock code is documented in the register
293 * description. Both the unlock code and address can be written in the
294 * same operation.
295 */
296 if (priv->params->bank_address_words != 0) {
297 /*
298 * In banked/i.MX7 mode the OTP register bank goes into waddr
299 * see i.MX 7Solo Applications Processor Reference Manual, Rev.
300 * 0.1 section 6.4.3.1
301 */
302 offset = offset / priv->config->word_size;
303 waddr = offset / priv->params->bank_address_words;
304 word = offset & (priv->params->bank_address_words - 1);
305 } else {
306 /*
307 * Non-banked i.MX6 mode.
308 * OTP write/read address specifies one of 128 word address
309 * locations
310 */
311 waddr = offset / 4;
312 }
313
314 ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL);
315 ctrl &= ~IMX_OCOTP_BM_CTRL_ADDR;
316 ctrl |= waddr & IMX_OCOTP_BM_CTRL_ADDR;
317 ctrl |= IMX_OCOTP_WR_UNLOCK;
318
319 writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL);
320
321 /* 47.3.1.3.4
322 * Write the data to the HW_OCOTP_DATA register. This will automatically
323 * set HW_OCOTP_CTRL[BUSY] and clear HW_OCOTP_CTRL[WR_UNLOCK]. To
324 * protect programming same OTP bit twice, before program OCOTP will
325 * automatically read fuse value in OTP and use read value to mask
326 * program data. The controller will use masked program data to program
327 * a 32-bit word in the OTP per the address in HW_OCOTP_CTRL[ADDR]. Bit
328 * fields with 1's will result in that OTP bit being programmed. Bit
329 * fields with 0's will be ignored. At the same time that the write is
330 * accepted, the controller makes an internal copy of
331 * HW_OCOTP_CTRL[ADDR] which cannot be updated until the next write
332 * sequence is initiated. This copy guarantees that erroneous writes to
333 * HW_OCOTP_CTRL[ADDR] will not affect an active write operation. It
334 * should also be noted that during the programming HW_OCOTP_DATA will
335 * shift right (with zero fill). This shifting is required to program
336 * the OTP serially. During the write operation, HW_OCOTP_DATA cannot be
337 * modified.
338 * Note: on i.MX7 there are four data fields to write for banked write
339 * with the fuse blowing operation only taking place after data0
340 * has been written. This is why data0 must always be the last
341 * register written.
342 */
343 if (priv->params->bank_address_words != 0) {
344 /* Banked/i.MX7 mode */
345 switch (word) {
346 case 0:
347 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
348 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
349 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
350 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
351 break;
352 case 1:
353 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1);
354 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
355 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
356 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
357 break;
358 case 2:
359 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
360 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2);
361 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
362 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
363 break;
364 case 3:
365 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
366 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
367 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3);
368 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
369 break;
370 }
371 } else {
372 /* Non-banked i.MX6 mode */
373 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
374 }
375
376 /* 47.4.1.4.5
377 * Once complete, the controller will clear BUSY. A write request to a
378 * protected or locked region will result in no OTP access and no
379 * setting of HW_OCOTP_CTRL[BUSY]. In addition HW_OCOTP_CTRL[ERROR] will
380 * be set. It must be cleared by software before any new write access
381 * can be issued.
382 */
383 ret = imx_ocotp_wait_for_busy(priv->base, 0);
384 if (ret < 0) {
385 if (ret == -EPERM) {
386 dev_err(priv->dev, "failed write to locked region");
387 imx_ocotp_clr_err_if_set(priv->base);
388 } else {
389 dev_err(priv->dev, "timeout during data write\n");
390 }
391 goto write_end;
392 }
393
394 /* 47.3.1.4
395 * Write Postamble: Due to internal electrical characteristics of the
396 * OTP during writes, all OTP operations following a write must be
397 * separated by 2 us after the clearing of HW_OCOTP_CTRL_BUSY following
398 * the write.
399 */
400 udelay(2);
401
402 /* reload all shadow registers */
403 writel(IMX_OCOTP_BM_CTRL_REL_SHADOWS,
404 priv->base + IMX_OCOTP_ADDR_CTRL_SET);
405 ret = imx_ocotp_wait_for_busy(priv->base,
406 IMX_OCOTP_BM_CTRL_REL_SHADOWS);
407 if (ret < 0) {
408 dev_err(priv->dev, "timeout during shadow register reload\n");
409 goto write_end;
410 }
411
412 write_end:
413 clk_disable_unprepare(priv->clk);
414 mutex_unlock(&ocotp_mutex);
415 if (ret < 0)
416 return ret;
417 return bytes;
418 }
419
420 static struct nvmem_config imx_ocotp_nvmem_config = {
421 .name = "imx-ocotp",
422 .read_only = false,
423 .word_size = 4,
424 .stride = 4,
425 .reg_read = imx_ocotp_read,
426 .reg_write = imx_ocotp_write,
427 };
428
429 static const struct ocotp_params imx6q_params = {
430 .nregs = 128,
431 .bank_address_words = 0,
432 .set_timing = imx_ocotp_set_imx6_timing,
433 };
434
435 static const struct ocotp_params imx6sl_params = {
436 .nregs = 64,
437 .bank_address_words = 0,
438 .set_timing = imx_ocotp_set_imx6_timing,
439 };
440
441 static const struct ocotp_params imx6sll_params = {
442 .nregs = 128,
443 .bank_address_words = 0,
444 .set_timing = imx_ocotp_set_imx6_timing,
445 };
446
447 static const struct ocotp_params imx6sx_params = {
448 .nregs = 128,
449 .bank_address_words = 0,
450 .set_timing = imx_ocotp_set_imx6_timing,
451 };
452
453 static const struct ocotp_params imx6ul_params = {
454 .nregs = 128,
455 .bank_address_words = 0,
456 .set_timing = imx_ocotp_set_imx6_timing,
457 };
458
459 static const struct ocotp_params imx7d_params = {
460 .nregs = 64,
461 .bank_address_words = 4,
462 .set_timing = imx_ocotp_set_imx7_timing,
463 };
464
465 static const struct of_device_id imx_ocotp_dt_ids[] = {
466 { .compatible = "fsl,imx6q-ocotp", .data = &imx6q_params },
467 { .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params },
468 { .compatible = "fsl,imx6sx-ocotp", .data = &imx6sx_params },
469 { .compatible = "fsl,imx6ul-ocotp", .data = &imx6ul_params },
470 { .compatible = "fsl,imx7d-ocotp", .data = &imx7d_params },
471 { .compatible = "fsl,imx6sll-ocotp", .data = &imx6sll_params },
472 { },
473 };
474 MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids);
475
imx_ocotp_probe(struct platform_device * pdev)476 static int imx_ocotp_probe(struct platform_device *pdev)
477 {
478 struct device *dev = &pdev->dev;
479 struct resource *res;
480 struct ocotp_priv *priv;
481 struct nvmem_device *nvmem;
482
483 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
484 if (!priv)
485 return -ENOMEM;
486
487 priv->dev = dev;
488
489 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
490 priv->base = devm_ioremap_resource(dev, res);
491 if (IS_ERR(priv->base))
492 return PTR_ERR(priv->base);
493
494 priv->clk = devm_clk_get(dev, NULL);
495 if (IS_ERR(priv->clk))
496 return PTR_ERR(priv->clk);
497
498 clk_prepare_enable(priv->clk);
499 imx_ocotp_clr_err_if_set(priv->base);
500 clk_disable_unprepare(priv->clk);
501
502 priv->params = of_device_get_match_data(&pdev->dev);
503 imx_ocotp_nvmem_config.size = 4 * priv->params->nregs;
504 imx_ocotp_nvmem_config.dev = dev;
505 imx_ocotp_nvmem_config.priv = priv;
506 priv->config = &imx_ocotp_nvmem_config;
507 nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config);
508
509
510 return PTR_ERR_OR_ZERO(nvmem);
511 }
512
513 static struct platform_driver imx_ocotp_driver = {
514 .probe = imx_ocotp_probe,
515 .driver = {
516 .name = "imx_ocotp",
517 .of_match_table = imx_ocotp_dt_ids,
518 },
519 };
520 module_platform_driver(imx_ocotp_driver);
521
522 MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
523 MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver");
524 MODULE_LICENSE("GPL v2");
525