1 /*
2 ** I/O Sapic Driver - PCI interrupt line support
3 **
4 ** (c) Copyright 1999 Grant Grundler
5 ** (c) Copyright 1999 Hewlett-Packard Company
6 **
7 ** This program is free software; you can redistribute it and/or modify
8 ** it under the terms of the GNU General Public License as published by
9 ** the Free Software Foundation; either version 2 of the License, or
10 ** (at your option) any later version.
11 **
12 ** The I/O sapic driver manages the Interrupt Redirection Table which is
13 ** the control logic to convert PCI line based interrupts into a Message
14 ** Signaled Interrupt (aka Transaction Based Interrupt, TBI).
15 **
16 ** Acronyms
17 ** --------
18 ** HPA Hard Physical Address (aka MMIO address)
19 ** IRQ Interrupt ReQuest. Implies Line based interrupt.
20 ** IRT Interrupt Routing Table (provided by PAT firmware)
21 ** IRdT Interrupt Redirection Table. IRQ line to TXN ADDR/DATA
22 ** table which is implemented in I/O SAPIC.
23 ** ISR Interrupt Service Routine. aka Interrupt handler.
24 ** MSI Message Signaled Interrupt. PCI 2.2 functionality.
25 ** aka Transaction Based Interrupt (or TBI).
26 ** PA Precision Architecture. HP's RISC architecture.
27 ** RISC Reduced Instruction Set Computer.
28 **
29 **
30 ** What's a Message Signalled Interrupt?
31 ** -------------------------------------
32 ** MSI is a write transaction which targets a processor and is similar
33 ** to a processor write to memory or MMIO. MSIs can be generated by I/O
34 ** devices as well as processors and require *architecture* to work.
35 **
36 ** PA only supports MSI. So I/O subsystems must either natively generate
37 ** MSIs (e.g. GSC or HP-PB) or convert line based interrupts into MSIs
38 ** (e.g. PCI and EISA). IA64 supports MSIs via a "local SAPIC" which
39 ** acts on behalf of a processor.
40 **
41 ** MSI allows any I/O device to interrupt any processor. This makes
42 ** load balancing of the interrupt processing possible on an SMP platform.
43 ** Interrupts are also ordered WRT to DMA data. It's possible on I/O
44 ** coherent systems to completely eliminate PIO reads from the interrupt
45 ** path. The device and driver must be designed and implemented to
46 ** guarantee all DMA has been issued (issues about atomicity here)
47 ** before the MSI is issued. I/O status can then safely be read from
48 ** DMA'd data by the ISR.
49 **
50 **
51 ** PA Firmware
52 ** -----------
53 ** PA-RISC platforms have two fundamentally different types of firmware.
54 ** For PCI devices, "Legacy" PDC initializes the "INTERRUPT_LINE" register
55 ** and BARs similar to a traditional PC BIOS.
56 ** The newer "PAT" firmware supports PDC calls which return tables.
57 ** PAT firmware only initializes the PCI Console and Boot interface.
58 ** With these tables, the OS can program all other PCI devices.
59 **
60 ** One such PAT PDC call returns the "Interrupt Routing Table" (IRT).
61 ** The IRT maps each PCI slot's INTA-D "output" line to an I/O SAPIC
62 ** input line. If the IRT is not available, this driver assumes
63 ** INTERRUPT_LINE register has been programmed by firmware. The latter
64 ** case also means online addition of PCI cards can NOT be supported
65 ** even if HW support is present.
66 **
67 ** All platforms with PAT firmware to date (Oct 1999) use one Interrupt
68 ** Routing Table for the entire platform.
69 **
70 ** Where's the iosapic?
71 ** --------------------
72 ** I/O sapic is part of the "Core Electronics Complex". And on HP platforms
73 ** it's integrated as part of the PCI bus adapter, "lba". So no bus walk
74 ** will discover I/O Sapic. I/O Sapic driver learns about each device
75 ** when lba driver advertises the presence of the I/O sapic by calling
76 ** iosapic_register().
77 **
78 **
79 ** IRQ handling notes
80 ** ------------------
81 ** The IO-SAPIC can indicate to the CPU which interrupt was asserted.
82 ** So, unlike the GSC-ASIC and Dino, we allocate one CPU interrupt per
83 ** IO-SAPIC interrupt and call the device driver's handler directly.
84 ** The IO-SAPIC driver hijacks the CPU interrupt handler so it can
85 ** issue the End Of Interrupt command to the IO-SAPIC.
86 **
87 ** Overview of exported iosapic functions
88 ** --------------------------------------
89 ** (caveat: code isn't finished yet - this is just the plan)
90 **
91 ** iosapic_init:
92 ** o initialize globals (lock, etc)
93 ** o try to read IRT. Presence of IRT determines if this is
94 ** a PAT platform or not.
95 **
96 ** iosapic_register():
97 ** o create iosapic_info instance data structure
98 ** o allocate vector_info array for this iosapic
99 ** o initialize vector_info - read corresponding IRdT?
100 **
101 ** iosapic_xlate_pin: (only called by fixup_irq for PAT platform)
102 ** o intr_pin = read cfg (INTERRUPT_PIN);
103 ** o if (device under PCI-PCI bridge)
104 ** translate slot/pin
105 **
106 ** iosapic_fixup_irq:
107 ** o if PAT platform (IRT present)
108 ** intr_pin = iosapic_xlate_pin(isi,pcidev):
109 ** intr_line = find IRT entry(isi, PCI_SLOT(pcidev), intr_pin)
110 ** save IRT entry into vector_info later
111 ** write cfg INTERRUPT_LINE (with intr_line)?
112 ** else
113 ** intr_line = pcidev->irq
114 ** IRT pointer = NULL
115 ** endif
116 ** o locate vector_info (needs: isi, intr_line)
117 ** o allocate processor "irq" and get txn_addr/data
118 ** o request_irq(processor_irq, iosapic_interrupt, vector_info,...)
119 **
120 ** iosapic_enable_irq:
121 ** o clear any pending IRQ on that line
122 ** o enable IRdT - call enable_irq(vector[line]->processor_irq)
123 ** o write EOI in case line is already asserted.
124 **
125 ** iosapic_disable_irq:
126 ** o disable IRdT - call disable_irq(vector[line]->processor_irq)
127 */
128
129
130 /* FIXME: determine which include files are really needed */
131 #include <linux/types.h>
132 #include <linux/kernel.h>
133 #include <linux/spinlock.h>
134 #include <linux/pci.h>
135 #include <linux/init.h>
136 #include <linux/slab.h>
137 #include <linux/interrupt.h>
138
139 #include <asm/byteorder.h> /* get in-line asm for swab */
140 #include <asm/pdc.h>
141 #include <asm/pdcpat.h>
142 #include <asm/page.h>
143 #include <asm/io.h> /* read/write functions */
144 #ifdef CONFIG_SUPERIO
145 #include <asm/superio.h>
146 #endif
147
148 #include <asm/ropes.h>
149 #include "iosapic_private.h"
150
151 #define MODULE_NAME "iosapic"
152
153 /* "local" compile flags */
154 #undef PCI_BRIDGE_FUNCS
155 #undef DEBUG_IOSAPIC
156 #undef DEBUG_IOSAPIC_IRT
157
158
159 #ifdef DEBUG_IOSAPIC
160 #define DBG(x...) printk(x)
161 #else /* DEBUG_IOSAPIC */
162 #define DBG(x...)
163 #endif /* DEBUG_IOSAPIC */
164
165 #ifdef DEBUG_IOSAPIC_IRT
166 #define DBG_IRT(x...) printk(x)
167 #else
168 #define DBG_IRT(x...)
169 #endif
170
171 #ifdef CONFIG_64BIT
172 #define COMPARE_IRTE_ADDR(irte, hpa) ((irte)->dest_iosapic_addr == (hpa))
173 #else
174 #define COMPARE_IRTE_ADDR(irte, hpa) \
175 ((irte)->dest_iosapic_addr == ((hpa) | 0xffffffff00000000ULL))
176 #endif
177
178 #define IOSAPIC_REG_SELECT 0x00
179 #define IOSAPIC_REG_WINDOW 0x10
180 #define IOSAPIC_REG_EOI 0x40
181
182 #define IOSAPIC_REG_VERSION 0x1
183
184 #define IOSAPIC_IRDT_ENTRY(idx) (0x10+(idx)*2)
185 #define IOSAPIC_IRDT_ENTRY_HI(idx) (0x11+(idx)*2)
186
iosapic_read(void __iomem * iosapic,unsigned int reg)187 static inline unsigned int iosapic_read(void __iomem *iosapic, unsigned int reg)
188 {
189 writel(reg, iosapic + IOSAPIC_REG_SELECT);
190 return readl(iosapic + IOSAPIC_REG_WINDOW);
191 }
192
iosapic_write(void __iomem * iosapic,unsigned int reg,u32 val)193 static inline void iosapic_write(void __iomem *iosapic, unsigned int reg, u32 val)
194 {
195 writel(reg, iosapic + IOSAPIC_REG_SELECT);
196 writel(val, iosapic + IOSAPIC_REG_WINDOW);
197 }
198
199 #define IOSAPIC_VERSION_MASK 0x000000ff
200 #define IOSAPIC_VERSION(ver) ((int) (ver & IOSAPIC_VERSION_MASK))
201
202 #define IOSAPIC_MAX_ENTRY_MASK 0x00ff0000
203 #define IOSAPIC_MAX_ENTRY_SHIFT 0x10
204 #define IOSAPIC_IRDT_MAX_ENTRY(ver) \
205 (int) (((ver) & IOSAPIC_MAX_ENTRY_MASK) >> IOSAPIC_MAX_ENTRY_SHIFT)
206
207 /* bits in the "low" I/O Sapic IRdT entry */
208 #define IOSAPIC_IRDT_ENABLE 0x10000
209 #define IOSAPIC_IRDT_PO_LOW 0x02000
210 #define IOSAPIC_IRDT_LEVEL_TRIG 0x08000
211 #define IOSAPIC_IRDT_MODE_LPRI 0x00100
212
213 /* bits in the "high" I/O Sapic IRdT entry */
214 #define IOSAPIC_IRDT_ID_EID_SHIFT 0x10
215
216
217 static DEFINE_SPINLOCK(iosapic_lock);
218
iosapic_eoi(__le32 __iomem * addr,__le32 data)219 static inline void iosapic_eoi(__le32 __iomem *addr, __le32 data)
220 {
221 __raw_writel((__force u32)data, addr);
222 }
223
224 /*
225 ** REVISIT: future platforms may have more than one IRT.
226 ** If so, the following three fields form a structure which
227 ** then be linked into a list. Names are chosen to make searching
228 ** for them easy - not necessarily accurate (eg "cell").
229 **
230 ** Alternative: iosapic_info could point to the IRT it's in.
231 ** iosapic_register() could search a list of IRT's.
232 */
233 static struct irt_entry *irt_cell;
234 static size_t irt_num_entry;
235
iosapic_alloc_irt(int num_entries)236 static struct irt_entry *iosapic_alloc_irt(int num_entries)
237 {
238 unsigned long a;
239
240 /* The IRT needs to be 8-byte aligned for the PDC call.
241 * Normally kmalloc would guarantee larger alignment, but
242 * if CONFIG_DEBUG_SLAB is enabled, then we can get only
243 * 4-byte alignment on 32-bit kernels
244 */
245 a = (unsigned long)kmalloc(sizeof(struct irt_entry) * num_entries + 8, GFP_KERNEL);
246 a = (a + 7UL) & ~7UL;
247 return (struct irt_entry *)a;
248 }
249
250 /**
251 * iosapic_load_irt - Fill in the interrupt routing table
252 * @cell_num: The cell number of the CPU we're currently executing on
253 * @irt: The address to place the new IRT at
254 * @return The number of entries found
255 *
256 * The "Get PCI INT Routing Table Size" option returns the number of
257 * entries in the PCI interrupt routing table for the cell specified
258 * in the cell_number argument. The cell number must be for a cell
259 * within the caller's protection domain.
260 *
261 * The "Get PCI INT Routing Table" option returns, for the cell
262 * specified in the cell_number argument, the PCI interrupt routing
263 * table in the caller allocated memory pointed to by mem_addr.
264 * We assume the IRT only contains entries for I/O SAPIC and
265 * calculate the size based on the size of I/O sapic entries.
266 *
267 * The PCI interrupt routing table entry format is derived from the
268 * IA64 SAL Specification 2.4. The PCI interrupt routing table defines
269 * the routing of PCI interrupt signals between the PCI device output
270 * "pins" and the IO SAPICs' input "lines" (including core I/O PCI
271 * devices). This table does NOT include information for devices/slots
272 * behind PCI to PCI bridges. See PCI to PCI Bridge Architecture Spec.
273 * for the architected method of routing of IRQ's behind PPB's.
274 */
275
276
277 static int __init
iosapic_load_irt(unsigned long cell_num,struct irt_entry ** irt)278 iosapic_load_irt(unsigned long cell_num, struct irt_entry **irt)
279 {
280 long status; /* PDC return value status */
281 struct irt_entry *table; /* start of interrupt routing tbl */
282 unsigned long num_entries = 0UL;
283
284 BUG_ON(!irt);
285
286 if (is_pdc_pat()) {
287 /* Use pat pdc routine to get interrupt routing table size */
288 DBG("calling get_irt_size (cell %ld)\n", cell_num);
289 status = pdc_pat_get_irt_size(&num_entries, cell_num);
290 DBG("get_irt_size: %ld\n", status);
291
292 BUG_ON(status != PDC_OK);
293 BUG_ON(num_entries == 0);
294
295 /*
296 ** allocate memory for interrupt routing table
297 ** This interface isn't really right. We are assuming
298 ** the contents of the table are exclusively
299 ** for I/O sapic devices.
300 */
301 table = iosapic_alloc_irt(num_entries);
302 if (table == NULL) {
303 printk(KERN_WARNING MODULE_NAME ": read_irt : can "
304 "not alloc mem for IRT\n");
305 return 0;
306 }
307
308 /* get PCI INT routing table */
309 status = pdc_pat_get_irt(table, cell_num);
310 DBG("pdc_pat_get_irt: %ld\n", status);
311 WARN_ON(status != PDC_OK);
312 } else {
313 /*
314 ** C3000/J5000 (and similar) platforms with Sprockets PDC
315 ** will return exactly one IRT for all iosapics.
316 ** So if we have one, don't need to get it again.
317 */
318 if (irt_cell)
319 return 0;
320
321 /* Should be using the Elroy's HPA, but it's ignored anyway */
322 status = pdc_pci_irt_size(&num_entries, 0);
323 DBG("pdc_pci_irt_size: %ld\n", status);
324
325 if (status != PDC_OK) {
326 /* Not a "legacy" system with I/O SAPIC either */
327 return 0;
328 }
329
330 BUG_ON(num_entries == 0);
331
332 table = iosapic_alloc_irt(num_entries);
333 if (!table) {
334 printk(KERN_WARNING MODULE_NAME ": read_irt : can "
335 "not alloc mem for IRT\n");
336 return 0;
337 }
338
339 /* HPA ignored by this call too. */
340 status = pdc_pci_irt(num_entries, 0, table);
341 BUG_ON(status != PDC_OK);
342 }
343
344 /* return interrupt table address */
345 *irt = table;
346
347 #ifdef DEBUG_IOSAPIC_IRT
348 {
349 struct irt_entry *p = table;
350 int i;
351
352 printk(MODULE_NAME " Interrupt Routing Table (cell %ld)\n", cell_num);
353 printk(MODULE_NAME " start = 0x%p num_entries %ld entry_size %d\n",
354 table,
355 num_entries,
356 (int) sizeof(struct irt_entry));
357
358 for (i = 0 ; i < num_entries ; i++, p++) {
359 printk(MODULE_NAME " %02x %02x %02x %02x %02x %02x %02x %02x %08x%08x\n",
360 p->entry_type, p->entry_length, p->interrupt_type,
361 p->polarity_trigger, p->src_bus_irq_devno, p->src_bus_id,
362 p->src_seg_id, p->dest_iosapic_intin,
363 ((u32 *) p)[2],
364 ((u32 *) p)[3]
365 );
366 }
367 }
368 #endif /* DEBUG_IOSAPIC_IRT */
369
370 return num_entries;
371 }
372
373
374
iosapic_init(void)375 void __init iosapic_init(void)
376 {
377 unsigned long cell = 0;
378
379 DBG("iosapic_init()\n");
380
381 #ifdef __LP64__
382 if (is_pdc_pat()) {
383 int status;
384 struct pdc_pat_cell_num cell_info;
385
386 status = pdc_pat_cell_get_number(&cell_info);
387 if (status == PDC_OK) {
388 cell = cell_info.cell_num;
389 }
390 }
391 #endif
392
393 /* get interrupt routing table for this cell */
394 irt_num_entry = iosapic_load_irt(cell, &irt_cell);
395 if (irt_num_entry == 0)
396 irt_cell = NULL; /* old PDC w/o iosapic */
397 }
398
399
400 /*
401 ** Return the IRT entry in case we need to look something else up.
402 */
403 static struct irt_entry *
irt_find_irqline(struct iosapic_info * isi,u8 slot,u8 intr_pin)404 irt_find_irqline(struct iosapic_info *isi, u8 slot, u8 intr_pin)
405 {
406 struct irt_entry *i = irt_cell;
407 int cnt; /* track how many entries we've looked at */
408 u8 irq_devno = (slot << IRT_DEV_SHIFT) | (intr_pin-1);
409
410 DBG_IRT("irt_find_irqline() SLOT %d pin %d\n", slot, intr_pin);
411
412 for (cnt=0; cnt < irt_num_entry; cnt++, i++) {
413
414 /*
415 ** Validate: entry_type, entry_length, interrupt_type
416 **
417 ** Difference between validate vs compare is the former
418 ** should print debug info and is not expected to "fail"
419 ** on current platforms.
420 */
421 if (i->entry_type != IRT_IOSAPIC_TYPE) {
422 DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d type %d\n", i, cnt, i->entry_type);
423 continue;
424 }
425
426 if (i->entry_length != IRT_IOSAPIC_LENGTH) {
427 DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d length %d\n", i, cnt, i->entry_length);
428 continue;
429 }
430
431 if (i->interrupt_type != IRT_VECTORED_INTR) {
432 DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d interrupt_type %d\n", i, cnt, i->interrupt_type);
433 continue;
434 }
435
436 if (!COMPARE_IRTE_ADDR(i, isi->isi_hpa))
437 continue;
438
439 if ((i->src_bus_irq_devno & IRT_IRQ_DEVNO_MASK) != irq_devno)
440 continue;
441
442 /*
443 ** Ignore: src_bus_id and rc_seg_id correlate with
444 ** iosapic_info->isi_hpa on HP platforms.
445 ** If needed, pass in "PFA" (aka config space addr)
446 ** instead of slot.
447 */
448
449 /* Found it! */
450 return i;
451 }
452
453 printk(KERN_WARNING MODULE_NAME ": 0x%lx : no IRT entry for slot %d, pin %d\n",
454 isi->isi_hpa, slot, intr_pin);
455 return NULL;
456 }
457
458
459 /*
460 ** xlate_pin() supports the skewing of IRQ lines done by subsidiary bridges.
461 ** Legacy PDC already does this translation for us and stores it in INTR_LINE.
462 **
463 ** PAT PDC needs to basically do what legacy PDC does:
464 ** o read PIN
465 ** o adjust PIN in case device is "behind" a PPB
466 ** (eg 4-port 100BT and SCSI/LAN "Combo Card")
467 ** o convert slot/pin to I/O SAPIC input line.
468 **
469 ** HP platforms only support:
470 ** o one level of skewing for any number of PPBs
471 ** o only support PCI-PCI Bridges.
472 */
473 static struct irt_entry *
iosapic_xlate_pin(struct iosapic_info * isi,struct pci_dev * pcidev)474 iosapic_xlate_pin(struct iosapic_info *isi, struct pci_dev *pcidev)
475 {
476 u8 intr_pin, intr_slot;
477
478 pci_read_config_byte(pcidev, PCI_INTERRUPT_PIN, &intr_pin);
479
480 DBG_IRT("iosapic_xlate_pin(%s) SLOT %d pin %d\n",
481 pcidev->slot_name, PCI_SLOT(pcidev->devfn), intr_pin);
482
483 if (intr_pin == 0) {
484 /* The device does NOT support/use IRQ lines. */
485 return NULL;
486 }
487
488 /* Check if pcidev behind a PPB */
489 if (pcidev->bus->parent) {
490 /* Convert pcidev INTR_PIN into something we
491 ** can lookup in the IRT.
492 */
493 #ifdef PCI_BRIDGE_FUNCS
494 /*
495 ** Proposal #1:
496 **
497 ** call implementation specific translation function
498 ** This is architecturally "cleaner". HP-UX doesn't
499 ** support other secondary bus types (eg. E/ISA) directly.
500 ** May be needed for other processor (eg IA64) architectures
501 ** or by some ambitous soul who wants to watch TV.
502 */
503 if (pci_bridge_funcs->xlate_intr_line) {
504 intr_pin = pci_bridge_funcs->xlate_intr_line(pcidev);
505 }
506 #else /* PCI_BRIDGE_FUNCS */
507 struct pci_bus *p = pcidev->bus;
508 /*
509 ** Proposal #2:
510 ** The "pin" is skewed ((pin + dev - 1) % 4).
511 **
512 ** This isn't very clean since I/O SAPIC must assume:
513 ** - all platforms only have PCI busses.
514 ** - only PCI-PCI bridge (eg not PCI-EISA, PCI-PCMCIA)
515 ** - IRQ routing is only skewed once regardless of
516 ** the number of PPB's between iosapic and device.
517 ** (Bit3 expansion chassis follows this rule)
518 **
519 ** Advantage is it's really easy to implement.
520 */
521 intr_pin = pci_swizzle_interrupt_pin(pcidev, intr_pin);
522 #endif /* PCI_BRIDGE_FUNCS */
523
524 /*
525 * Locate the host slot of the PPB.
526 */
527 while (p->parent->parent)
528 p = p->parent;
529
530 intr_slot = PCI_SLOT(p->self->devfn);
531 } else {
532 intr_slot = PCI_SLOT(pcidev->devfn);
533 }
534 DBG_IRT("iosapic_xlate_pin: bus %d slot %d pin %d\n",
535 pcidev->bus->busn_res.start, intr_slot, intr_pin);
536
537 return irt_find_irqline(isi, intr_slot, intr_pin);
538 }
539
iosapic_rd_irt_entry(struct vector_info * vi,u32 * dp0,u32 * dp1)540 static void iosapic_rd_irt_entry(struct vector_info *vi , u32 *dp0, u32 *dp1)
541 {
542 struct iosapic_info *isp = vi->iosapic;
543 u8 idx = vi->irqline;
544
545 *dp0 = iosapic_read(isp->addr, IOSAPIC_IRDT_ENTRY(idx));
546 *dp1 = iosapic_read(isp->addr, IOSAPIC_IRDT_ENTRY_HI(idx));
547 }
548
549
iosapic_wr_irt_entry(struct vector_info * vi,u32 dp0,u32 dp1)550 static void iosapic_wr_irt_entry(struct vector_info *vi, u32 dp0, u32 dp1)
551 {
552 struct iosapic_info *isp = vi->iosapic;
553
554 DBG_IRT("iosapic_wr_irt_entry(): irq %d hpa %lx 0x%x 0x%x\n",
555 vi->irqline, isp->isi_hpa, dp0, dp1);
556
557 iosapic_write(isp->addr, IOSAPIC_IRDT_ENTRY(vi->irqline), dp0);
558
559 /* Read the window register to flush the writes down to HW */
560 dp0 = readl(isp->addr+IOSAPIC_REG_WINDOW);
561
562 iosapic_write(isp->addr, IOSAPIC_IRDT_ENTRY_HI(vi->irqline), dp1);
563
564 /* Read the window register to flush the writes down to HW */
565 dp1 = readl(isp->addr+IOSAPIC_REG_WINDOW);
566 }
567
568 /*
569 ** set_irt prepares the data (dp0, dp1) according to the vector_info
570 ** and target cpu (id_eid). dp0/dp1 are then used to program I/O SAPIC
571 ** IRdT for the given "vector" (aka IRQ line).
572 */
573 static void
iosapic_set_irt_data(struct vector_info * vi,u32 * dp0,u32 * dp1)574 iosapic_set_irt_data( struct vector_info *vi, u32 *dp0, u32 *dp1)
575 {
576 u32 mode = 0;
577 struct irt_entry *p = vi->irte;
578
579 if ((p->polarity_trigger & IRT_PO_MASK) == IRT_ACTIVE_LO)
580 mode |= IOSAPIC_IRDT_PO_LOW;
581
582 if (((p->polarity_trigger >> IRT_EL_SHIFT) & IRT_EL_MASK) == IRT_LEVEL_TRIG)
583 mode |= IOSAPIC_IRDT_LEVEL_TRIG;
584
585 /*
586 ** IA64 REVISIT
587 ** PA doesn't support EXTINT or LPRIO bits.
588 */
589
590 *dp0 = mode | (u32) vi->txn_data;
591
592 /*
593 ** Extracting id_eid isn't a real clean way of getting it.
594 ** But the encoding is the same for both PA and IA64 platforms.
595 */
596 if (is_pdc_pat()) {
597 /*
598 ** PAT PDC just hands it to us "right".
599 ** txn_addr comes from cpu_data[x].txn_addr.
600 */
601 *dp1 = (u32) (vi->txn_addr);
602 } else {
603 /*
604 ** eg if base_addr == 0xfffa0000),
605 ** we want to get 0xa0ff0000.
606 **
607 ** eid 0x0ff00000 -> 0x00ff0000
608 ** id 0x000ff000 -> 0xff000000
609 */
610 *dp1 = (((u32)vi->txn_addr & 0x0ff00000) >> 4) |
611 (((u32)vi->txn_addr & 0x000ff000) << 12);
612 }
613 DBG_IRT("iosapic_set_irt_data(): 0x%x 0x%x\n", *dp0, *dp1);
614 }
615
616
iosapic_mask_irq(struct irq_data * d)617 static void iosapic_mask_irq(struct irq_data *d)
618 {
619 unsigned long flags;
620 struct vector_info *vi = irq_data_get_irq_chip_data(d);
621 u32 d0, d1;
622
623 spin_lock_irqsave(&iosapic_lock, flags);
624 iosapic_rd_irt_entry(vi, &d0, &d1);
625 d0 |= IOSAPIC_IRDT_ENABLE;
626 iosapic_wr_irt_entry(vi, d0, d1);
627 spin_unlock_irqrestore(&iosapic_lock, flags);
628 }
629
iosapic_unmask_irq(struct irq_data * d)630 static void iosapic_unmask_irq(struct irq_data *d)
631 {
632 struct vector_info *vi = irq_data_get_irq_chip_data(d);
633 u32 d0, d1;
634
635 /* data is initialized by fixup_irq */
636 WARN_ON(vi->txn_irq == 0);
637
638 iosapic_set_irt_data(vi, &d0, &d1);
639 iosapic_wr_irt_entry(vi, d0, d1);
640
641 #ifdef DEBUG_IOSAPIC_IRT
642 {
643 u32 *t = (u32 *) ((ulong) vi->eoi_addr & ~0xffUL);
644 printk("iosapic_enable_irq(): regs %p", vi->eoi_addr);
645 for ( ; t < vi->eoi_addr; t++)
646 printk(" %x", readl(t));
647 printk("\n");
648 }
649
650 printk("iosapic_enable_irq(): sel ");
651 {
652 struct iosapic_info *isp = vi->iosapic;
653
654 for (d0=0x10; d0<0x1e; d0++) {
655 d1 = iosapic_read(isp->addr, d0);
656 printk(" %x", d1);
657 }
658 }
659 printk("\n");
660 #endif
661
662 /*
663 * Issuing I/O SAPIC an EOI causes an interrupt IFF IRQ line is
664 * asserted. IRQ generally should not be asserted when a driver
665 * enables their IRQ. It can lead to "interesting" race conditions
666 * in the driver initialization sequence.
667 */
668 DBG(KERN_DEBUG "enable_irq(%d): eoi(%p, 0x%x)\n", d->irq,
669 vi->eoi_addr, vi->eoi_data);
670 iosapic_eoi(vi->eoi_addr, vi->eoi_data);
671 }
672
iosapic_eoi_irq(struct irq_data * d)673 static void iosapic_eoi_irq(struct irq_data *d)
674 {
675 struct vector_info *vi = irq_data_get_irq_chip_data(d);
676
677 iosapic_eoi(vi->eoi_addr, vi->eoi_data);
678 cpu_eoi_irq(d);
679 }
680
681 #ifdef CONFIG_SMP
iosapic_set_affinity_irq(struct irq_data * d,const struct cpumask * dest,bool force)682 static int iosapic_set_affinity_irq(struct irq_data *d,
683 const struct cpumask *dest, bool force)
684 {
685 struct vector_info *vi = irq_data_get_irq_chip_data(d);
686 u32 d0, d1, dummy_d0;
687 unsigned long flags;
688 int dest_cpu;
689
690 dest_cpu = cpu_check_affinity(d, dest);
691 if (dest_cpu < 0)
692 return -1;
693
694 cpumask_copy(irq_data_get_affinity_mask(d), cpumask_of(dest_cpu));
695 vi->txn_addr = txn_affinity_addr(d->irq, dest_cpu);
696
697 spin_lock_irqsave(&iosapic_lock, flags);
698 /* d1 contains the destination CPU, so only want to set that
699 * entry */
700 iosapic_rd_irt_entry(vi, &d0, &d1);
701 iosapic_set_irt_data(vi, &dummy_d0, &d1);
702 iosapic_wr_irt_entry(vi, d0, d1);
703 spin_unlock_irqrestore(&iosapic_lock, flags);
704
705 return 0;
706 }
707 #endif
708
709 static struct irq_chip iosapic_interrupt_type = {
710 .name = "IO-SAPIC-level",
711 .irq_unmask = iosapic_unmask_irq,
712 .irq_mask = iosapic_mask_irq,
713 .irq_ack = cpu_ack_irq,
714 .irq_eoi = iosapic_eoi_irq,
715 #ifdef CONFIG_SMP
716 .irq_set_affinity = iosapic_set_affinity_irq,
717 #endif
718 };
719
iosapic_fixup_irq(void * isi_obj,struct pci_dev * pcidev)720 int iosapic_fixup_irq(void *isi_obj, struct pci_dev *pcidev)
721 {
722 struct iosapic_info *isi = isi_obj;
723 struct irt_entry *irte = NULL; /* only used if PAT PDC */
724 struct vector_info *vi;
725 int isi_line; /* line used by device */
726
727 if (!isi) {
728 printk(KERN_WARNING MODULE_NAME ": hpa not registered for %s\n",
729 pci_name(pcidev));
730 return -1;
731 }
732
733 #ifdef CONFIG_SUPERIO
734 /*
735 * HACK ALERT! (non-compliant PCI device support)
736 *
737 * All SuckyIO interrupts are routed through the PIC's on function 1.
738 * But SuckyIO OHCI USB controller gets an IRT entry anyway because
739 * it advertises INT D for INT_PIN. Use that IRT entry to get the
740 * SuckyIO interrupt routing for PICs on function 1 (*BLEECCHH*).
741 */
742 if (is_superio_device(pcidev)) {
743 /* We must call superio_fixup_irq() to register the pdev */
744 pcidev->irq = superio_fixup_irq(pcidev);
745
746 /* Don't return if need to program the IOSAPIC's IRT... */
747 if (PCI_FUNC(pcidev->devfn) != SUPERIO_USB_FN)
748 return pcidev->irq;
749 }
750 #endif /* CONFIG_SUPERIO */
751
752 /* lookup IRT entry for isi/slot/pin set */
753 irte = iosapic_xlate_pin(isi, pcidev);
754 if (!irte) {
755 printk("iosapic: no IRTE for %s (IRQ not connected?)\n",
756 pci_name(pcidev));
757 return -1;
758 }
759 DBG_IRT("iosapic_fixup_irq(): irte %p %x %x %x %x %x %x %x %x\n",
760 irte,
761 irte->entry_type,
762 irte->entry_length,
763 irte->polarity_trigger,
764 irte->src_bus_irq_devno,
765 irte->src_bus_id,
766 irte->src_seg_id,
767 irte->dest_iosapic_intin,
768 (u32) irte->dest_iosapic_addr);
769 isi_line = irte->dest_iosapic_intin;
770
771 /* get vector info for this input line */
772 vi = isi->isi_vector + isi_line;
773 DBG_IRT("iosapic_fixup_irq: line %d vi 0x%p\n", isi_line, vi);
774
775 /* If this IRQ line has already been setup, skip it */
776 if (vi->irte)
777 goto out;
778
779 vi->irte = irte;
780
781 /*
782 * Allocate processor IRQ
783 *
784 * XXX/FIXME The txn_alloc_irq() code and related code should be
785 * moved to enable_irq(). That way we only allocate processor IRQ
786 * bits for devices that actually have drivers claiming them.
787 * Right now we assign an IRQ to every PCI device present,
788 * regardless of whether it's used or not.
789 */
790 vi->txn_irq = txn_alloc_irq(8);
791
792 if (vi->txn_irq < 0)
793 panic("I/O sapic: couldn't get TXN IRQ\n");
794
795 /* enable_irq() will use txn_* to program IRdT */
796 vi->txn_addr = txn_alloc_addr(vi->txn_irq);
797 vi->txn_data = txn_alloc_data(vi->txn_irq);
798
799 vi->eoi_addr = isi->addr + IOSAPIC_REG_EOI;
800 vi->eoi_data = cpu_to_le32(vi->txn_data);
801
802 cpu_claim_irq(vi->txn_irq, &iosapic_interrupt_type, vi);
803
804 out:
805 pcidev->irq = vi->txn_irq;
806
807 DBG_IRT("iosapic_fixup_irq() %d:%d %x %x line %d irq %d\n",
808 PCI_SLOT(pcidev->devfn), PCI_FUNC(pcidev->devfn),
809 pcidev->vendor, pcidev->device, isi_line, pcidev->irq);
810
811 return pcidev->irq;
812 }
813
814 static struct iosapic_info *iosapic_list;
815
816 #ifdef CONFIG_64BIT
iosapic_serial_irq(struct parisc_device * dev)817 int iosapic_serial_irq(struct parisc_device *dev)
818 {
819 struct iosapic_info *isi;
820 struct irt_entry *irte;
821 struct vector_info *vi;
822 int cnt;
823 int intin;
824
825 intin = (dev->mod_info >> 24) & 15;
826
827 /* lookup IRT entry for isi/slot/pin set */
828 for (cnt = 0; cnt < irt_num_entry; cnt++) {
829 irte = &irt_cell[cnt];
830 if (COMPARE_IRTE_ADDR(irte, dev->mod0) &&
831 irte->dest_iosapic_intin == intin)
832 break;
833 }
834 if (cnt >= irt_num_entry)
835 return 0; /* no irq found, force polling */
836
837 DBG_IRT("iosapic_serial_irq(): irte %p %x %x %x %x %x %x %x %x\n",
838 irte,
839 irte->entry_type,
840 irte->entry_length,
841 irte->polarity_trigger,
842 irte->src_bus_irq_devno,
843 irte->src_bus_id,
844 irte->src_seg_id,
845 irte->dest_iosapic_intin,
846 (u32) irte->dest_iosapic_addr);
847
848 /* search for iosapic */
849 for (isi = iosapic_list; isi; isi = isi->isi_next)
850 if (isi->isi_hpa == dev->mod0)
851 break;
852 if (!isi)
853 return 0; /* no iosapic found, force polling */
854
855 /* get vector info for this input line */
856 vi = isi->isi_vector + intin;
857 DBG_IRT("iosapic_serial_irq: line %d vi 0x%p\n", iosapic_intin, vi);
858
859 /* If this IRQ line has already been setup, skip it */
860 if (vi->irte)
861 goto out;
862
863 vi->irte = irte;
864
865 /*
866 * Allocate processor IRQ
867 *
868 * XXX/FIXME The txn_alloc_irq() code and related code should be
869 * moved to enable_irq(). That way we only allocate processor IRQ
870 * bits for devices that actually have drivers claiming them.
871 * Right now we assign an IRQ to every PCI device present,
872 * regardless of whether it's used or not.
873 */
874 vi->txn_irq = txn_alloc_irq(8);
875
876 if (vi->txn_irq < 0)
877 panic("I/O sapic: couldn't get TXN IRQ\n");
878
879 /* enable_irq() will use txn_* to program IRdT */
880 vi->txn_addr = txn_alloc_addr(vi->txn_irq);
881 vi->txn_data = txn_alloc_data(vi->txn_irq);
882
883 vi->eoi_addr = isi->addr + IOSAPIC_REG_EOI;
884 vi->eoi_data = cpu_to_le32(vi->txn_data);
885
886 cpu_claim_irq(vi->txn_irq, &iosapic_interrupt_type, vi);
887
888 out:
889
890 return vi->txn_irq;
891 }
892 EXPORT_SYMBOL(iosapic_serial_irq);
893 #endif
894
895
896 /*
897 ** squirrel away the I/O Sapic Version
898 */
899 static unsigned int
iosapic_rd_version(struct iosapic_info * isi)900 iosapic_rd_version(struct iosapic_info *isi)
901 {
902 return iosapic_read(isi->addr, IOSAPIC_REG_VERSION);
903 }
904
905
906 /*
907 ** iosapic_register() is called by "drivers" with an integrated I/O SAPIC.
908 ** Caller must be certain they have an I/O SAPIC and know its MMIO address.
909 **
910 ** o allocate iosapic_info and add it to the list
911 ** o read iosapic version and squirrel that away
912 ** o read size of IRdT.
913 ** o allocate and initialize isi_vector[]
914 ** o allocate irq region
915 */
iosapic_register(unsigned long hpa)916 void *iosapic_register(unsigned long hpa)
917 {
918 struct iosapic_info *isi = NULL;
919 struct irt_entry *irte = irt_cell;
920 struct vector_info *vip;
921 int cnt; /* track how many entries we've looked at */
922
923 /*
924 * Astro based platforms can only support PCI OLARD if they implement
925 * PAT PDC. Legacy PDC omits LBAs with no PCI devices from the IRT.
926 * Search the IRT and ignore iosapic's which aren't in the IRT.
927 */
928 for (cnt=0; cnt < irt_num_entry; cnt++, irte++) {
929 WARN_ON(IRT_IOSAPIC_TYPE != irte->entry_type);
930 if (COMPARE_IRTE_ADDR(irte, hpa))
931 break;
932 }
933
934 if (cnt >= irt_num_entry) {
935 DBG("iosapic_register() ignoring 0x%lx (NOT FOUND)\n", hpa);
936 return NULL;
937 }
938
939 isi = kzalloc(sizeof(struct iosapic_info), GFP_KERNEL);
940 if (!isi) {
941 BUG();
942 return NULL;
943 }
944
945 isi->addr = ioremap_nocache(hpa, 4096);
946 isi->isi_hpa = hpa;
947 isi->isi_version = iosapic_rd_version(isi);
948 isi->isi_num_vectors = IOSAPIC_IRDT_MAX_ENTRY(isi->isi_version) + 1;
949
950 vip = isi->isi_vector = kcalloc(isi->isi_num_vectors,
951 sizeof(struct vector_info), GFP_KERNEL);
952 if (vip == NULL) {
953 kfree(isi);
954 return NULL;
955 }
956
957 for (cnt=0; cnt < isi->isi_num_vectors; cnt++, vip++) {
958 vip->irqline = (unsigned char) cnt;
959 vip->iosapic = isi;
960 }
961 isi->isi_next = iosapic_list;
962 iosapic_list = isi;
963 return isi;
964 }
965
966
967 #ifdef DEBUG_IOSAPIC
968
969 static void
iosapic_prt_irt(void * irt,long num_entry)970 iosapic_prt_irt(void *irt, long num_entry)
971 {
972 unsigned int i, *irp = (unsigned int *) irt;
973
974
975 printk(KERN_DEBUG MODULE_NAME ": Interrupt Routing Table (%lx entries)\n", num_entry);
976
977 for (i=0; i<num_entry; i++, irp += 4) {
978 printk(KERN_DEBUG "%p : %2d %.8x %.8x %.8x %.8x\n",
979 irp, i, irp[0], irp[1], irp[2], irp[3]);
980 }
981 }
982
983
984 static void
iosapic_prt_vi(struct vector_info * vi)985 iosapic_prt_vi(struct vector_info *vi)
986 {
987 printk(KERN_DEBUG MODULE_NAME ": vector_info[%d] is at %p\n", vi->irqline, vi);
988 printk(KERN_DEBUG "\t\tstatus: %.4x\n", vi->status);
989 printk(KERN_DEBUG "\t\ttxn_irq: %d\n", vi->txn_irq);
990 printk(KERN_DEBUG "\t\ttxn_addr: %lx\n", vi->txn_addr);
991 printk(KERN_DEBUG "\t\ttxn_data: %lx\n", vi->txn_data);
992 printk(KERN_DEBUG "\t\teoi_addr: %p\n", vi->eoi_addr);
993 printk(KERN_DEBUG "\t\teoi_data: %x\n", vi->eoi_data);
994 }
995
996
997 static void
iosapic_prt_isi(struct iosapic_info * isi)998 iosapic_prt_isi(struct iosapic_info *isi)
999 {
1000 printk(KERN_DEBUG MODULE_NAME ": io_sapic_info at %p\n", isi);
1001 printk(KERN_DEBUG "\t\tisi_hpa: %lx\n", isi->isi_hpa);
1002 printk(KERN_DEBUG "\t\tisi_status: %x\n", isi->isi_status);
1003 printk(KERN_DEBUG "\t\tisi_version: %x\n", isi->isi_version);
1004 printk(KERN_DEBUG "\t\tisi_vector: %p\n", isi->isi_vector);
1005 }
1006 #endif /* DEBUG_IOSAPIC */
1007