1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * This file contains work-arounds for many known PCI hardware bugs.
4 * Devices present only on certain architectures (host bridges et cetera)
5 * should be handled in arch-specific code.
6 *
7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 *
9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 *
11 * Init/reset quirks for USB host controllers should be in the USB quirks
12 * file, where their drivers can use them.
13 */
14
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/export.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/acpi.h>
22 #include <linux/dmi.h>
23 #include <linux/pci-aspm.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/ktime.h>
27 #include <linux/mm.h>
28 #include <linux/nvme.h>
29 #include <linux/platform_data/x86/apple.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/suspend.h>
32 #include <linux/switchtec.h>
33 #include <asm/dma.h> /* isa_dma_bridge_buggy */
34 #include "pci.h"
35
fixup_debug_start(struct pci_dev * dev,void (* fn)(struct pci_dev * dev))36 static ktime_t fixup_debug_start(struct pci_dev *dev,
37 void (*fn)(struct pci_dev *dev))
38 {
39 if (initcall_debug)
40 pci_info(dev, "calling %pF @ %i\n", fn, task_pid_nr(current));
41
42 return ktime_get();
43 }
44
fixup_debug_report(struct pci_dev * dev,ktime_t calltime,void (* fn)(struct pci_dev * dev))45 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
46 void (*fn)(struct pci_dev *dev))
47 {
48 ktime_t delta, rettime;
49 unsigned long long duration;
50
51 rettime = ktime_get();
52 delta = ktime_sub(rettime, calltime);
53 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
54 if (initcall_debug || duration > 10000)
55 pci_info(dev, "%pF took %lld usecs\n", fn, duration);
56 }
57
pci_do_fixups(struct pci_dev * dev,struct pci_fixup * f,struct pci_fixup * end)58 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
59 struct pci_fixup *end)
60 {
61 ktime_t calltime;
62
63 for (; f < end; f++)
64 if ((f->class == (u32) (dev->class >> f->class_shift) ||
65 f->class == (u32) PCI_ANY_ID) &&
66 (f->vendor == dev->vendor ||
67 f->vendor == (u16) PCI_ANY_ID) &&
68 (f->device == dev->device ||
69 f->device == (u16) PCI_ANY_ID)) {
70 void (*hook)(struct pci_dev *dev);
71 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
72 hook = offset_to_ptr(&f->hook_offset);
73 #else
74 hook = f->hook;
75 #endif
76 calltime = fixup_debug_start(dev, hook);
77 hook(dev);
78 fixup_debug_report(dev, calltime, hook);
79 }
80 }
81
82 extern struct pci_fixup __start_pci_fixups_early[];
83 extern struct pci_fixup __end_pci_fixups_early[];
84 extern struct pci_fixup __start_pci_fixups_header[];
85 extern struct pci_fixup __end_pci_fixups_header[];
86 extern struct pci_fixup __start_pci_fixups_final[];
87 extern struct pci_fixup __end_pci_fixups_final[];
88 extern struct pci_fixup __start_pci_fixups_enable[];
89 extern struct pci_fixup __end_pci_fixups_enable[];
90 extern struct pci_fixup __start_pci_fixups_resume[];
91 extern struct pci_fixup __end_pci_fixups_resume[];
92 extern struct pci_fixup __start_pci_fixups_resume_early[];
93 extern struct pci_fixup __end_pci_fixups_resume_early[];
94 extern struct pci_fixup __start_pci_fixups_suspend[];
95 extern struct pci_fixup __end_pci_fixups_suspend[];
96 extern struct pci_fixup __start_pci_fixups_suspend_late[];
97 extern struct pci_fixup __end_pci_fixups_suspend_late[];
98
99 static bool pci_apply_fixup_final_quirks;
100
pci_fixup_device(enum pci_fixup_pass pass,struct pci_dev * dev)101 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
102 {
103 struct pci_fixup *start, *end;
104
105 switch (pass) {
106 case pci_fixup_early:
107 start = __start_pci_fixups_early;
108 end = __end_pci_fixups_early;
109 break;
110
111 case pci_fixup_header:
112 start = __start_pci_fixups_header;
113 end = __end_pci_fixups_header;
114 break;
115
116 case pci_fixup_final:
117 if (!pci_apply_fixup_final_quirks)
118 return;
119 start = __start_pci_fixups_final;
120 end = __end_pci_fixups_final;
121 break;
122
123 case pci_fixup_enable:
124 start = __start_pci_fixups_enable;
125 end = __end_pci_fixups_enable;
126 break;
127
128 case pci_fixup_resume:
129 start = __start_pci_fixups_resume;
130 end = __end_pci_fixups_resume;
131 break;
132
133 case pci_fixup_resume_early:
134 start = __start_pci_fixups_resume_early;
135 end = __end_pci_fixups_resume_early;
136 break;
137
138 case pci_fixup_suspend:
139 start = __start_pci_fixups_suspend;
140 end = __end_pci_fixups_suspend;
141 break;
142
143 case pci_fixup_suspend_late:
144 start = __start_pci_fixups_suspend_late;
145 end = __end_pci_fixups_suspend_late;
146 break;
147
148 default:
149 /* stupid compiler warning, you would think with an enum... */
150 return;
151 }
152 pci_do_fixups(dev, start, end);
153 }
154 EXPORT_SYMBOL(pci_fixup_device);
155
pci_apply_final_quirks(void)156 static int __init pci_apply_final_quirks(void)
157 {
158 struct pci_dev *dev = NULL;
159 u8 cls = 0;
160 u8 tmp;
161
162 if (pci_cache_line_size)
163 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
164 pci_cache_line_size << 2);
165
166 pci_apply_fixup_final_quirks = true;
167 for_each_pci_dev(dev) {
168 pci_fixup_device(pci_fixup_final, dev);
169 /*
170 * If arch hasn't set it explicitly yet, use the CLS
171 * value shared by all PCI devices. If there's a
172 * mismatch, fall back to the default value.
173 */
174 if (!pci_cache_line_size) {
175 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
176 if (!cls)
177 cls = tmp;
178 if (!tmp || cls == tmp)
179 continue;
180
181 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
182 cls << 2, tmp << 2,
183 pci_dfl_cache_line_size << 2);
184 pci_cache_line_size = pci_dfl_cache_line_size;
185 }
186 }
187
188 if (!pci_cache_line_size) {
189 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
190 cls << 2, pci_dfl_cache_line_size << 2);
191 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
192 }
193
194 return 0;
195 }
196 fs_initcall_sync(pci_apply_final_quirks);
197
198 /*
199 * Decoding should be disabled for a PCI device during BAR sizing to avoid
200 * conflict. But doing so may cause problems on host bridge and perhaps other
201 * key system devices. For devices that need to have mmio decoding always-on,
202 * we need to set the dev->mmio_always_on bit.
203 */
quirk_mmio_always_on(struct pci_dev * dev)204 static void quirk_mmio_always_on(struct pci_dev *dev)
205 {
206 dev->mmio_always_on = 1;
207 }
208 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
209 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
210
211 /*
212 * The Mellanox Tavor device gives false positive parity errors. Mark this
213 * device with a broken_parity_status to allow PCI scanning code to "skip"
214 * this now blacklisted device.
215 */
quirk_mellanox_tavor(struct pci_dev * dev)216 static void quirk_mellanox_tavor(struct pci_dev *dev)
217 {
218 dev->broken_parity_status = 1; /* This device gives false positives */
219 }
220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
222
223 /*
224 * Deal with broken BIOSes that neglect to enable passive release,
225 * which can cause problems in combination with the 82441FX/PPro MTRRs
226 */
quirk_passive_release(struct pci_dev * dev)227 static void quirk_passive_release(struct pci_dev *dev)
228 {
229 struct pci_dev *d = NULL;
230 unsigned char dlc;
231
232 /*
233 * We have to make sure a particular bit is set in the PIIX3
234 * ISA bridge, so we have to go out and find it.
235 */
236 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
237 pci_read_config_byte(d, 0x82, &dlc);
238 if (!(dlc & 1<<1)) {
239 pci_info(d, "PIIX3: Enabling Passive Release\n");
240 dlc |= 1<<1;
241 pci_write_config_byte(d, 0x82, dlc);
242 }
243 }
244 }
245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
246 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
247
248 /*
249 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
250 * workaround but VIA don't answer queries. If you happen to have good
251 * contacts at VIA ask them for me please -- Alan
252 *
253 * This appears to be BIOS not version dependent. So presumably there is a
254 * chipset level fix.
255 */
quirk_isa_dma_hangs(struct pci_dev * dev)256 static void quirk_isa_dma_hangs(struct pci_dev *dev)
257 {
258 if (!isa_dma_bridge_buggy) {
259 isa_dma_bridge_buggy = 1;
260 pci_info(dev, "Activating ISA DMA hang workarounds\n");
261 }
262 }
263 /*
264 * It's not totally clear which chipsets are the problematic ones. We know
265 * 82C586 and 82C596 variants are affected.
266 */
267 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
268 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
269 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
270 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
271 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
272 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
273 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
274
275 /*
276 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
277 * for some HT machines to use C4 w/o hanging.
278 */
quirk_tigerpoint_bm_sts(struct pci_dev * dev)279 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
280 {
281 u32 pmbase;
282 u16 pm1a;
283
284 pci_read_config_dword(dev, 0x40, &pmbase);
285 pmbase = pmbase & 0xff80;
286 pm1a = inw(pmbase);
287
288 if (pm1a & 0x10) {
289 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
290 outw(0x10, pmbase);
291 }
292 }
293 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
294
295 /* Chipsets where PCI->PCI transfers vanish or hang */
quirk_nopcipci(struct pci_dev * dev)296 static void quirk_nopcipci(struct pci_dev *dev)
297 {
298 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
299 pci_info(dev, "Disabling direct PCI/PCI transfers\n");
300 pci_pci_problems |= PCIPCI_FAIL;
301 }
302 }
303 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
304 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
305
quirk_nopciamd(struct pci_dev * dev)306 static void quirk_nopciamd(struct pci_dev *dev)
307 {
308 u8 rev;
309 pci_read_config_byte(dev, 0x08, &rev);
310 if (rev == 0x13) {
311 /* Erratum 24 */
312 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
313 pci_pci_problems |= PCIAGP_FAIL;
314 }
315 }
316 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
317
318 /* Triton requires workarounds to be used by the drivers */
quirk_triton(struct pci_dev * dev)319 static void quirk_triton(struct pci_dev *dev)
320 {
321 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
322 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
323 pci_pci_problems |= PCIPCI_TRITON;
324 }
325 }
326 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
327 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
328 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
329 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
330
331 /*
332 * VIA Apollo KT133 needs PCI latency patch
333 * Made according to a Windows driver-based patch by George E. Breese;
334 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
335 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
336 * which Mr Breese based his work.
337 *
338 * Updated based on further information from the site and also on
339 * information provided by VIA
340 */
quirk_vialatency(struct pci_dev * dev)341 static void quirk_vialatency(struct pci_dev *dev)
342 {
343 struct pci_dev *p;
344 u8 busarb;
345
346 /*
347 * Ok, we have a potential problem chipset here. Now see if we have
348 * a buggy southbridge.
349 */
350 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
351 if (p != NULL) {
352
353 /*
354 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
355 * thanks Dan Hollis.
356 * Check for buggy part revisions
357 */
358 if (p->revision < 0x40 || p->revision > 0x42)
359 goto exit;
360 } else {
361 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
362 if (p == NULL) /* No problem parts */
363 goto exit;
364
365 /* Check for buggy part revisions */
366 if (p->revision < 0x10 || p->revision > 0x12)
367 goto exit;
368 }
369
370 /*
371 * Ok we have the problem. Now set the PCI master grant to occur
372 * every master grant. The apparent bug is that under high PCI load
373 * (quite common in Linux of course) you can get data loss when the
374 * CPU is held off the bus for 3 bus master requests. This happens
375 * to include the IDE controllers....
376 *
377 * VIA only apply this fix when an SB Live! is present but under
378 * both Linux and Windows this isn't enough, and we have seen
379 * corruption without SB Live! but with things like 3 UDMA IDE
380 * controllers. So we ignore that bit of the VIA recommendation..
381 */
382 pci_read_config_byte(dev, 0x76, &busarb);
383
384 /*
385 * Set bit 4 and bit 5 of byte 76 to 0x01
386 * "Master priority rotation on every PCI master grant"
387 */
388 busarb &= ~(1<<5);
389 busarb |= (1<<4);
390 pci_write_config_byte(dev, 0x76, busarb);
391 pci_info(dev, "Applying VIA southbridge workaround\n");
392 exit:
393 pci_dev_put(p);
394 }
395 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
396 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
397 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
398 /* Must restore this on a resume from RAM */
399 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
400 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
401 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
402
403 /* VIA Apollo VP3 needs ETBF on BT848/878 */
quirk_viaetbf(struct pci_dev * dev)404 static void quirk_viaetbf(struct pci_dev *dev)
405 {
406 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
407 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
408 pci_pci_problems |= PCIPCI_VIAETBF;
409 }
410 }
411 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
412
quirk_vsfx(struct pci_dev * dev)413 static void quirk_vsfx(struct pci_dev *dev)
414 {
415 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
416 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
417 pci_pci_problems |= PCIPCI_VSFX;
418 }
419 }
420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
421
422 /*
423 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
424 * space. Latency must be set to 0xA and Triton workaround applied too.
425 * [Info kindly provided by ALi]
426 */
quirk_alimagik(struct pci_dev * dev)427 static void quirk_alimagik(struct pci_dev *dev)
428 {
429 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
430 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
431 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
432 }
433 }
434 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
435 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
436
437 /* Natoma has some interesting boundary conditions with Zoran stuff at least */
quirk_natoma(struct pci_dev * dev)438 static void quirk_natoma(struct pci_dev *dev)
439 {
440 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
441 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
442 pci_pci_problems |= PCIPCI_NATOMA;
443 }
444 }
445 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
446 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
447 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
448 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
449 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
450 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
451
452 /*
453 * This chip can cause PCI parity errors if config register 0xA0 is read
454 * while DMAs are occurring.
455 */
quirk_citrine(struct pci_dev * dev)456 static void quirk_citrine(struct pci_dev *dev)
457 {
458 dev->cfg_size = 0xA0;
459 }
460 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
461
462 /*
463 * This chip can cause bus lockups if config addresses above 0x600
464 * are read or written.
465 */
quirk_nfp6000(struct pci_dev * dev)466 static void quirk_nfp6000(struct pci_dev *dev)
467 {
468 dev->cfg_size = 0x600;
469 }
470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
471 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
472 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000);
473 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
474
475 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
quirk_extend_bar_to_page(struct pci_dev * dev)476 static void quirk_extend_bar_to_page(struct pci_dev *dev)
477 {
478 int i;
479
480 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
481 struct resource *r = &dev->resource[i];
482
483 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
484 r->end = PAGE_SIZE - 1;
485 r->start = 0;
486 r->flags |= IORESOURCE_UNSET;
487 pci_info(dev, "expanded BAR %d to page size: %pR\n",
488 i, r);
489 }
490 }
491 }
492 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
493
494 /*
495 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
496 * If it's needed, re-allocate the region.
497 */
quirk_s3_64M(struct pci_dev * dev)498 static void quirk_s3_64M(struct pci_dev *dev)
499 {
500 struct resource *r = &dev->resource[0];
501
502 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
503 r->flags |= IORESOURCE_UNSET;
504 r->start = 0;
505 r->end = 0x3ffffff;
506 }
507 }
508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
509 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
510
quirk_io(struct pci_dev * dev,int pos,unsigned size,const char * name)511 static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
512 const char *name)
513 {
514 u32 region;
515 struct pci_bus_region bus_region;
516 struct resource *res = dev->resource + pos;
517
518 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
519
520 if (!region)
521 return;
522
523 res->name = pci_name(dev);
524 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
525 res->flags |=
526 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
527 region &= ~(size - 1);
528
529 /* Convert from PCI bus to resource space */
530 bus_region.start = region;
531 bus_region.end = region + size - 1;
532 pcibios_bus_to_resource(dev->bus, res, &bus_region);
533
534 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
535 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
536 }
537
538 /*
539 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
540 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
541 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
542 * (which conflicts w/ BAR1's memory range).
543 *
544 * CS553x's ISA PCI BARs may also be read-only (ref:
545 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
546 */
quirk_cs5536_vsa(struct pci_dev * dev)547 static void quirk_cs5536_vsa(struct pci_dev *dev)
548 {
549 static char *name = "CS5536 ISA bridge";
550
551 if (pci_resource_len(dev, 0) != 8) {
552 quirk_io(dev, 0, 8, name); /* SMB */
553 quirk_io(dev, 1, 256, name); /* GPIO */
554 quirk_io(dev, 2, 64, name); /* MFGPT */
555 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
556 name);
557 }
558 }
559 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
560
quirk_io_region(struct pci_dev * dev,int port,unsigned size,int nr,const char * name)561 static void quirk_io_region(struct pci_dev *dev, int port,
562 unsigned size, int nr, const char *name)
563 {
564 u16 region;
565 struct pci_bus_region bus_region;
566 struct resource *res = dev->resource + nr;
567
568 pci_read_config_word(dev, port, ®ion);
569 region &= ~(size - 1);
570
571 if (!region)
572 return;
573
574 res->name = pci_name(dev);
575 res->flags = IORESOURCE_IO;
576
577 /* Convert from PCI bus to resource space */
578 bus_region.start = region;
579 bus_region.end = region + size - 1;
580 pcibios_bus_to_resource(dev->bus, res, &bus_region);
581
582 if (!pci_claim_resource(dev, nr))
583 pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
584 }
585
586 /*
587 * ATI Northbridge setups MCE the processor if you even read somewhere
588 * between 0x3b0->0x3bb or read 0x3d3
589 */
quirk_ati_exploding_mce(struct pci_dev * dev)590 static void quirk_ati_exploding_mce(struct pci_dev *dev)
591 {
592 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
593 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
594 request_region(0x3b0, 0x0C, "RadeonIGP");
595 request_region(0x3d3, 0x01, "RadeonIGP");
596 }
597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
598
599 /*
600 * In the AMD NL platform, this device ([1022:7912]) has a class code of
601 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
602 * claim it.
603 *
604 * But the dwc3 driver is a more specific driver for this device, and we'd
605 * prefer to use it instead of xhci. To prevent xhci from claiming the
606 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
607 * defines as "USB device (not host controller)". The dwc3 driver can then
608 * claim it based on its Vendor and Device ID.
609 */
quirk_amd_nl_class(struct pci_dev * pdev)610 static void quirk_amd_nl_class(struct pci_dev *pdev)
611 {
612 u32 class = pdev->class;
613
614 /* Use "USB Device (not host controller)" class */
615 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
616 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
617 class, pdev->class);
618 }
619 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
620 quirk_amd_nl_class);
621
622 /*
623 * Let's make the southbridge information explicit instead of having to
624 * worry about people probing the ACPI areas, for example.. (Yes, it
625 * happens, and if you read the wrong ACPI register it will put the machine
626 * to sleep with no way of waking it up again. Bummer).
627 *
628 * ALI M7101: Two IO regions pointed to by words at
629 * 0xE0 (64 bytes of ACPI registers)
630 * 0xE2 (32 bytes of SMB registers)
631 */
quirk_ali7101_acpi(struct pci_dev * dev)632 static void quirk_ali7101_acpi(struct pci_dev *dev)
633 {
634 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
635 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
636 }
637 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
638
piix4_io_quirk(struct pci_dev * dev,const char * name,unsigned int port,unsigned int enable)639 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
640 {
641 u32 devres;
642 u32 mask, size, base;
643
644 pci_read_config_dword(dev, port, &devres);
645 if ((devres & enable) != enable)
646 return;
647 mask = (devres >> 16) & 15;
648 base = devres & 0xffff;
649 size = 16;
650 for (;;) {
651 unsigned bit = size >> 1;
652 if ((bit & mask) == bit)
653 break;
654 size = bit;
655 }
656 /*
657 * For now we only print it out. Eventually we'll want to
658 * reserve it (at least if it's in the 0x1000+ range), but
659 * let's get enough confirmation reports first.
660 */
661 base &= -size;
662 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
663 }
664
piix4_mem_quirk(struct pci_dev * dev,const char * name,unsigned int port,unsigned int enable)665 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
666 {
667 u32 devres;
668 u32 mask, size, base;
669
670 pci_read_config_dword(dev, port, &devres);
671 if ((devres & enable) != enable)
672 return;
673 base = devres & 0xffff0000;
674 mask = (devres & 0x3f) << 16;
675 size = 128 << 16;
676 for (;;) {
677 unsigned bit = size >> 1;
678 if ((bit & mask) == bit)
679 break;
680 size = bit;
681 }
682
683 /*
684 * For now we only print it out. Eventually we'll want to
685 * reserve it, but let's get enough confirmation reports first.
686 */
687 base &= -size;
688 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
689 }
690
691 /*
692 * PIIX4 ACPI: Two IO regions pointed to by longwords at
693 * 0x40 (64 bytes of ACPI registers)
694 * 0x90 (16 bytes of SMB registers)
695 * and a few strange programmable PIIX4 device resources.
696 */
quirk_piix4_acpi(struct pci_dev * dev)697 static void quirk_piix4_acpi(struct pci_dev *dev)
698 {
699 u32 res_a;
700
701 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
702 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
703
704 /* Device resource A has enables for some of the other ones */
705 pci_read_config_dword(dev, 0x5c, &res_a);
706
707 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
708 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
709
710 /* Device resource D is just bitfields for static resources */
711
712 /* Device 12 enabled? */
713 if (res_a & (1 << 29)) {
714 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
715 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
716 }
717 /* Device 13 enabled? */
718 if (res_a & (1 << 30)) {
719 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
720 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
721 }
722 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
723 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
724 }
725 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
726 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
727
728 #define ICH_PMBASE 0x40
729 #define ICH_ACPI_CNTL 0x44
730 #define ICH4_ACPI_EN 0x10
731 #define ICH6_ACPI_EN 0x80
732 #define ICH4_GPIOBASE 0x58
733 #define ICH4_GPIO_CNTL 0x5c
734 #define ICH4_GPIO_EN 0x10
735 #define ICH6_GPIOBASE 0x48
736 #define ICH6_GPIO_CNTL 0x4c
737 #define ICH6_GPIO_EN 0x10
738
739 /*
740 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
741 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
742 * 0x58 (64 bytes of GPIO I/O space)
743 */
quirk_ich4_lpc_acpi(struct pci_dev * dev)744 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
745 {
746 u8 enable;
747
748 /*
749 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
750 * with low legacy (and fixed) ports. We don't know the decoding
751 * priority and can't tell whether the legacy device or the one created
752 * here is really at that address. This happens on boards with broken
753 * BIOSes.
754 */
755 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
756 if (enable & ICH4_ACPI_EN)
757 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
758 "ICH4 ACPI/GPIO/TCO");
759
760 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
761 if (enable & ICH4_GPIO_EN)
762 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
763 "ICH4 GPIO");
764 }
765 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
766 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
767 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
768 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
769 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
770 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
771 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
772 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
773 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
774 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
775
ich6_lpc_acpi_gpio(struct pci_dev * dev)776 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
777 {
778 u8 enable;
779
780 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
781 if (enable & ICH6_ACPI_EN)
782 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
783 "ICH6 ACPI/GPIO/TCO");
784
785 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
786 if (enable & ICH6_GPIO_EN)
787 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
788 "ICH6 GPIO");
789 }
790
ich6_lpc_generic_decode(struct pci_dev * dev,unsigned reg,const char * name,int dynsize)791 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
792 const char *name, int dynsize)
793 {
794 u32 val;
795 u32 size, base;
796
797 pci_read_config_dword(dev, reg, &val);
798
799 /* Enabled? */
800 if (!(val & 1))
801 return;
802 base = val & 0xfffc;
803 if (dynsize) {
804 /*
805 * This is not correct. It is 16, 32 or 64 bytes depending on
806 * register D31:F0:ADh bits 5:4.
807 *
808 * But this gets us at least _part_ of it.
809 */
810 size = 16;
811 } else {
812 size = 128;
813 }
814 base &= ~(size-1);
815
816 /*
817 * Just print it out for now. We should reserve it after more
818 * debugging.
819 */
820 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
821 }
822
quirk_ich6_lpc(struct pci_dev * dev)823 static void quirk_ich6_lpc(struct pci_dev *dev)
824 {
825 /* Shared ACPI/GPIO decode with all ICH6+ */
826 ich6_lpc_acpi_gpio(dev);
827
828 /* ICH6-specific generic IO decode */
829 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
830 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
831 }
832 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
833 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
834
ich7_lpc_generic_decode(struct pci_dev * dev,unsigned reg,const char * name)835 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
836 const char *name)
837 {
838 u32 val;
839 u32 mask, base;
840
841 pci_read_config_dword(dev, reg, &val);
842
843 /* Enabled? */
844 if (!(val & 1))
845 return;
846
847 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
848 base = val & 0xfffc;
849 mask = (val >> 16) & 0xfc;
850 mask |= 3;
851
852 /*
853 * Just print it out for now. We should reserve it after more
854 * debugging.
855 */
856 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
857 }
858
859 /* ICH7-10 has the same common LPC generic IO decode registers */
quirk_ich7_lpc(struct pci_dev * dev)860 static void quirk_ich7_lpc(struct pci_dev *dev)
861 {
862 /* We share the common ACPI/GPIO decode with ICH6 */
863 ich6_lpc_acpi_gpio(dev);
864
865 /* And have 4 ICH7+ generic decodes */
866 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
867 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
868 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
869 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
870 }
871 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
872 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
873 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
874 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
875 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
876 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
877 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
878 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
879 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
880 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
881 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
882 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
883 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
884
885 /*
886 * VIA ACPI: One IO region pointed to by longword at
887 * 0x48 or 0x20 (256 bytes of ACPI registers)
888 */
quirk_vt82c586_acpi(struct pci_dev * dev)889 static void quirk_vt82c586_acpi(struct pci_dev *dev)
890 {
891 if (dev->revision & 0x10)
892 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
893 "vt82c586 ACPI");
894 }
895 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
896
897 /*
898 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
899 * 0x48 (256 bytes of ACPI registers)
900 * 0x70 (128 bytes of hardware monitoring register)
901 * 0x90 (16 bytes of SMB registers)
902 */
quirk_vt82c686_acpi(struct pci_dev * dev)903 static void quirk_vt82c686_acpi(struct pci_dev *dev)
904 {
905 quirk_vt82c586_acpi(dev);
906
907 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
908 "vt82c686 HW-mon");
909
910 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
911 }
912 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
913
914 /*
915 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
916 * 0x88 (128 bytes of power management registers)
917 * 0xd0 (16 bytes of SMB registers)
918 */
quirk_vt8235_acpi(struct pci_dev * dev)919 static void quirk_vt8235_acpi(struct pci_dev *dev)
920 {
921 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
922 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
923 }
924 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
925
926 /*
927 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
928 * back-to-back: Disable fast back-to-back on the secondary bus segment
929 */
quirk_xio2000a(struct pci_dev * dev)930 static void quirk_xio2000a(struct pci_dev *dev)
931 {
932 struct pci_dev *pdev;
933 u16 command;
934
935 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
936 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
937 pci_read_config_word(pdev, PCI_COMMAND, &command);
938 if (command & PCI_COMMAND_FAST_BACK)
939 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
940 }
941 }
942 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
943 quirk_xio2000a);
944
945 #ifdef CONFIG_X86_IO_APIC
946
947 #include <asm/io_apic.h>
948
949 /*
950 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
951 * devices to the external APIC.
952 *
953 * TODO: When we have device-specific interrupt routers, this code will go
954 * away from quirks.
955 */
quirk_via_ioapic(struct pci_dev * dev)956 static void quirk_via_ioapic(struct pci_dev *dev)
957 {
958 u8 tmp;
959
960 if (nr_ioapics < 1)
961 tmp = 0; /* nothing routed to external APIC */
962 else
963 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
964
965 pci_info(dev, "%sbling VIA external APIC routing\n",
966 tmp == 0 ? "Disa" : "Ena");
967
968 /* Offset 0x58: External APIC IRQ output control */
969 pci_write_config_byte(dev, 0x58, tmp);
970 }
971 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
972 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
973
974 /*
975 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
976 * This leads to doubled level interrupt rates.
977 * Set this bit to get rid of cycle wastage.
978 * Otherwise uncritical.
979 */
quirk_via_vt8237_bypass_apic_deassert(struct pci_dev * dev)980 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
981 {
982 u8 misc_control2;
983 #define BYPASS_APIC_DEASSERT 8
984
985 pci_read_config_byte(dev, 0x5B, &misc_control2);
986 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
987 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
988 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
989 }
990 }
991 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
992 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
993
994 /*
995 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
996 * We check all revs >= B0 (yet not in the pre production!) as the bug
997 * is currently marked NoFix
998 *
999 * We have multiple reports of hangs with this chipset that went away with
1000 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1001 * of course. However the advice is demonstrably good even if so.
1002 */
quirk_amd_ioapic(struct pci_dev * dev)1003 static void quirk_amd_ioapic(struct pci_dev *dev)
1004 {
1005 if (dev->revision >= 0x02) {
1006 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1007 pci_warn(dev, " : booting with the \"noapic\" option\n");
1008 }
1009 }
1010 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1011 #endif /* CONFIG_X86_IO_APIC */
1012
1013 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
1014
quirk_cavium_sriov_rnm_link(struct pci_dev * dev)1015 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
1016 {
1017 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
1018 if (dev->subsystem_device == 0xa118)
1019 dev->sriov->link = dev->devfn;
1020 }
1021 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
1022 #endif
1023
1024 /*
1025 * Some settings of MMRBC can lead to data corruption so block changes.
1026 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1027 */
quirk_amd_8131_mmrbc(struct pci_dev * dev)1028 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
1029 {
1030 if (dev->subordinate && dev->revision <= 0x12) {
1031 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
1032 dev->revision);
1033 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
1034 }
1035 }
1036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1037
1038 /*
1039 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
1040 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1041 * at all. Therefore it seems like setting the pci_dev's IRQ to the value
1042 * of the ACPI SCI interrupt is only done for convenience.
1043 * -jgarzik
1044 */
quirk_via_acpi(struct pci_dev * d)1045 static void quirk_via_acpi(struct pci_dev *d)
1046 {
1047 u8 irq;
1048
1049 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1050 pci_read_config_byte(d, 0x42, &irq);
1051 irq &= 0xf;
1052 if (irq && (irq != 2))
1053 d->irq = irq;
1054 }
1055 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
1056 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1057
1058 /* VIA bridges which have VLink */
1059 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1060
quirk_via_bridge(struct pci_dev * dev)1061 static void quirk_via_bridge(struct pci_dev *dev)
1062 {
1063 /* See what bridge we have and find the device ranges */
1064 switch (dev->device) {
1065 case PCI_DEVICE_ID_VIA_82C686:
1066 /*
1067 * The VT82C686 is special; it attaches to PCI and can have
1068 * any device number. All its subdevices are functions of
1069 * that single device.
1070 */
1071 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
1072 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
1073 break;
1074 case PCI_DEVICE_ID_VIA_8237:
1075 case PCI_DEVICE_ID_VIA_8237A:
1076 via_vlink_dev_lo = 15;
1077 break;
1078 case PCI_DEVICE_ID_VIA_8235:
1079 via_vlink_dev_lo = 16;
1080 break;
1081 case PCI_DEVICE_ID_VIA_8231:
1082 case PCI_DEVICE_ID_VIA_8233_0:
1083 case PCI_DEVICE_ID_VIA_8233A:
1084 case PCI_DEVICE_ID_VIA_8233C_0:
1085 via_vlink_dev_lo = 17;
1086 break;
1087 }
1088 }
1089 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
1090 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
1091 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
1092 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
1093 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
1094 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
1095 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
1096 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
1097
1098 /*
1099 * quirk_via_vlink - VIA VLink IRQ number update
1100 * @dev: PCI device
1101 *
1102 * If the device we are dealing with is on a PIC IRQ we need to ensure that
1103 * the IRQ line register which usually is not relevant for PCI cards, is
1104 * actually written so that interrupts get sent to the right place.
1105 *
1106 * We only do this on systems where a VIA south bridge was detected, and
1107 * only for VIA devices on the motherboard (see quirk_via_bridge above).
1108 */
quirk_via_vlink(struct pci_dev * dev)1109 static void quirk_via_vlink(struct pci_dev *dev)
1110 {
1111 u8 irq, new_irq;
1112
1113 /* Check if we have VLink at all */
1114 if (via_vlink_dev_lo == -1)
1115 return;
1116
1117 new_irq = dev->irq;
1118
1119 /* Don't quirk interrupts outside the legacy IRQ range */
1120 if (!new_irq || new_irq > 15)
1121 return;
1122
1123 /* Internal device ? */
1124 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
1125 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1126 return;
1127
1128 /*
1129 * This is an internal VLink device on a PIC interrupt. The BIOS
1130 * ought to have set this but may not have, so we redo it.
1131 */
1132 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1133 if (new_irq != irq) {
1134 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
1135 irq, new_irq);
1136 udelay(15); /* unknown if delay really needed */
1137 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
1138 }
1139 }
1140 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
1141
1142 /*
1143 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1144 * of VT82C597 for backward compatibility. We need to switch it off to be
1145 * able to recognize the real type of the chip.
1146 */
quirk_vt82c598_id(struct pci_dev * dev)1147 static void quirk_vt82c598_id(struct pci_dev *dev)
1148 {
1149 pci_write_config_byte(dev, 0xfc, 0);
1150 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
1151 }
1152 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1153
1154 /*
1155 * CardBus controllers have a legacy base address that enables them to
1156 * respond as i82365 pcmcia controllers. We don't want them to do this
1157 * even if the Linux CardBus driver is not loaded, because the Linux i82365
1158 * driver does not (and should not) handle CardBus.
1159 */
quirk_cardbus_legacy(struct pci_dev * dev)1160 static void quirk_cardbus_legacy(struct pci_dev *dev)
1161 {
1162 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1163 }
1164 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1165 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1166 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1167 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1168
1169 /*
1170 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1171 * what the designers were smoking but let's not inhale...
1172 *
1173 * To be fair to AMD, it follows the spec by default, it's BIOS people who
1174 * turn it off!
1175 */
quirk_amd_ordering(struct pci_dev * dev)1176 static void quirk_amd_ordering(struct pci_dev *dev)
1177 {
1178 u32 pcic;
1179 pci_read_config_dword(dev, 0x4C, &pcic);
1180 if ((pcic & 6) != 6) {
1181 pcic |= 6;
1182 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1183 pci_write_config_dword(dev, 0x4C, pcic);
1184 pci_read_config_dword(dev, 0x84, &pcic);
1185 pcic |= (1 << 23); /* Required in this mode */
1186 pci_write_config_dword(dev, 0x84, pcic);
1187 }
1188 }
1189 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1190 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1191
1192 /*
1193 * DreamWorks-provided workaround for Dunord I-3000 problem
1194 *
1195 * This card decodes and responds to addresses not apparently assigned to
1196 * it. We force a larger allocation to ensure that nothing gets put too
1197 * close to it.
1198 */
quirk_dunord(struct pci_dev * dev)1199 static void quirk_dunord(struct pci_dev *dev)
1200 {
1201 struct resource *r = &dev->resource[1];
1202
1203 r->flags |= IORESOURCE_UNSET;
1204 r->start = 0;
1205 r->end = 0xffffff;
1206 }
1207 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1208
1209 /*
1210 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1211 * decoding (transparent), and does indicate this in the ProgIf.
1212 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1213 */
quirk_transparent_bridge(struct pci_dev * dev)1214 static void quirk_transparent_bridge(struct pci_dev *dev)
1215 {
1216 dev->transparent = 1;
1217 }
1218 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1219 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1220
1221 /*
1222 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1223 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1224 * found at http://www.national.com/analog for info on what these bits do.
1225 * <christer@weinigel.se>
1226 */
quirk_mediagx_master(struct pci_dev * dev)1227 static void quirk_mediagx_master(struct pci_dev *dev)
1228 {
1229 u8 reg;
1230
1231 pci_read_config_byte(dev, 0x41, ®);
1232 if (reg & 2) {
1233 reg &= ~2;
1234 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1235 reg);
1236 pci_write_config_byte(dev, 0x41, reg);
1237 }
1238 }
1239 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1240 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1241
1242 /*
1243 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1244 * in the odd case it is not the results are corruption hence the presence
1245 * of a Linux check.
1246 */
quirk_disable_pxb(struct pci_dev * pdev)1247 static void quirk_disable_pxb(struct pci_dev *pdev)
1248 {
1249 u16 config;
1250
1251 if (pdev->revision != 0x04) /* Only C0 requires this */
1252 return;
1253 pci_read_config_word(pdev, 0x40, &config);
1254 if (config & (1<<6)) {
1255 config &= ~(1<<6);
1256 pci_write_config_word(pdev, 0x40, config);
1257 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
1258 }
1259 }
1260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1261 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1262
quirk_amd_ide_mode(struct pci_dev * pdev)1263 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1264 {
1265 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1266 u8 tmp;
1267
1268 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1269 if (tmp == 0x01) {
1270 pci_read_config_byte(pdev, 0x40, &tmp);
1271 pci_write_config_byte(pdev, 0x40, tmp|1);
1272 pci_write_config_byte(pdev, 0x9, 1);
1273 pci_write_config_byte(pdev, 0xa, 6);
1274 pci_write_config_byte(pdev, 0x40, tmp);
1275
1276 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1277 pci_info(pdev, "set SATA to AHCI mode\n");
1278 }
1279 }
1280 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1281 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1282 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1283 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1284 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1285 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1287 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1288
1289 /* Serverworks CSB5 IDE does not fully support native mode */
quirk_svwks_csb5ide(struct pci_dev * pdev)1290 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1291 {
1292 u8 prog;
1293 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1294 if (prog & 5) {
1295 prog &= ~5;
1296 pdev->class &= ~5;
1297 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1298 /* PCI layer will sort out resources */
1299 }
1300 }
1301 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1302
1303 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
quirk_ide_samemode(struct pci_dev * pdev)1304 static void quirk_ide_samemode(struct pci_dev *pdev)
1305 {
1306 u8 prog;
1307
1308 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1309
1310 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1311 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
1312 prog &= ~5;
1313 pdev->class &= ~5;
1314 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1315 }
1316 }
1317 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1318
1319 /* Some ATA devices break if put into D3 */
quirk_no_ata_d3(struct pci_dev * pdev)1320 static void quirk_no_ata_d3(struct pci_dev *pdev)
1321 {
1322 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1323 }
1324 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1325 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1326 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1327 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1328 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1329 /* ALi loses some register settings that we cannot then restore */
1330 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1331 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1332 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1333 occur when mode detecting */
1334 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1335 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1336
1337 /*
1338 * This was originally an Alpha-specific thing, but it really fits here.
1339 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1340 */
quirk_eisa_bridge(struct pci_dev * dev)1341 static void quirk_eisa_bridge(struct pci_dev *dev)
1342 {
1343 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1344 }
1345 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1346
1347 /*
1348 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1349 * is not activated. The myth is that Asus said that they do not want the
1350 * users to be irritated by just another PCI Device in the Win98 device
1351 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1352 * package 2.7.0 for details)
1353 *
1354 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1355 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1356 * becomes necessary to do this tweak in two steps -- the chosen trigger
1357 * is either the Host bridge (preferred) or on-board VGA controller.
1358 *
1359 * Note that we used to unhide the SMBus that way on Toshiba laptops
1360 * (Satellite A40 and Tecra M2) but then found that the thermal management
1361 * was done by SMM code, which could cause unsynchronized concurrent
1362 * accesses to the SMBus registers, with potentially bad effects. Thus you
1363 * should be very careful when adding new entries: if SMM is accessing the
1364 * Intel SMBus, this is a very good reason to leave it hidden.
1365 *
1366 * Likewise, many recent laptops use ACPI for thermal management. If the
1367 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1368 * natively, and keeping the SMBus hidden is the right thing to do. If you
1369 * are about to add an entry in the table below, please first disassemble
1370 * the DSDT and double-check that there is no code accessing the SMBus.
1371 */
1372 static int asus_hides_smbus;
1373
asus_hides_smbus_hostbridge(struct pci_dev * dev)1374 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1375 {
1376 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1377 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1378 switch (dev->subsystem_device) {
1379 case 0x8025: /* P4B-LX */
1380 case 0x8070: /* P4B */
1381 case 0x8088: /* P4B533 */
1382 case 0x1626: /* L3C notebook */
1383 asus_hides_smbus = 1;
1384 }
1385 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1386 switch (dev->subsystem_device) {
1387 case 0x80b1: /* P4GE-V */
1388 case 0x80b2: /* P4PE */
1389 case 0x8093: /* P4B533-V */
1390 asus_hides_smbus = 1;
1391 }
1392 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1393 switch (dev->subsystem_device) {
1394 case 0x8030: /* P4T533 */
1395 asus_hides_smbus = 1;
1396 }
1397 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1398 switch (dev->subsystem_device) {
1399 case 0x8070: /* P4G8X Deluxe */
1400 asus_hides_smbus = 1;
1401 }
1402 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1403 switch (dev->subsystem_device) {
1404 case 0x80c9: /* PU-DLS */
1405 asus_hides_smbus = 1;
1406 }
1407 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1408 switch (dev->subsystem_device) {
1409 case 0x1751: /* M2N notebook */
1410 case 0x1821: /* M5N notebook */
1411 case 0x1897: /* A6L notebook */
1412 asus_hides_smbus = 1;
1413 }
1414 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1415 switch (dev->subsystem_device) {
1416 case 0x184b: /* W1N notebook */
1417 case 0x186a: /* M6Ne notebook */
1418 asus_hides_smbus = 1;
1419 }
1420 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1421 switch (dev->subsystem_device) {
1422 case 0x80f2: /* P4P800-X */
1423 asus_hides_smbus = 1;
1424 }
1425 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1426 switch (dev->subsystem_device) {
1427 case 0x1882: /* M6V notebook */
1428 case 0x1977: /* A6VA notebook */
1429 asus_hides_smbus = 1;
1430 }
1431 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1432 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1433 switch (dev->subsystem_device) {
1434 case 0x088C: /* HP Compaq nc8000 */
1435 case 0x0890: /* HP Compaq nc6000 */
1436 asus_hides_smbus = 1;
1437 }
1438 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1439 switch (dev->subsystem_device) {
1440 case 0x12bc: /* HP D330L */
1441 case 0x12bd: /* HP D530 */
1442 case 0x006a: /* HP Compaq nx9500 */
1443 asus_hides_smbus = 1;
1444 }
1445 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1446 switch (dev->subsystem_device) {
1447 case 0x12bf: /* HP xw4100 */
1448 asus_hides_smbus = 1;
1449 }
1450 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1451 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1452 switch (dev->subsystem_device) {
1453 case 0xC00C: /* Samsung P35 notebook */
1454 asus_hides_smbus = 1;
1455 }
1456 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1457 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1458 switch (dev->subsystem_device) {
1459 case 0x0058: /* Compaq Evo N620c */
1460 asus_hides_smbus = 1;
1461 }
1462 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1463 switch (dev->subsystem_device) {
1464 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1465 /* Motherboard doesn't have Host bridge
1466 * subvendor/subdevice IDs, therefore checking
1467 * its on-board VGA controller */
1468 asus_hides_smbus = 1;
1469 }
1470 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1471 switch (dev->subsystem_device) {
1472 case 0x00b8: /* Compaq Evo D510 CMT */
1473 case 0x00b9: /* Compaq Evo D510 SFF */
1474 case 0x00ba: /* Compaq Evo D510 USDT */
1475 /* Motherboard doesn't have Host bridge
1476 * subvendor/subdevice IDs and on-board VGA
1477 * controller is disabled if an AGP card is
1478 * inserted, therefore checking USB UHCI
1479 * Controller #1 */
1480 asus_hides_smbus = 1;
1481 }
1482 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1483 switch (dev->subsystem_device) {
1484 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1485 /* Motherboard doesn't have host bridge
1486 * subvendor/subdevice IDs, therefore checking
1487 * its on-board VGA controller */
1488 asus_hides_smbus = 1;
1489 }
1490 }
1491 }
1492 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1493 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1496 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1497 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1498 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1499 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1502
1503 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1505 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1506
asus_hides_smbus_lpc(struct pci_dev * dev)1507 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1508 {
1509 u16 val;
1510
1511 if (likely(!asus_hides_smbus))
1512 return;
1513
1514 pci_read_config_word(dev, 0xF2, &val);
1515 if (val & 0x8) {
1516 pci_write_config_word(dev, 0xF2, val & (~0x8));
1517 pci_read_config_word(dev, 0xF2, &val);
1518 if (val & 0x8)
1519 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1520 val);
1521 else
1522 pci_info(dev, "Enabled i801 SMBus device\n");
1523 }
1524 }
1525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1527 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1528 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1529 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1530 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1531 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1532 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1533 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1534 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1535 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1536 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1537 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1538 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1539
1540 /* It appears we just have one such device. If not, we have a warning */
1541 static void __iomem *asus_rcba_base;
asus_hides_smbus_lpc_ich6_suspend(struct pci_dev * dev)1542 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1543 {
1544 u32 rcba;
1545
1546 if (likely(!asus_hides_smbus))
1547 return;
1548 WARN_ON(asus_rcba_base);
1549
1550 pci_read_config_dword(dev, 0xF0, &rcba);
1551 /* use bits 31:14, 16 kB aligned */
1552 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1553 if (asus_rcba_base == NULL)
1554 return;
1555 }
1556
asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev * dev)1557 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1558 {
1559 u32 val;
1560
1561 if (likely(!asus_hides_smbus || !asus_rcba_base))
1562 return;
1563
1564 /* read the Function Disable register, dword mode only */
1565 val = readl(asus_rcba_base + 0x3418);
1566
1567 /* enable the SMBus device */
1568 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1569 }
1570
asus_hides_smbus_lpc_ich6_resume(struct pci_dev * dev)1571 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1572 {
1573 if (likely(!asus_hides_smbus || !asus_rcba_base))
1574 return;
1575
1576 iounmap(asus_rcba_base);
1577 asus_rcba_base = NULL;
1578 pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
1579 }
1580
asus_hides_smbus_lpc_ich6(struct pci_dev * dev)1581 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1582 {
1583 asus_hides_smbus_lpc_ich6_suspend(dev);
1584 asus_hides_smbus_lpc_ich6_resume_early(dev);
1585 asus_hides_smbus_lpc_ich6_resume(dev);
1586 }
1587 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1588 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1589 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1590 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1591
1592 /* SiS 96x south bridge: BIOS typically hides SMBus device... */
quirk_sis_96x_smbus(struct pci_dev * dev)1593 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1594 {
1595 u8 val = 0;
1596 pci_read_config_byte(dev, 0x77, &val);
1597 if (val & 0x10) {
1598 pci_info(dev, "Enabling SiS 96x SMBus\n");
1599 pci_write_config_byte(dev, 0x77, val & ~0x10);
1600 }
1601 }
1602 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1603 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1604 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1605 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1606 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1607 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1608 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1609 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1610
1611 /*
1612 * ... This is further complicated by the fact that some SiS96x south
1613 * bridges pretend to be 85C503/5513 instead. In that case see if we
1614 * spotted a compatible north bridge to make sure.
1615 * (pci_find_device() doesn't work yet)
1616 *
1617 * We can also enable the sis96x bit in the discovery register..
1618 */
1619 #define SIS_DETECT_REGISTER 0x40
1620
quirk_sis_503(struct pci_dev * dev)1621 static void quirk_sis_503(struct pci_dev *dev)
1622 {
1623 u8 reg;
1624 u16 devid;
1625
1626 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1627 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1628 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1629 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1630 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1631 return;
1632 }
1633
1634 /*
1635 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
1636 * it has already been processed. (Depends on link order, which is
1637 * apparently not guaranteed)
1638 */
1639 dev->device = devid;
1640 quirk_sis_96x_smbus(dev);
1641 }
1642 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1643 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1644
1645 /*
1646 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1647 * and MC97 modem controller are disabled when a second PCI soundcard is
1648 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1649 * -- bjd
1650 */
asus_hides_ac97_lpc(struct pci_dev * dev)1651 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1652 {
1653 u8 val;
1654 int asus_hides_ac97 = 0;
1655
1656 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1657 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1658 asus_hides_ac97 = 1;
1659 }
1660
1661 if (!asus_hides_ac97)
1662 return;
1663
1664 pci_read_config_byte(dev, 0x50, &val);
1665 if (val & 0xc0) {
1666 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1667 pci_read_config_byte(dev, 0x50, &val);
1668 if (val & 0xc0)
1669 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1670 val);
1671 else
1672 pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
1673 }
1674 }
1675 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1676 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1677
1678 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1679
1680 /*
1681 * If we are using libata we can drive this chip properly but must do this
1682 * early on to make the additional device appear during the PCI scanning.
1683 */
quirk_jmicron_ata(struct pci_dev * pdev)1684 static void quirk_jmicron_ata(struct pci_dev *pdev)
1685 {
1686 u32 conf1, conf5, class;
1687 u8 hdr;
1688
1689 /* Only poke fn 0 */
1690 if (PCI_FUNC(pdev->devfn))
1691 return;
1692
1693 pci_read_config_dword(pdev, 0x40, &conf1);
1694 pci_read_config_dword(pdev, 0x80, &conf5);
1695
1696 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1697 conf5 &= ~(1 << 24); /* Clear bit 24 */
1698
1699 switch (pdev->device) {
1700 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1701 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1702 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1703 /* The controller should be in single function ahci mode */
1704 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1705 break;
1706
1707 case PCI_DEVICE_ID_JMICRON_JMB365:
1708 case PCI_DEVICE_ID_JMICRON_JMB366:
1709 /* Redirect IDE second PATA port to the right spot */
1710 conf5 |= (1 << 24);
1711 /* Fall through */
1712 case PCI_DEVICE_ID_JMICRON_JMB361:
1713 case PCI_DEVICE_ID_JMICRON_JMB363:
1714 case PCI_DEVICE_ID_JMICRON_JMB369:
1715 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1716 /* Set the class codes correctly and then direct IDE 0 */
1717 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1718 break;
1719
1720 case PCI_DEVICE_ID_JMICRON_JMB368:
1721 /* The controller should be in single function IDE mode */
1722 conf1 |= 0x00C00000; /* Set 22, 23 */
1723 break;
1724 }
1725
1726 pci_write_config_dword(pdev, 0x40, conf1);
1727 pci_write_config_dword(pdev, 0x80, conf5);
1728
1729 /* Update pdev accordingly */
1730 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1731 pdev->hdr_type = hdr & 0x7f;
1732 pdev->multifunction = !!(hdr & 0x80);
1733
1734 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1735 pdev->class = class >> 8;
1736 }
1737 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1738 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1739 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1740 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1741 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1742 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1743 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1744 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1745 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1746 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1747 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1748 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1749 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1750 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1751 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1752 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1753 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1754 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1755
1756 #endif
1757
quirk_jmicron_async_suspend(struct pci_dev * dev)1758 static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1759 {
1760 if (dev->multifunction) {
1761 device_disable_async_suspend(&dev->dev);
1762 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1763 }
1764 }
1765 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1766 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1767 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1768 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1769
1770 #ifdef CONFIG_X86_IO_APIC
quirk_alder_ioapic(struct pci_dev * pdev)1771 static void quirk_alder_ioapic(struct pci_dev *pdev)
1772 {
1773 int i;
1774
1775 if ((pdev->class >> 8) != 0xff00)
1776 return;
1777
1778 /*
1779 * The first BAR is the location of the IO-APIC... we must
1780 * not touch this (and it's already covered by the fixmap), so
1781 * forcibly insert it into the resource tree.
1782 */
1783 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1784 insert_resource(&iomem_resource, &pdev->resource[0]);
1785
1786 /*
1787 * The next five BARs all seem to be rubbish, so just clean
1788 * them out.
1789 */
1790 for (i = 1; i < 6; i++)
1791 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1792 }
1793 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1794 #endif
1795
quirk_pcie_mch(struct pci_dev * pdev)1796 static void quirk_pcie_mch(struct pci_dev *pdev)
1797 {
1798 pdev->no_msi = 1;
1799 }
1800 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1801 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1802 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1803
1804 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1805
1806 /*
1807 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1808 * together on certain PXH-based systems.
1809 */
quirk_pcie_pxh(struct pci_dev * dev)1810 static void quirk_pcie_pxh(struct pci_dev *dev)
1811 {
1812 dev->no_msi = 1;
1813 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
1814 }
1815 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1816 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1817 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1818 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1819 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1820
1821 /*
1822 * Some Intel PCI Express chipsets have trouble with downstream device
1823 * power management.
1824 */
quirk_intel_pcie_pm(struct pci_dev * dev)1825 static void quirk_intel_pcie_pm(struct pci_dev *dev)
1826 {
1827 pci_pm_d3_delay = 120;
1828 dev->no_d1d2 = 1;
1829 }
1830 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1831 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1832 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1833 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1835 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1836 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1837 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1838 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1839 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1840 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1841 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1842 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1843 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1844 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1845 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1846 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1847 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1848 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1849 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1850 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1851
quirk_d3hot_delay(struct pci_dev * dev,unsigned int delay)1852 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay)
1853 {
1854 if (dev->d3_delay >= delay)
1855 return;
1856
1857 dev->d3_delay = delay;
1858 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n",
1859 dev->d3_delay);
1860 }
1861
quirk_radeon_pm(struct pci_dev * dev)1862 static void quirk_radeon_pm(struct pci_dev *dev)
1863 {
1864 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1865 dev->subsystem_device == 0x00e2)
1866 quirk_d3hot_delay(dev, 20);
1867 }
1868 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1869
1870 /*
1871 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle.
1872 * https://bugzilla.kernel.org/show_bug.cgi?id=205587
1873 *
1874 * The kernel attempts to transition these devices to D3cold, but that seems
1875 * to be ineffective on the platforms in question; the PCI device appears to
1876 * remain on in D3hot state. The D3hot-to-D0 transition then requires an
1877 * extended delay in order to succeed.
1878 */
quirk_ryzen_xhci_d3hot(struct pci_dev * dev)1879 static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev)
1880 {
1881 quirk_d3hot_delay(dev, 20);
1882 }
1883 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
1884 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
1885 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot);
1886
1887 #ifdef CONFIG_X86_IO_APIC
dmi_disable_ioapicreroute(const struct dmi_system_id * d)1888 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
1889 {
1890 noioapicreroute = 1;
1891 pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
1892
1893 return 0;
1894 }
1895
1896 static const struct dmi_system_id boot_interrupt_dmi_table[] = {
1897 /*
1898 * Systems to exclude from boot interrupt reroute quirks
1899 */
1900 {
1901 .callback = dmi_disable_ioapicreroute,
1902 .ident = "ASUSTek Computer INC. M2N-LR",
1903 .matches = {
1904 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
1905 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1906 },
1907 },
1908 {}
1909 };
1910
1911 /*
1912 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1913 * remap the original interrupt in the Linux kernel to the boot interrupt, so
1914 * that a PCI device's interrupt handler is installed on the boot interrupt
1915 * line instead.
1916 */
quirk_reroute_to_boot_interrupts_intel(struct pci_dev * dev)1917 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1918 {
1919 dmi_check_system(boot_interrupt_dmi_table);
1920 if (noioapicquirk || noioapicreroute)
1921 return;
1922
1923 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1924 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
1925 dev->vendor, dev->device);
1926 }
1927 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1928 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1929 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1930 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1931 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1932 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1933 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1934 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1935 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1936 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1937 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1938 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1939 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1940 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1941 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1942 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1943
1944 /*
1945 * On some chipsets we can disable the generation of legacy INTx boot
1946 * interrupts.
1947 */
1948
1949 /*
1950 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
1951 * 300641-004US, section 5.7.3.
1952 *
1953 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
1954 * Core IO on Xeon E5 v2, see Intel order no 329188-003.
1955 * Core IO on Xeon E7 v2, see Intel order no 329595-002.
1956 * Core IO on Xeon E5 v3, see Intel order no 330784-003.
1957 * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
1958 * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
1959 * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
1960 * Core IO on Xeon D-1500, see Intel order no 332051-001.
1961 * Core IO on Xeon Scalable, see Intel order no 610950.
1962 */
1963 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */
1964 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1965
1966 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */
1967 #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25)
1968
quirk_disable_intel_boot_interrupt(struct pci_dev * dev)1969 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1970 {
1971 u16 pci_config_word;
1972 u32 pci_config_dword;
1973
1974 if (noioapicquirk)
1975 return;
1976
1977 switch (dev->device) {
1978 case PCI_DEVICE_ID_INTEL_ESB_10:
1979 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR,
1980 &pci_config_word);
1981 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1982 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR,
1983 pci_config_word);
1984 break;
1985 case 0x3c28: /* Xeon E5 1600/2600/4600 */
1986 case 0x0e28: /* Xeon E5/E7 V2 */
1987 case 0x2f28: /* Xeon E5/E7 V3,V4 */
1988 case 0x6f28: /* Xeon D-1500 */
1989 case 0x2034: /* Xeon Scalable Family */
1990 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
1991 &pci_config_dword);
1992 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH;
1993 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
1994 pci_config_dword);
1995 break;
1996 default:
1997 return;
1998 }
1999 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2000 dev->vendor, dev->device);
2001 }
2002 /*
2003 * Device 29 Func 5 Device IDs of IO-APIC
2004 * containing ABAR—APIC1 Alternate Base Address Register
2005 */
2006 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2007 quirk_disable_intel_boot_interrupt);
2008 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2009 quirk_disable_intel_boot_interrupt);
2010
2011 /*
2012 * Device 5 Func 0 Device IDs of Core IO modules/hubs
2013 * containing Coherent Interface Protocol Interrupt Control
2014 *
2015 * Device IDs obtained from volume 2 datasheets of commented
2016 * families above.
2017 */
2018 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28,
2019 quirk_disable_intel_boot_interrupt);
2020 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28,
2021 quirk_disable_intel_boot_interrupt);
2022 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28,
2023 quirk_disable_intel_boot_interrupt);
2024 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28,
2025 quirk_disable_intel_boot_interrupt);
2026 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034,
2027 quirk_disable_intel_boot_interrupt);
2028 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28,
2029 quirk_disable_intel_boot_interrupt);
2030 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28,
2031 quirk_disable_intel_boot_interrupt);
2032 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28,
2033 quirk_disable_intel_boot_interrupt);
2034 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28,
2035 quirk_disable_intel_boot_interrupt);
2036 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034,
2037 quirk_disable_intel_boot_interrupt);
2038
2039 /* Disable boot interrupts on HT-1000 */
2040 #define BC_HT1000_FEATURE_REG 0x64
2041 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
2042 #define BC_HT1000_MAP_IDX 0xC00
2043 #define BC_HT1000_MAP_DATA 0xC01
2044
quirk_disable_broadcom_boot_interrupt(struct pci_dev * dev)2045 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
2046 {
2047 u32 pci_config_dword;
2048 u8 irq;
2049
2050 if (noioapicquirk)
2051 return;
2052
2053 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
2054 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
2055 BC_HT1000_PIC_REGS_ENABLE);
2056
2057 for (irq = 0x10; irq < 0x10 + 32; irq++) {
2058 outb(irq, BC_HT1000_MAP_IDX);
2059 outb(0x00, BC_HT1000_MAP_DATA);
2060 }
2061
2062 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
2063
2064 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2065 dev->vendor, dev->device);
2066 }
2067 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2068 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2069
2070 /* Disable boot interrupts on AMD and ATI chipsets */
2071
2072 /*
2073 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
2074 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2075 * (due to an erratum).
2076 */
2077 #define AMD_813X_MISC 0x40
2078 #define AMD_813X_NOIOAMODE (1<<0)
2079 #define AMD_813X_REV_B1 0x12
2080 #define AMD_813X_REV_B2 0x13
2081
quirk_disable_amd_813x_boot_interrupt(struct pci_dev * dev)2082 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
2083 {
2084 u32 pci_config_dword;
2085
2086 if (noioapicquirk)
2087 return;
2088 if ((dev->revision == AMD_813X_REV_B1) ||
2089 (dev->revision == AMD_813X_REV_B2))
2090 return;
2091
2092 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
2093 pci_config_dword &= ~AMD_813X_NOIOAMODE;
2094 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
2095
2096 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2097 dev->vendor, dev->device);
2098 }
2099 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2100 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2101 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2102 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2103
2104 #define AMD_8111_PCI_IRQ_ROUTING 0x56
2105
quirk_disable_amd_8111_boot_interrupt(struct pci_dev * dev)2106 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
2107 {
2108 u16 pci_config_word;
2109
2110 if (noioapicquirk)
2111 return;
2112
2113 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
2114 if (!pci_config_word) {
2115 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
2116 dev->vendor, dev->device);
2117 return;
2118 }
2119 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
2120 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2121 dev->vendor, dev->device);
2122 }
2123 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2124 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2125 #endif /* CONFIG_X86_IO_APIC */
2126
2127 /*
2128 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2129 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
2130 * Re-allocate the region if needed...
2131 */
quirk_tc86c001_ide(struct pci_dev * dev)2132 static void quirk_tc86c001_ide(struct pci_dev *dev)
2133 {
2134 struct resource *r = &dev->resource[0];
2135
2136 if (r->start & 0x8) {
2137 r->flags |= IORESOURCE_UNSET;
2138 r->start = 0;
2139 r->end = 0xf;
2140 }
2141 }
2142 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
2143 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
2144 quirk_tc86c001_ide);
2145
2146 /*
2147 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2148 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2149 * being read correctly if bit 7 of the base address is set.
2150 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2151 * Re-allocate the regions to a 256-byte boundary if necessary.
2152 */
quirk_plx_pci9050(struct pci_dev * dev)2153 static void quirk_plx_pci9050(struct pci_dev *dev)
2154 {
2155 unsigned int bar;
2156
2157 /* Fixed in revision 2 (PCI 9052). */
2158 if (dev->revision >= 2)
2159 return;
2160 for (bar = 0; bar <= 1; bar++)
2161 if (pci_resource_len(dev, bar) == 0x80 &&
2162 (pci_resource_start(dev, bar) & 0x80)) {
2163 struct resource *r = &dev->resource[bar];
2164 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2165 bar);
2166 r->flags |= IORESOURCE_UNSET;
2167 r->start = 0;
2168 r->end = 0xff;
2169 }
2170 }
2171 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2172 quirk_plx_pci9050);
2173 /*
2174 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2175 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2176 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2177 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2178 *
2179 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2180 * driver.
2181 */
2182 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
2183 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
2184
quirk_netmos(struct pci_dev * dev)2185 static void quirk_netmos(struct pci_dev *dev)
2186 {
2187 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
2188 unsigned int num_serial = dev->subsystem_device & 0xf;
2189
2190 /*
2191 * These Netmos parts are multiport serial devices with optional
2192 * parallel ports. Even when parallel ports are present, they
2193 * are identified as class SERIAL, which means the serial driver
2194 * will claim them. To prevent this, mark them as class OTHER.
2195 * These combo devices should be claimed by parport_serial.
2196 *
2197 * The subdevice ID is of the form 0x00PS, where <P> is the number
2198 * of parallel ports and <S> is the number of serial ports.
2199 */
2200 switch (dev->device) {
2201 case PCI_DEVICE_ID_NETMOS_9835:
2202 /* Well, this rule doesn't hold for the following 9835 device */
2203 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
2204 dev->subsystem_device == 0x0299)
2205 return;
2206 /* else: fall through */
2207 case PCI_DEVICE_ID_NETMOS_9735:
2208 case PCI_DEVICE_ID_NETMOS_9745:
2209 case PCI_DEVICE_ID_NETMOS_9845:
2210 case PCI_DEVICE_ID_NETMOS_9855:
2211 if (num_parallel) {
2212 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
2213 dev->device, num_parallel, num_serial);
2214 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
2215 (dev->class & 0xff);
2216 }
2217 }
2218 }
2219 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
2220 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
2221
quirk_e100_interrupt(struct pci_dev * dev)2222 static void quirk_e100_interrupt(struct pci_dev *dev)
2223 {
2224 u16 command, pmcsr;
2225 u8 __iomem *csr;
2226 u8 cmd_hi;
2227
2228 switch (dev->device) {
2229 /* PCI IDs taken from drivers/net/e100.c */
2230 case 0x1029:
2231 case 0x1030 ... 0x1034:
2232 case 0x1038 ... 0x103E:
2233 case 0x1050 ... 0x1057:
2234 case 0x1059:
2235 case 0x1064 ... 0x106B:
2236 case 0x1091 ... 0x1095:
2237 case 0x1209:
2238 case 0x1229:
2239 case 0x2449:
2240 case 0x2459:
2241 case 0x245D:
2242 case 0x27DC:
2243 break;
2244 default:
2245 return;
2246 }
2247
2248 /*
2249 * Some firmware hands off the e100 with interrupts enabled,
2250 * which can cause a flood of interrupts if packets are
2251 * received before the driver attaches to the device. So
2252 * disable all e100 interrupts here. The driver will
2253 * re-enable them when it's ready.
2254 */
2255 pci_read_config_word(dev, PCI_COMMAND, &command);
2256
2257 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2258 return;
2259
2260 /*
2261 * Check that the device is in the D0 power state. If it's not,
2262 * there is no point to look any further.
2263 */
2264 if (dev->pm_cap) {
2265 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2266 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2267 return;
2268 }
2269
2270 /* Convert from PCI bus to resource space. */
2271 csr = ioremap(pci_resource_start(dev, 0), 8);
2272 if (!csr) {
2273 pci_warn(dev, "Can't map e100 registers\n");
2274 return;
2275 }
2276
2277 cmd_hi = readb(csr + 3);
2278 if (cmd_hi == 0) {
2279 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
2280 writeb(1, csr + 3);
2281 }
2282
2283 iounmap(csr);
2284 }
2285 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2286 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2287
2288 /*
2289 * The 82575 and 82598 may experience data corruption issues when transitioning
2290 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2291 */
quirk_disable_aspm_l0s(struct pci_dev * dev)2292 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2293 {
2294 pci_info(dev, "Disabling L0s\n");
2295 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2296 }
2297 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2298 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2299 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2300 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2301 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2302 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2303 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2304 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2305 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2306 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2307 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2308 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2309 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2310 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2311
quirk_disable_aspm_l0s_l1(struct pci_dev * dev)2312 static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
2313 {
2314 pci_info(dev, "Disabling ASPM L0s/L1\n");
2315 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
2316 }
2317
2318 /*
2319 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2320 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected;
2321 * disable both L0s and L1 for now to be safe.
2322 */
2323 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
2324
2325 /*
2326 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2327 * Link bit cleared after starting the link retrain process to allow this
2328 * process to finish.
2329 *
2330 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
2331 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
2332 */
quirk_enable_clear_retrain_link(struct pci_dev * dev)2333 static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
2334 {
2335 dev->clear_retrain_link = 1;
2336 pci_info(dev, "Enable PCIe Retrain Link quirk\n");
2337 }
2338 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link);
2339 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link);
2340 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link);
2341
fixup_rev1_53c810(struct pci_dev * dev)2342 static void fixup_rev1_53c810(struct pci_dev *dev)
2343 {
2344 u32 class = dev->class;
2345
2346 /*
2347 * rev 1 ncr53c810 chips don't set the class at all which means
2348 * they don't get their resources remapped. Fix that here.
2349 */
2350 if (class)
2351 return;
2352
2353 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2354 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2355 class, dev->class);
2356 }
2357 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2358
2359 /* Enable 1k I/O space granularity on the Intel P64H2 */
quirk_p64h2_1k_io(struct pci_dev * dev)2360 static void quirk_p64h2_1k_io(struct pci_dev *dev)
2361 {
2362 u16 en1k;
2363
2364 pci_read_config_word(dev, 0x40, &en1k);
2365
2366 if (en1k & 0x200) {
2367 pci_info(dev, "Enable I/O Space to 1KB granularity\n");
2368 dev->io_window_1k = 1;
2369 }
2370 }
2371 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2372
2373 /*
2374 * Under some circumstances, AER is not linked with extended capabilities.
2375 * Force it to be linked by setting the corresponding control bit in the
2376 * config space.
2377 */
quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev * dev)2378 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2379 {
2380 uint8_t b;
2381
2382 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2383 if (!(b & 0x20)) {
2384 pci_write_config_byte(dev, 0xf41, b | 0x20);
2385 pci_info(dev, "Linking AER extended capability\n");
2386 }
2387 }
2388 }
2389 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2390 quirk_nvidia_ck804_pcie_aer_ext_cap);
2391 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2392 quirk_nvidia_ck804_pcie_aer_ext_cap);
2393
quirk_via_cx700_pci_parking_caching(struct pci_dev * dev)2394 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2395 {
2396 /*
2397 * Disable PCI Bus Parking and PCI Master read caching on CX700
2398 * which causes unspecified timing errors with a VT6212L on the PCI
2399 * bus leading to USB2.0 packet loss.
2400 *
2401 * This quirk is only enabled if a second (on the external PCI bus)
2402 * VT6212L is found -- the CX700 core itself also contains a USB
2403 * host controller with the same PCI ID as the VT6212L.
2404 */
2405
2406 /* Count VT6212L instances */
2407 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2408 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2409 uint8_t b;
2410
2411 /*
2412 * p should contain the first (internal) VT6212L -- see if we have
2413 * an external one by searching again.
2414 */
2415 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2416 if (!p)
2417 return;
2418 pci_dev_put(p);
2419
2420 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2421 if (b & 0x40) {
2422 /* Turn off PCI Bus Parking */
2423 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2424
2425 pci_info(dev, "Disabling VIA CX700 PCI parking\n");
2426 }
2427 }
2428
2429 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2430 if (b != 0) {
2431 /* Turn off PCI Master read caching */
2432 pci_write_config_byte(dev, 0x72, 0x0);
2433
2434 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2435 pci_write_config_byte(dev, 0x75, 0x1);
2436
2437 /* Disable "Read FIFO Timer" */
2438 pci_write_config_byte(dev, 0x77, 0x0);
2439
2440 pci_info(dev, "Disabling VIA CX700 PCI caching\n");
2441 }
2442 }
2443 }
2444 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2445
quirk_brcm_5719_limit_mrrs(struct pci_dev * dev)2446 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2447 {
2448 u32 rev;
2449
2450 pci_read_config_dword(dev, 0xf4, &rev);
2451
2452 /* Only CAP the MRRS if the device is a 5719 A0 */
2453 if (rev == 0x05719000) {
2454 int readrq = pcie_get_readrq(dev);
2455 if (readrq > 2048)
2456 pcie_set_readrq(dev, 2048);
2457 }
2458 }
2459 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2460 PCI_DEVICE_ID_TIGON3_5719,
2461 quirk_brcm_5719_limit_mrrs);
2462
2463 /*
2464 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2465 * hide device 6 which configures the overflow device access containing the
2466 * DRBs - this is where we expose device 6.
2467 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2468 */
quirk_unhide_mch_dev6(struct pci_dev * dev)2469 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2470 {
2471 u8 reg;
2472
2473 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2474 pci_info(dev, "Enabling MCH 'Overflow' Device\n");
2475 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2476 }
2477 }
2478 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2479 quirk_unhide_mch_dev6);
2480 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2481 quirk_unhide_mch_dev6);
2482
2483 #ifdef CONFIG_PCI_MSI
2484 /*
2485 * Some chipsets do not support MSI. We cannot easily rely on setting
2486 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2487 * other buses controlled by the chipset even if Linux is not aware of it.
2488 * Instead of setting the flag on all buses in the machine, simply disable
2489 * MSI globally.
2490 */
quirk_disable_all_msi(struct pci_dev * dev)2491 static void quirk_disable_all_msi(struct pci_dev *dev)
2492 {
2493 pci_no_msi();
2494 pci_warn(dev, "MSI quirk detected; MSI disabled\n");
2495 }
2496 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2497 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2498 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2499 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2500 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2501 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2502 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2503 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2504
2505 /* Disable MSI on chipsets that are known to not support it */
quirk_disable_msi(struct pci_dev * dev)2506 static void quirk_disable_msi(struct pci_dev *dev)
2507 {
2508 if (dev->subordinate) {
2509 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2510 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2511 }
2512 }
2513 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2514 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2515 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2516
2517 /*
2518 * The APC bridge device in AMD 780 family northbridges has some random
2519 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2520 * we use the possible vendor/device IDs of the host bridge for the
2521 * declared quirk, and search for the APC bridge by slot number.
2522 */
quirk_amd_780_apc_msi(struct pci_dev * host_bridge)2523 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2524 {
2525 struct pci_dev *apc_bridge;
2526
2527 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2528 if (apc_bridge) {
2529 if (apc_bridge->device == 0x9602)
2530 quirk_disable_msi(apc_bridge);
2531 pci_dev_put(apc_bridge);
2532 }
2533 }
2534 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2535 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2536
2537 /*
2538 * Go through the list of HyperTransport capabilities and return 1 if a HT
2539 * MSI capability is found and enabled.
2540 */
msi_ht_cap_enabled(struct pci_dev * dev)2541 static int msi_ht_cap_enabled(struct pci_dev *dev)
2542 {
2543 int pos, ttl = PCI_FIND_CAP_TTL;
2544
2545 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2546 while (pos && ttl--) {
2547 u8 flags;
2548
2549 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2550 &flags) == 0) {
2551 pci_info(dev, "Found %s HT MSI Mapping\n",
2552 flags & HT_MSI_FLAGS_ENABLE ?
2553 "enabled" : "disabled");
2554 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2555 }
2556
2557 pos = pci_find_next_ht_capability(dev, pos,
2558 HT_CAPTYPE_MSI_MAPPING);
2559 }
2560 return 0;
2561 }
2562
2563 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
quirk_msi_ht_cap(struct pci_dev * dev)2564 static void quirk_msi_ht_cap(struct pci_dev *dev)
2565 {
2566 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2567 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2568 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2569 }
2570 }
2571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2572 quirk_msi_ht_cap);
2573
2574 /*
2575 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2576 * if the MSI capability is set in any of these mappings.
2577 */
quirk_nvidia_ck804_msi_ht_cap(struct pci_dev * dev)2578 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2579 {
2580 struct pci_dev *pdev;
2581
2582 if (!dev->subordinate)
2583 return;
2584
2585 /*
2586 * Check HT MSI cap on this chipset and the root one. A single one
2587 * having MSI is enough to be sure that MSI is supported.
2588 */
2589 pdev = pci_get_slot(dev->bus, 0);
2590 if (!pdev)
2591 return;
2592 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2593 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2594 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2595 }
2596 pci_dev_put(pdev);
2597 }
2598 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2599 quirk_nvidia_ck804_msi_ht_cap);
2600
2601 /* Force enable MSI mapping capability on HT bridges */
ht_enable_msi_mapping(struct pci_dev * dev)2602 static void ht_enable_msi_mapping(struct pci_dev *dev)
2603 {
2604 int pos, ttl = PCI_FIND_CAP_TTL;
2605
2606 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2607 while (pos && ttl--) {
2608 u8 flags;
2609
2610 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2611 &flags) == 0) {
2612 pci_info(dev, "Enabling HT MSI Mapping\n");
2613
2614 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2615 flags | HT_MSI_FLAGS_ENABLE);
2616 }
2617 pos = pci_find_next_ht_capability(dev, pos,
2618 HT_CAPTYPE_MSI_MAPPING);
2619 }
2620 }
2621 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2622 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2623 ht_enable_msi_mapping);
2624 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2625 ht_enable_msi_mapping);
2626
2627 /*
2628 * The P5N32-SLI motherboards from Asus have a problem with MSI
2629 * for the MCP55 NIC. It is not yet determined whether the MSI problem
2630 * also affects other devices. As for now, turn off MSI for this device.
2631 */
nvenet_msi_disable(struct pci_dev * dev)2632 static void nvenet_msi_disable(struct pci_dev *dev)
2633 {
2634 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2635
2636 if (board_name &&
2637 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2638 strstr(board_name, "P5N32-E SLI"))) {
2639 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2640 dev->no_msi = 1;
2641 }
2642 }
2643 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2644 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2645 nvenet_msi_disable);
2646
2647 /*
2648 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2649 * config register. This register controls the routing of legacy
2650 * interrupts from devices that route through the MCP55. If this register
2651 * is misprogrammed, interrupts are only sent to the BSP, unlike
2652 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2653 * having this register set properly prevents kdump from booting up
2654 * properly, so let's make sure that we have it set correctly.
2655 * Note that this is an undocumented register.
2656 */
nvbridge_check_legacy_irq_routing(struct pci_dev * dev)2657 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2658 {
2659 u32 cfg;
2660
2661 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2662 return;
2663
2664 pci_read_config_dword(dev, 0x74, &cfg);
2665
2666 if (cfg & ((1 << 2) | (1 << 15))) {
2667 printk(KERN_INFO "Rewriting IRQ routing register on MCP55\n");
2668 cfg &= ~((1 << 2) | (1 << 15));
2669 pci_write_config_dword(dev, 0x74, cfg);
2670 }
2671 }
2672 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2673 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2674 nvbridge_check_legacy_irq_routing);
2675 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2676 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2677 nvbridge_check_legacy_irq_routing);
2678
ht_check_msi_mapping(struct pci_dev * dev)2679 static int ht_check_msi_mapping(struct pci_dev *dev)
2680 {
2681 int pos, ttl = PCI_FIND_CAP_TTL;
2682 int found = 0;
2683
2684 /* Check if there is HT MSI cap or enabled on this device */
2685 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2686 while (pos && ttl--) {
2687 u8 flags;
2688
2689 if (found < 1)
2690 found = 1;
2691 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2692 &flags) == 0) {
2693 if (flags & HT_MSI_FLAGS_ENABLE) {
2694 if (found < 2) {
2695 found = 2;
2696 break;
2697 }
2698 }
2699 }
2700 pos = pci_find_next_ht_capability(dev, pos,
2701 HT_CAPTYPE_MSI_MAPPING);
2702 }
2703
2704 return found;
2705 }
2706
host_bridge_with_leaf(struct pci_dev * host_bridge)2707 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2708 {
2709 struct pci_dev *dev;
2710 int pos;
2711 int i, dev_no;
2712 int found = 0;
2713
2714 dev_no = host_bridge->devfn >> 3;
2715 for (i = dev_no + 1; i < 0x20; i++) {
2716 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2717 if (!dev)
2718 continue;
2719
2720 /* found next host bridge? */
2721 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2722 if (pos != 0) {
2723 pci_dev_put(dev);
2724 break;
2725 }
2726
2727 if (ht_check_msi_mapping(dev)) {
2728 found = 1;
2729 pci_dev_put(dev);
2730 break;
2731 }
2732 pci_dev_put(dev);
2733 }
2734
2735 return found;
2736 }
2737
2738 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2739 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2740
is_end_of_ht_chain(struct pci_dev * dev)2741 static int is_end_of_ht_chain(struct pci_dev *dev)
2742 {
2743 int pos, ctrl_off;
2744 int end = 0;
2745 u16 flags, ctrl;
2746
2747 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2748
2749 if (!pos)
2750 goto out;
2751
2752 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2753
2754 ctrl_off = ((flags >> 10) & 1) ?
2755 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2756 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2757
2758 if (ctrl & (1 << 6))
2759 end = 1;
2760
2761 out:
2762 return end;
2763 }
2764
nv_ht_enable_msi_mapping(struct pci_dev * dev)2765 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2766 {
2767 struct pci_dev *host_bridge;
2768 int pos;
2769 int i, dev_no;
2770 int found = 0;
2771
2772 dev_no = dev->devfn >> 3;
2773 for (i = dev_no; i >= 0; i--) {
2774 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2775 if (!host_bridge)
2776 continue;
2777
2778 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2779 if (pos != 0) {
2780 found = 1;
2781 break;
2782 }
2783 pci_dev_put(host_bridge);
2784 }
2785
2786 if (!found)
2787 return;
2788
2789 /* don't enable end_device/host_bridge with leaf directly here */
2790 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2791 host_bridge_with_leaf(host_bridge))
2792 goto out;
2793
2794 /* root did that ! */
2795 if (msi_ht_cap_enabled(host_bridge))
2796 goto out;
2797
2798 ht_enable_msi_mapping(dev);
2799
2800 out:
2801 pci_dev_put(host_bridge);
2802 }
2803
ht_disable_msi_mapping(struct pci_dev * dev)2804 static void ht_disable_msi_mapping(struct pci_dev *dev)
2805 {
2806 int pos, ttl = PCI_FIND_CAP_TTL;
2807
2808 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2809 while (pos && ttl--) {
2810 u8 flags;
2811
2812 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2813 &flags) == 0) {
2814 pci_info(dev, "Disabling HT MSI Mapping\n");
2815
2816 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2817 flags & ~HT_MSI_FLAGS_ENABLE);
2818 }
2819 pos = pci_find_next_ht_capability(dev, pos,
2820 HT_CAPTYPE_MSI_MAPPING);
2821 }
2822 }
2823
__nv_msi_ht_cap_quirk(struct pci_dev * dev,int all)2824 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2825 {
2826 struct pci_dev *host_bridge;
2827 int pos;
2828 int found;
2829
2830 if (!pci_msi_enabled())
2831 return;
2832
2833 /* check if there is HT MSI cap or enabled on this device */
2834 found = ht_check_msi_mapping(dev);
2835
2836 /* no HT MSI CAP */
2837 if (found == 0)
2838 return;
2839
2840 /*
2841 * HT MSI mapping should be disabled on devices that are below
2842 * a non-Hypertransport host bridge. Locate the host bridge...
2843 */
2844 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
2845 PCI_DEVFN(0, 0));
2846 if (host_bridge == NULL) {
2847 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2848 return;
2849 }
2850
2851 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2852 if (pos != 0) {
2853 /* Host bridge is to HT */
2854 if (found == 1) {
2855 /* it is not enabled, try to enable it */
2856 if (all)
2857 ht_enable_msi_mapping(dev);
2858 else
2859 nv_ht_enable_msi_mapping(dev);
2860 }
2861 goto out;
2862 }
2863
2864 /* HT MSI is not enabled */
2865 if (found == 1)
2866 goto out;
2867
2868 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2869 ht_disable_msi_mapping(dev);
2870
2871 out:
2872 pci_dev_put(host_bridge);
2873 }
2874
nv_msi_ht_cap_quirk_all(struct pci_dev * dev)2875 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2876 {
2877 return __nv_msi_ht_cap_quirk(dev, 1);
2878 }
2879 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2880 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2881
nv_msi_ht_cap_quirk_leaf(struct pci_dev * dev)2882 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2883 {
2884 return __nv_msi_ht_cap_quirk(dev, 0);
2885 }
2886 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2887 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2888
quirk_msi_intx_disable_bug(struct pci_dev * dev)2889 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2890 {
2891 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2892 }
2893
quirk_msi_intx_disable_ati_bug(struct pci_dev * dev)2894 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2895 {
2896 struct pci_dev *p;
2897
2898 /*
2899 * SB700 MSI issue will be fixed at HW level from revision A21;
2900 * we need check PCI REVISION ID of SMBus controller to get SB700
2901 * revision.
2902 */
2903 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2904 NULL);
2905 if (!p)
2906 return;
2907
2908 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2909 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2910 pci_dev_put(p);
2911 }
2912
quirk_msi_intx_disable_qca_bug(struct pci_dev * dev)2913 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2914 {
2915 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2916 if (dev->revision < 0x18) {
2917 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
2918 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2919 }
2920 }
2921 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2922 PCI_DEVICE_ID_TIGON3_5780,
2923 quirk_msi_intx_disable_bug);
2924 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2925 PCI_DEVICE_ID_TIGON3_5780S,
2926 quirk_msi_intx_disable_bug);
2927 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2928 PCI_DEVICE_ID_TIGON3_5714,
2929 quirk_msi_intx_disable_bug);
2930 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2931 PCI_DEVICE_ID_TIGON3_5714S,
2932 quirk_msi_intx_disable_bug);
2933 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2934 PCI_DEVICE_ID_TIGON3_5715,
2935 quirk_msi_intx_disable_bug);
2936 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2937 PCI_DEVICE_ID_TIGON3_5715S,
2938 quirk_msi_intx_disable_bug);
2939
2940 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2941 quirk_msi_intx_disable_ati_bug);
2942 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2943 quirk_msi_intx_disable_ati_bug);
2944 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2945 quirk_msi_intx_disable_ati_bug);
2946 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2947 quirk_msi_intx_disable_ati_bug);
2948 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2949 quirk_msi_intx_disable_ati_bug);
2950
2951 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2952 quirk_msi_intx_disable_bug);
2953 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2954 quirk_msi_intx_disable_bug);
2955 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2956 quirk_msi_intx_disable_bug);
2957
2958 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2959 quirk_msi_intx_disable_bug);
2960 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2961 quirk_msi_intx_disable_bug);
2962 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2963 quirk_msi_intx_disable_bug);
2964 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2965 quirk_msi_intx_disable_bug);
2966 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2967 quirk_msi_intx_disable_bug);
2968 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2969 quirk_msi_intx_disable_bug);
2970 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2971 quirk_msi_intx_disable_qca_bug);
2972 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2973 quirk_msi_intx_disable_qca_bug);
2974 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2975 quirk_msi_intx_disable_qca_bug);
2976 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2977 quirk_msi_intx_disable_qca_bug);
2978 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2979 quirk_msi_intx_disable_qca_bug);
2980 #endif /* CONFIG_PCI_MSI */
2981
2982 /*
2983 * Allow manual resource allocation for PCI hotplug bridges via
2984 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
2985 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
2986 * allocate resources when hotplug device is inserted and PCI bus is
2987 * rescanned.
2988 */
quirk_hotplug_bridge(struct pci_dev * dev)2989 static void quirk_hotplug_bridge(struct pci_dev *dev)
2990 {
2991 dev->is_hotplug_bridge = 1;
2992 }
2993 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2994
2995 /*
2996 * This is a quirk for the Ricoh MMC controller found as a part of some
2997 * multifunction chips.
2998 *
2999 * This is very similar and based on the ricoh_mmc driver written by
3000 * Philip Langdale. Thank you for these magic sequences.
3001 *
3002 * These chips implement the four main memory card controllers (SD, MMC,
3003 * MS, xD) and one or both of CardBus or FireWire.
3004 *
3005 * It happens that they implement SD and MMC support as separate
3006 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
3007 * cards but the chip detects MMC cards in hardware and directs them to the
3008 * MMC controller - so the SDHCI driver never sees them.
3009 *
3010 * To get around this, we must disable the useless MMC controller. At that
3011 * point, the SDHCI controller will start seeing them. It seems to be the
3012 * case that the relevant PCI registers to deactivate the MMC controller
3013 * live on PCI function 0, which might be the CardBus controller or the
3014 * FireWire controller, depending on the particular chip in question
3015 *
3016 * This has to be done early, because as soon as we disable the MMC controller
3017 * other PCI functions shift up one level, e.g. function #2 becomes function
3018 * #1, and this will confuse the PCI core.
3019 */
3020 #ifdef CONFIG_MMC_RICOH_MMC
ricoh_mmc_fixup_rl5c476(struct pci_dev * dev)3021 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
3022 {
3023 u8 write_enable;
3024 u8 write_target;
3025 u8 disable;
3026
3027 /*
3028 * Disable via CardBus interface
3029 *
3030 * This must be done via function #0
3031 */
3032 if (PCI_FUNC(dev->devfn))
3033 return;
3034
3035 pci_read_config_byte(dev, 0xB7, &disable);
3036 if (disable & 0x02)
3037 return;
3038
3039 pci_read_config_byte(dev, 0x8E, &write_enable);
3040 pci_write_config_byte(dev, 0x8E, 0xAA);
3041 pci_read_config_byte(dev, 0x8D, &write_target);
3042 pci_write_config_byte(dev, 0x8D, 0xB7);
3043 pci_write_config_byte(dev, 0xB7, disable | 0x02);
3044 pci_write_config_byte(dev, 0x8E, write_enable);
3045 pci_write_config_byte(dev, 0x8D, write_target);
3046
3047 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
3048 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3049 }
3050 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3051 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3052
ricoh_mmc_fixup_r5c832(struct pci_dev * dev)3053 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
3054 {
3055 u8 write_enable;
3056 u8 disable;
3057
3058 /*
3059 * Disable via FireWire interface
3060 *
3061 * This must be done via function #0
3062 */
3063 if (PCI_FUNC(dev->devfn))
3064 return;
3065 /*
3066 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
3067 * certain types of SD/MMC cards. Lowering the SD base clock
3068 * frequency from 200Mhz to 50Mhz fixes this issue.
3069 *
3070 * 0x150 - SD2.0 mode enable for changing base clock
3071 * frequency to 50Mhz
3072 * 0xe1 - Base clock frequency
3073 * 0x32 - 50Mhz new clock frequency
3074 * 0xf9 - Key register for 0x150
3075 * 0xfc - key register for 0xe1
3076 */
3077 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
3078 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
3079 pci_write_config_byte(dev, 0xf9, 0xfc);
3080 pci_write_config_byte(dev, 0x150, 0x10);
3081 pci_write_config_byte(dev, 0xf9, 0x00);
3082 pci_write_config_byte(dev, 0xfc, 0x01);
3083 pci_write_config_byte(dev, 0xe1, 0x32);
3084 pci_write_config_byte(dev, 0xfc, 0x00);
3085
3086 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
3087 }
3088
3089 pci_read_config_byte(dev, 0xCB, &disable);
3090
3091 if (disable & 0x02)
3092 return;
3093
3094 pci_read_config_byte(dev, 0xCA, &write_enable);
3095 pci_write_config_byte(dev, 0xCA, 0x57);
3096 pci_write_config_byte(dev, 0xCB, disable | 0x02);
3097 pci_write_config_byte(dev, 0xCA, write_enable);
3098
3099 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
3100 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3101
3102 }
3103 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3104 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3105 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3106 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3107 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3108 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3109 #endif /*CONFIG_MMC_RICOH_MMC*/
3110
3111 #ifdef CONFIG_DMAR_TABLE
3112 #define VTUNCERRMSK_REG 0x1ac
3113 #define VTD_MSK_SPEC_ERRORS (1 << 31)
3114 /*
3115 * This is a quirk for masking VT-d spec-defined errors to platform error
3116 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
3117 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3118 * on the RAS config settings of the platform) when a VT-d fault happens.
3119 * The resulting SMI caused the system to hang.
3120 *
3121 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3122 * need to report the same error through other channels.
3123 */
vtd_mask_spec_errors(struct pci_dev * dev)3124 static void vtd_mask_spec_errors(struct pci_dev *dev)
3125 {
3126 u32 word;
3127
3128 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
3129 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
3130 }
3131 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3132 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3133 #endif
3134
fixup_ti816x_class(struct pci_dev * dev)3135 static void fixup_ti816x_class(struct pci_dev *dev)
3136 {
3137 u32 class = dev->class;
3138
3139 /* TI 816x devices do not have class code set when in PCIe boot mode */
3140 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
3141 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
3142 class, dev->class);
3143 }
3144 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3145 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
3146
3147 /*
3148 * Some PCIe devices do not work reliably with the claimed maximum
3149 * payload size supported.
3150 */
fixup_mpss_256(struct pci_dev * dev)3151 static void fixup_mpss_256(struct pci_dev *dev)
3152 {
3153 dev->pcie_mpss = 1; /* 256 bytes */
3154 }
3155 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3156 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3157 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3158 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3159 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3160 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3161 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256);
3162
3163 /*
3164 * Intel 5000 and 5100 Memory controllers have an erratum with read completion
3165 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3166 * Since there is no way of knowing what the PCIe MPS on each fabric will be
3167 * until all of the devices are discovered and buses walked, read completion
3168 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3169 * it is possible to hotplug a device with MPS of 256B.
3170 */
quirk_intel_mc_errata(struct pci_dev * dev)3171 static void quirk_intel_mc_errata(struct pci_dev *dev)
3172 {
3173 int err;
3174 u16 rcc;
3175
3176 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3177 pcie_bus_config == PCIE_BUS_DEFAULT)
3178 return;
3179
3180 /*
3181 * Intel erratum specifies bits to change but does not say what
3182 * they are. Keeping them magical until such time as the registers
3183 * and values can be explained.
3184 */
3185 err = pci_read_config_word(dev, 0x48, &rcc);
3186 if (err) {
3187 pci_err(dev, "Error attempting to read the read completion coalescing register\n");
3188 return;
3189 }
3190
3191 if (!(rcc & (1 << 10)))
3192 return;
3193
3194 rcc &= ~(1 << 10);
3195
3196 err = pci_write_config_word(dev, 0x48, rcc);
3197 if (err) {
3198 pci_err(dev, "Error attempting to write the read completion coalescing register\n");
3199 return;
3200 }
3201
3202 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
3203 }
3204 /* Intel 5000 series memory controllers and ports 2-7 */
3205 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3206 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3207 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3208 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3209 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3210 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3211 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3212 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3213 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3214 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3215 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3216 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3217 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3218 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3219 /* Intel 5100 series memory controllers and ports 2-7 */
3220 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3221 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3222 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3223 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3224 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3225 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3226 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3227 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3228 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3229 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3230 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3231
3232 /*
3233 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3234 * To work around this, query the size it should be configured to by the
3235 * device and modify the resource end to correspond to this new size.
3236 */
quirk_intel_ntb(struct pci_dev * dev)3237 static void quirk_intel_ntb(struct pci_dev *dev)
3238 {
3239 int rc;
3240 u8 val;
3241
3242 rc = pci_read_config_byte(dev, 0x00D0, &val);
3243 if (rc)
3244 return;
3245
3246 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3247
3248 rc = pci_read_config_byte(dev, 0x00D1, &val);
3249 if (rc)
3250 return;
3251
3252 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3253 }
3254 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3256
3257 /*
3258 * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3259 * though no one is handling them (e.g., if the i915 driver is never
3260 * loaded). Additionally the interrupt destination is not set up properly
3261 * and the interrupt ends up -somewhere-.
3262 *
3263 * These spurious interrupts are "sticky" and the kernel disables the
3264 * (shared) interrupt line after 100,000+ generated interrupts.
3265 *
3266 * Fix it by disabling the still enabled interrupts. This resolves crashes
3267 * often seen on monitor unplug.
3268 */
3269 #define I915_DEIER_REG 0x4400c
disable_igfx_irq(struct pci_dev * dev)3270 static void disable_igfx_irq(struct pci_dev *dev)
3271 {
3272 void __iomem *regs = pci_iomap(dev, 0, 0);
3273 if (regs == NULL) {
3274 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
3275 return;
3276 }
3277
3278 /* Check if any interrupt line is still enabled */
3279 if (readl(regs + I915_DEIER_REG) != 0) {
3280 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3281
3282 writel(0, regs + I915_DEIER_REG);
3283 }
3284
3285 pci_iounmap(dev, regs);
3286 }
3287 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3288 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3289 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3290 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3291 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3292 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3293 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3294
3295 /*
3296 * PCI devices which are on Intel chips can skip the 10ms delay
3297 * before entering D3 mode.
3298 */
quirk_remove_d3_delay(struct pci_dev * dev)3299 static void quirk_remove_d3_delay(struct pci_dev *dev)
3300 {
3301 dev->d3_delay = 0;
3302 }
3303 /* C600 Series devices do not need 10ms d3_delay */
3304 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3305 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3306 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3307 /* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3308 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3309 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3310 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3311 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3312 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3313 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3314 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3315 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3316 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3317 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3318 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3319 /* Intel Cherrytrail devices do not need 10ms d3_delay */
3320 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3321 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3322 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3323 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3324 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3326 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3327 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3328 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3329
3330 /*
3331 * Some devices may pass our check in pci_intx_mask_supported() if
3332 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3333 * support this feature.
3334 */
quirk_broken_intx_masking(struct pci_dev * dev)3335 static void quirk_broken_intx_masking(struct pci_dev *dev)
3336 {
3337 dev->broken_intx_masking = 1;
3338 }
3339 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3340 quirk_broken_intx_masking);
3341 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3342 quirk_broken_intx_masking);
3343 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3344 quirk_broken_intx_masking);
3345
3346 /*
3347 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3348 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3349 *
3350 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3351 */
3352 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3353 quirk_broken_intx_masking);
3354
3355 /*
3356 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3357 * DisINTx can be set but the interrupt status bit is non-functional.
3358 */
3359 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3360 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3361 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3362 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3363 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3364 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3365 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3366 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3367 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3368 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3369 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3370 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3371 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3372 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3373 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3374 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3375
3376 static u16 mellanox_broken_intx_devs[] = {
3377 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3378 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3379 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3380 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3381 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3382 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3383 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3384 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3385 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3386 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3387 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3388 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3389 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3390 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3391 };
3392
3393 #define CONNECTX_4_CURR_MAX_MINOR 99
3394 #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3395
3396 /*
3397 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3398 * If so, don't mark it as broken.
3399 * FW minor > 99 means older FW version format and no INTx masking support.
3400 * FW minor < 14 means new FW version format and no INTx masking support.
3401 */
mellanox_check_broken_intx_masking(struct pci_dev * pdev)3402 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3403 {
3404 __be32 __iomem *fw_ver;
3405 u16 fw_major;
3406 u16 fw_minor;
3407 u16 fw_subminor;
3408 u32 fw_maj_min;
3409 u32 fw_sub_min;
3410 int i;
3411
3412 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3413 if (pdev->device == mellanox_broken_intx_devs[i]) {
3414 pdev->broken_intx_masking = 1;
3415 return;
3416 }
3417 }
3418
3419 /*
3420 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3421 * support so shouldn't be checked further
3422 */
3423 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3424 return;
3425
3426 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3427 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3428 return;
3429
3430 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3431 if (pci_enable_device_mem(pdev)) {
3432 pci_warn(pdev, "Can't enable device memory\n");
3433 return;
3434 }
3435
3436 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3437 if (!fw_ver) {
3438 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
3439 goto out;
3440 }
3441
3442 /* Reading from resource space should be 32b aligned */
3443 fw_maj_min = ioread32be(fw_ver);
3444 fw_sub_min = ioread32be(fw_ver + 1);
3445 fw_major = fw_maj_min & 0xffff;
3446 fw_minor = fw_maj_min >> 16;
3447 fw_subminor = fw_sub_min & 0xffff;
3448 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3449 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3450 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3451 fw_major, fw_minor, fw_subminor, pdev->device ==
3452 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3453 pdev->broken_intx_masking = 1;
3454 }
3455
3456 iounmap(fw_ver);
3457
3458 out:
3459 pci_disable_device(pdev);
3460 }
3461 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3462 mellanox_check_broken_intx_masking);
3463
quirk_no_bus_reset(struct pci_dev * dev)3464 static void quirk_no_bus_reset(struct pci_dev *dev)
3465 {
3466 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3467 }
3468
3469 /*
3470 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
3471 * prevented for those affected devices.
3472 */
quirk_nvidia_no_bus_reset(struct pci_dev * dev)3473 static void quirk_nvidia_no_bus_reset(struct pci_dev *dev)
3474 {
3475 if ((dev->device & 0xffc0) == 0x2340)
3476 quirk_no_bus_reset(dev);
3477 }
3478 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
3479 quirk_nvidia_no_bus_reset);
3480
3481 /*
3482 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3483 * The device will throw a Link Down error on AER-capable systems and
3484 * regardless of AER, config space of the device is never accessible again
3485 * and typically causes the system to hang or reset when access is attempted.
3486 * http://www.spinics.net/lists/linux-pci/msg34797.html
3487 */
3488 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3489 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3490 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3491 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3492 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3493 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset);
3494
3495 /*
3496 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3497 * reset when used with certain child devices. After the reset, config
3498 * accesses to the child may fail.
3499 */
3500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3501
3502 /*
3503 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS
3504 * automatically disables LTSSM when Secondary Bus Reset is received and
3505 * the device stops working. Prevent bus reset for these devices. With
3506 * this change, the device can be assigned to VMs with VFIO, but it will
3507 * leak state between VMs. Reference
3508 * https://e2e.ti.com/support/processors/f/791/t/954382
3509 */
3510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
3511
quirk_no_pm_reset(struct pci_dev * dev)3512 static void quirk_no_pm_reset(struct pci_dev *dev)
3513 {
3514 /*
3515 * We can't do a bus reset on root bus devices, but an ineffective
3516 * PM reset may be better than nothing.
3517 */
3518 if (!pci_is_root_bus(dev->bus))
3519 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3520 }
3521
3522 /*
3523 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3524 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3525 * to have no effect on the device: it retains the framebuffer contents and
3526 * monitor sync. Advertising this support makes other layers, like VFIO,
3527 * assume pci_reset_function() is viable for this device. Mark it as
3528 * unavailable to skip it when testing reset methods.
3529 */
3530 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3531 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3532
3533 /*
3534 * Thunderbolt controllers with broken MSI hotplug signaling:
3535 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3536 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3537 */
quirk_thunderbolt_hotplug_msi(struct pci_dev * pdev)3538 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3539 {
3540 if (pdev->is_hotplug_bridge &&
3541 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3542 pdev->revision <= 1))
3543 pdev->no_msi = 1;
3544 }
3545 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3546 quirk_thunderbolt_hotplug_msi);
3547 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3548 quirk_thunderbolt_hotplug_msi);
3549 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3550 quirk_thunderbolt_hotplug_msi);
3551 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3552 quirk_thunderbolt_hotplug_msi);
3553 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3554 quirk_thunderbolt_hotplug_msi);
3555
3556 #ifdef CONFIG_ACPI
3557 /*
3558 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3559 *
3560 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3561 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3562 * be present after resume if a device was plugged in before suspend.
3563 *
3564 * The Thunderbolt controller consists of a PCIe switch with downstream
3565 * bridges leading to the NHI and to the tunnel PCI bridges.
3566 *
3567 * This quirk cuts power to the whole chip. Therefore we have to apply it
3568 * during suspend_noirq of the upstream bridge.
3569 *
3570 * Power is automagically restored before resume. No action is needed.
3571 */
quirk_apple_poweroff_thunderbolt(struct pci_dev * dev)3572 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3573 {
3574 acpi_handle bridge, SXIO, SXFP, SXLV;
3575
3576 if (!x86_apple_machine)
3577 return;
3578 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3579 return;
3580
3581 /*
3582 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller.
3583 * We don't know how to turn it back on again, but firmware does,
3584 * so we can only use SXIO/SXFP/SXLF if we're suspending via
3585 * firmware.
3586 */
3587 if (!pm_suspend_via_firmware())
3588 return;
3589
3590 bridge = ACPI_HANDLE(&dev->dev);
3591 if (!bridge)
3592 return;
3593
3594 /*
3595 * SXIO and SXLV are present only on machines requiring this quirk.
3596 * Thunderbolt bridges in external devices might have the same
3597 * device ID as those on the host, but they will not have the
3598 * associated ACPI methods. This implicitly checks that we are at
3599 * the right bridge.
3600 */
3601 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3602 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3603 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3604 return;
3605 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");
3606
3607 /* magic sequence */
3608 acpi_execute_simple_method(SXIO, NULL, 1);
3609 acpi_execute_simple_method(SXFP, NULL, 0);
3610 msleep(300);
3611 acpi_execute_simple_method(SXLV, NULL, 0);
3612 acpi_execute_simple_method(SXIO, NULL, 0);
3613 acpi_execute_simple_method(SXLV, NULL, 0);
3614 }
3615 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3616 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3617 quirk_apple_poweroff_thunderbolt);
3618
3619 /*
3620 * Apple: Wait for the Thunderbolt controller to reestablish PCI tunnels
3621 *
3622 * During suspend the Thunderbolt controller is reset and all PCI
3623 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3624 * during resume. We have to manually wait for the NHI since there is
3625 * no parent child relationship between the NHI and the tunneled
3626 * bridges.
3627 */
quirk_apple_wait_for_thunderbolt(struct pci_dev * dev)3628 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3629 {
3630 struct pci_dev *sibling = NULL;
3631 struct pci_dev *nhi = NULL;
3632
3633 if (!x86_apple_machine)
3634 return;
3635 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3636 return;
3637
3638 /*
3639 * Find the NHI and confirm that we are a bridge on the Thunderbolt
3640 * host controller and not on a Thunderbolt endpoint.
3641 */
3642 sibling = pci_get_slot(dev->bus, 0x0);
3643 if (sibling == dev)
3644 goto out; /* we are the downstream bridge to the NHI */
3645 if (!sibling || !sibling->subordinate)
3646 goto out;
3647 nhi = pci_get_slot(sibling->subordinate, 0x0);
3648 if (!nhi)
3649 goto out;
3650 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3651 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3652 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
3653 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
3654 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3655 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3656 goto out;
3657 pci_info(dev, "quirk: waiting for Thunderbolt to reestablish PCI tunnels...\n");
3658 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3659 out:
3660 pci_dev_put(nhi);
3661 pci_dev_put(sibling);
3662 }
3663 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3664 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3665 quirk_apple_wait_for_thunderbolt);
3666 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3667 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3668 quirk_apple_wait_for_thunderbolt);
3669 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3670 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3671 quirk_apple_wait_for_thunderbolt);
3672 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3673 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
3674 quirk_apple_wait_for_thunderbolt);
3675 #endif
3676
3677 /*
3678 * Following are device-specific reset methods which can be used to
3679 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3680 * not available.
3681 */
reset_intel_82599_sfp_virtfn(struct pci_dev * dev,int probe)3682 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3683 {
3684 /*
3685 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3686 *
3687 * The 82599 supports FLR on VFs, but FLR support is reported only
3688 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3689 * Thus we must call pcie_flr() directly without first checking if it is
3690 * supported.
3691 */
3692 if (!probe)
3693 pcie_flr(dev);
3694 return 0;
3695 }
3696
3697 #define SOUTH_CHICKEN2 0xc2004
3698 #define PCH_PP_STATUS 0xc7200
3699 #define PCH_PP_CONTROL 0xc7204
3700 #define MSG_CTL 0x45010
3701 #define NSDE_PWR_STATE 0xd0100
3702 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3703
reset_ivb_igd(struct pci_dev * dev,int probe)3704 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3705 {
3706 void __iomem *mmio_base;
3707 unsigned long timeout;
3708 u32 val;
3709
3710 if (probe)
3711 return 0;
3712
3713 mmio_base = pci_iomap(dev, 0, 0);
3714 if (!mmio_base)
3715 return -ENOMEM;
3716
3717 iowrite32(0x00000002, mmio_base + MSG_CTL);
3718
3719 /*
3720 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3721 * driver loaded sets the right bits. However, this's a reset and
3722 * the bits have been set by i915 previously, so we clobber
3723 * SOUTH_CHICKEN2 register directly here.
3724 */
3725 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3726
3727 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3728 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3729
3730 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3731 do {
3732 val = ioread32(mmio_base + PCH_PP_STATUS);
3733 if ((val & 0xb0000000) == 0)
3734 goto reset_complete;
3735 msleep(10);
3736 } while (time_before(jiffies, timeout));
3737 pci_warn(dev, "timeout during reset\n");
3738
3739 reset_complete:
3740 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3741
3742 pci_iounmap(dev, mmio_base);
3743 return 0;
3744 }
3745
3746 /* Device-specific reset method for Chelsio T4-based adapters */
reset_chelsio_generic_dev(struct pci_dev * dev,int probe)3747 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3748 {
3749 u16 old_command;
3750 u16 msix_flags;
3751
3752 /*
3753 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3754 * that we have no device-specific reset method.
3755 */
3756 if ((dev->device & 0xf000) != 0x4000)
3757 return -ENOTTY;
3758
3759 /*
3760 * If this is the "probe" phase, return 0 indicating that we can
3761 * reset this device.
3762 */
3763 if (probe)
3764 return 0;
3765
3766 /*
3767 * T4 can wedge if there are DMAs in flight within the chip and Bus
3768 * Master has been disabled. We need to have it on till the Function
3769 * Level Reset completes. (BUS_MASTER is disabled in
3770 * pci_reset_function()).
3771 */
3772 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3773 pci_write_config_word(dev, PCI_COMMAND,
3774 old_command | PCI_COMMAND_MASTER);
3775
3776 /*
3777 * Perform the actual device function reset, saving and restoring
3778 * configuration information around the reset.
3779 */
3780 pci_save_state(dev);
3781
3782 /*
3783 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3784 * are disabled when an MSI-X interrupt message needs to be delivered.
3785 * So we briefly re-enable MSI-X interrupts for the duration of the
3786 * FLR. The pci_restore_state() below will restore the original
3787 * MSI-X state.
3788 */
3789 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3790 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3791 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3792 msix_flags |
3793 PCI_MSIX_FLAGS_ENABLE |
3794 PCI_MSIX_FLAGS_MASKALL);
3795
3796 pcie_flr(dev);
3797
3798 /*
3799 * Restore the configuration information (BAR values, etc.) including
3800 * the original PCI Configuration Space Command word, and return
3801 * success.
3802 */
3803 pci_restore_state(dev);
3804 pci_write_config_word(dev, PCI_COMMAND, old_command);
3805 return 0;
3806 }
3807
3808 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3809 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3810 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3811
3812 /*
3813 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
3814 * FLR where config space reads from the device return -1. We seem to be
3815 * able to avoid this condition if we disable the NVMe controller prior to
3816 * FLR. This quirk is generic for any NVMe class device requiring similar
3817 * assistance to quiesce the device prior to FLR.
3818 *
3819 * NVMe specification: https://nvmexpress.org/resources/specifications/
3820 * Revision 1.0e:
3821 * Chapter 2: Required and optional PCI config registers
3822 * Chapter 3: NVMe control registers
3823 * Chapter 7.3: Reset behavior
3824 */
nvme_disable_and_flr(struct pci_dev * dev,int probe)3825 static int nvme_disable_and_flr(struct pci_dev *dev, int probe)
3826 {
3827 void __iomem *bar;
3828 u16 cmd;
3829 u32 cfg;
3830
3831 if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
3832 !pcie_has_flr(dev) || !pci_resource_start(dev, 0))
3833 return -ENOTTY;
3834
3835 if (probe)
3836 return 0;
3837
3838 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
3839 if (!bar)
3840 return -ENOTTY;
3841
3842 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3843 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
3844
3845 cfg = readl(bar + NVME_REG_CC);
3846
3847 /* Disable controller if enabled */
3848 if (cfg & NVME_CC_ENABLE) {
3849 u32 cap = readl(bar + NVME_REG_CAP);
3850 unsigned long timeout;
3851
3852 /*
3853 * Per nvme_disable_ctrl() skip shutdown notification as it
3854 * could complete commands to the admin queue. We only intend
3855 * to quiesce the device before reset.
3856 */
3857 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);
3858
3859 writel(cfg, bar + NVME_REG_CC);
3860
3861 /*
3862 * Some controllers require an additional delay here, see
3863 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet
3864 * supported by this quirk.
3865 */
3866
3867 /* Cap register provides max timeout in 500ms increments */
3868 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
3869
3870 for (;;) {
3871 u32 status = readl(bar + NVME_REG_CSTS);
3872
3873 /* Ready status becomes zero on disable complete */
3874 if (!(status & NVME_CSTS_RDY))
3875 break;
3876
3877 msleep(100);
3878
3879 if (time_after(jiffies, timeout)) {
3880 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
3881 break;
3882 }
3883 }
3884 }
3885
3886 pci_iounmap(dev, bar);
3887
3888 pcie_flr(dev);
3889
3890 return 0;
3891 }
3892
3893 /*
3894 * Intel DC P3700 NVMe controller will timeout waiting for ready status
3895 * to change after NVMe enable if the driver starts interacting with the
3896 * device too soon after FLR. A 250ms delay after FLR has heuristically
3897 * proven to produce reliably working results for device assignment cases.
3898 */
delay_250ms_after_flr(struct pci_dev * dev,int probe)3899 static int delay_250ms_after_flr(struct pci_dev *dev, int probe)
3900 {
3901 if (!pcie_has_flr(dev))
3902 return -ENOTTY;
3903
3904 if (probe)
3905 return 0;
3906
3907 pcie_flr(dev);
3908
3909 msleep(250);
3910
3911 return 0;
3912 }
3913
3914 #define PCI_DEVICE_ID_HINIC_VF 0x375E
3915 #define HINIC_VF_FLR_TYPE 0x1000
3916 #define HINIC_VF_FLR_CAP_BIT (1UL << 30)
3917 #define HINIC_VF_OP 0xE80
3918 #define HINIC_VF_FLR_PROC_BIT (1UL << 18)
3919 #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */
3920
3921 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */
reset_hinic_vf_dev(struct pci_dev * pdev,int probe)3922 static int reset_hinic_vf_dev(struct pci_dev *pdev, int probe)
3923 {
3924 unsigned long timeout;
3925 void __iomem *bar;
3926 u32 val;
3927
3928 if (probe)
3929 return 0;
3930
3931 bar = pci_iomap(pdev, 0, 0);
3932 if (!bar)
3933 return -ENOTTY;
3934
3935 /* Get and check firmware capabilities */
3936 val = ioread32be(bar + HINIC_VF_FLR_TYPE);
3937 if (!(val & HINIC_VF_FLR_CAP_BIT)) {
3938 pci_iounmap(pdev, bar);
3939 return -ENOTTY;
3940 }
3941
3942 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */
3943 val = ioread32be(bar + HINIC_VF_OP);
3944 val = val | HINIC_VF_FLR_PROC_BIT;
3945 iowrite32be(val, bar + HINIC_VF_OP);
3946
3947 pcie_flr(pdev);
3948
3949 /*
3950 * The device must recapture its Bus and Device Numbers after FLR
3951 * in order generate Completions. Issue a config write to let the
3952 * device capture this information.
3953 */
3954 pci_write_config_word(pdev, PCI_VENDOR_ID, 0);
3955
3956 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */
3957 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT);
3958 do {
3959 val = ioread32be(bar + HINIC_VF_OP);
3960 if (!(val & HINIC_VF_FLR_PROC_BIT))
3961 goto reset_complete;
3962 msleep(20);
3963 } while (time_before(jiffies, timeout));
3964
3965 val = ioread32be(bar + HINIC_VF_OP);
3966 if (!(val & HINIC_VF_FLR_PROC_BIT))
3967 goto reset_complete;
3968
3969 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val);
3970
3971 reset_complete:
3972 pci_iounmap(pdev, bar);
3973
3974 return 0;
3975 }
3976
3977 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3978 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3979 reset_intel_82599_sfp_virtfn },
3980 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3981 reset_ivb_igd },
3982 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3983 reset_ivb_igd },
3984 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
3985 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
3986 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3987 reset_chelsio_generic_dev },
3988 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF,
3989 reset_hinic_vf_dev },
3990 { 0 }
3991 };
3992
3993 /*
3994 * These device-specific reset methods are here rather than in a driver
3995 * because when a host assigns a device to a guest VM, the host may need
3996 * to reset the device but probably doesn't have a driver for it.
3997 */
pci_dev_specific_reset(struct pci_dev * dev,int probe)3998 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3999 {
4000 const struct pci_dev_reset_methods *i;
4001
4002 for (i = pci_dev_reset_methods; i->reset; i++) {
4003 if ((i->vendor == dev->vendor ||
4004 i->vendor == (u16)PCI_ANY_ID) &&
4005 (i->device == dev->device ||
4006 i->device == (u16)PCI_ANY_ID))
4007 return i->reset(dev, probe);
4008 }
4009
4010 return -ENOTTY;
4011 }
4012
quirk_dma_func0_alias(struct pci_dev * dev)4013 static void quirk_dma_func0_alias(struct pci_dev *dev)
4014 {
4015 if (PCI_FUNC(dev->devfn) != 0)
4016 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
4017 }
4018
4019 /*
4020 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
4021 *
4022 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
4023 */
4024 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
4025 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
4026
quirk_dma_func1_alias(struct pci_dev * dev)4027 static void quirk_dma_func1_alias(struct pci_dev *dev)
4028 {
4029 if (PCI_FUNC(dev->devfn) != 1)
4030 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
4031 }
4032
4033 /*
4034 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
4035 * SKUs function 1 is present and is a legacy IDE controller, in other
4036 * SKUs this function is not present, making this a ghost requester.
4037 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
4038 */
4039 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
4040 quirk_dma_func1_alias);
4041 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
4042 quirk_dma_func1_alias);
4043 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */
4044 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125,
4045 quirk_dma_func1_alias);
4046 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
4047 quirk_dma_func1_alias);
4048 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
4049 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
4050 quirk_dma_func1_alias);
4051 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
4052 quirk_dma_func1_alias);
4053 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
4054 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
4055 quirk_dma_func1_alias);
4056 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
4057 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
4058 quirk_dma_func1_alias);
4059 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
4060 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
4061 quirk_dma_func1_alias);
4062 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
4063 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
4064 quirk_dma_func1_alias);
4065 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
4066 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
4067 quirk_dma_func1_alias);
4068 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */
4069 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215,
4070 quirk_dma_func1_alias);
4071 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
4072 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
4073 quirk_dma_func1_alias);
4074 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
4075 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
4076 quirk_dma_func1_alias);
4077 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235,
4078 quirk_dma_func1_alias);
4079 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
4080 quirk_dma_func1_alias);
4081 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
4082 quirk_dma_func1_alias);
4083 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
4084 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
4085 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
4086 quirk_dma_func1_alias);
4087 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
4088 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4089 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4090 quirk_dma_func1_alias);
4091
4092 /*
4093 * Some devices DMA with the wrong devfn, not just the wrong function.
4094 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
4095 * the alias is "fixed" and independent of the device devfn.
4096 *
4097 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
4098 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4099 * single device on the secondary bus. In reality, the single exposed
4100 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4101 * that provides a bridge to the internal bus of the I/O processor. The
4102 * controller supports private devices, which can be hidden from PCI config
4103 * space. In the case of the Adaptec 3405, a private device at 01.0
4104 * appears to be the DMA engine, which therefore needs to become a DMA
4105 * alias for the device.
4106 */
4107 static const struct pci_device_id fixed_dma_alias_tbl[] = {
4108 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4109 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
4110 .driver_data = PCI_DEVFN(1, 0) },
4111 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4112 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
4113 .driver_data = PCI_DEVFN(1, 0) },
4114 { 0 }
4115 };
4116
quirk_fixed_dma_alias(struct pci_dev * dev)4117 static void quirk_fixed_dma_alias(struct pci_dev *dev)
4118 {
4119 const struct pci_device_id *id;
4120
4121 id = pci_match_id(fixed_dma_alias_tbl, dev);
4122 if (id)
4123 pci_add_dma_alias(dev, id->driver_data);
4124 }
4125
4126 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4127
4128 /*
4129 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4130 * using the wrong DMA alias for the device. Some of these devices can be
4131 * used as either forward or reverse bridges, so we need to test whether the
4132 * device is operating in the correct mode. We could probably apply this
4133 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
4134 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4135 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4136 */
quirk_use_pcie_bridge_dma_alias(struct pci_dev * pdev)4137 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
4138 {
4139 if (!pci_is_root_bus(pdev->bus) &&
4140 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4141 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
4142 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
4143 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
4144 }
4145 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
4146 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4147 quirk_use_pcie_bridge_dma_alias);
4148 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4149 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4150 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4151 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4152 /* ITE 8893 has the same problem as the 8892 */
4153 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4154 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4155 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4156
4157 /*
4158 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4159 * be added as aliases to the DMA device in order to allow buffer access
4160 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4161 * programmed in the EEPROM.
4162 */
quirk_mic_x200_dma_alias(struct pci_dev * pdev)4163 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
4164 {
4165 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0));
4166 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0));
4167 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3));
4168 }
4169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4171
4172 /*
4173 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4174 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx).
4175 *
4176 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access
4177 * when IOMMU is enabled. These aliases allow computational unit access to
4178 * host memory. These aliases mark the whole VCA device as one IOMMU
4179 * group.
4180 *
4181 * All possible slot numbers (0x20) are used, since we are unable to tell
4182 * what slot is used on other side. This quirk is intended for both host
4183 * and computational unit sides. The VCA devices have up to five functions
4184 * (four for DMA channels and one additional).
4185 */
quirk_pex_vca_alias(struct pci_dev * pdev)4186 static void quirk_pex_vca_alias(struct pci_dev *pdev)
4187 {
4188 const unsigned int num_pci_slots = 0x20;
4189 unsigned int slot;
4190
4191 for (slot = 0; slot < num_pci_slots; slot++) {
4192 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0));
4193 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x1));
4194 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x2));
4195 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x3));
4196 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x4));
4197 }
4198 }
4199 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
4200 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
4201 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias);
4202 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias);
4203 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias);
4204 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias);
4205
4206 /*
4207 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4208 * associated not at the root bus, but at a bridge below. This quirk avoids
4209 * generating invalid DMA aliases.
4210 */
quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev * pdev)4211 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
4212 {
4213 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
4214 }
4215 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4216 quirk_bridge_cavm_thrx2_pcie_root);
4217 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4218 quirk_bridge_cavm_thrx2_pcie_root);
4219
4220 /*
4221 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4222 * class code. Fix it.
4223 */
quirk_tw686x_class(struct pci_dev * pdev)4224 static void quirk_tw686x_class(struct pci_dev *pdev)
4225 {
4226 u32 class = pdev->class;
4227
4228 /* Use "Multimedia controller" class */
4229 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4230 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4231 class, pdev->class);
4232 }
4233 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4234 quirk_tw686x_class);
4235 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4236 quirk_tw686x_class);
4237 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4238 quirk_tw686x_class);
4239 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4240 quirk_tw686x_class);
4241
4242 /*
4243 * Some devices have problems with Transaction Layer Packets with the Relaxed
4244 * Ordering Attribute set. Such devices should mark themselves and other
4245 * device drivers should check before sending TLPs with RO set.
4246 */
quirk_relaxedordering_disable(struct pci_dev * dev)4247 static void quirk_relaxedordering_disable(struct pci_dev *dev)
4248 {
4249 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4250 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4251 }
4252
4253 /*
4254 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4255 * Complex have a Flow Control Credit issue which can cause performance
4256 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4257 */
4258 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4259 quirk_relaxedordering_disable);
4260 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4261 quirk_relaxedordering_disable);
4262 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4263 quirk_relaxedordering_disable);
4264 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4265 quirk_relaxedordering_disable);
4266 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4267 quirk_relaxedordering_disable);
4268 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4269 quirk_relaxedordering_disable);
4270 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4271 quirk_relaxedordering_disable);
4272 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4273 quirk_relaxedordering_disable);
4274 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4275 quirk_relaxedordering_disable);
4276 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4277 quirk_relaxedordering_disable);
4278 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4279 quirk_relaxedordering_disable);
4280 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4281 quirk_relaxedordering_disable);
4282 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4283 quirk_relaxedordering_disable);
4284 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4285 quirk_relaxedordering_disable);
4286 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4287 quirk_relaxedordering_disable);
4288 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4289 quirk_relaxedordering_disable);
4290 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4291 quirk_relaxedordering_disable);
4292 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4293 quirk_relaxedordering_disable);
4294 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4295 quirk_relaxedordering_disable);
4296 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4297 quirk_relaxedordering_disable);
4298 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4299 quirk_relaxedordering_disable);
4300 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4301 quirk_relaxedordering_disable);
4302 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4303 quirk_relaxedordering_disable);
4304 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4305 quirk_relaxedordering_disable);
4306 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4307 quirk_relaxedordering_disable);
4308 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4309 quirk_relaxedordering_disable);
4310 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4311 quirk_relaxedordering_disable);
4312 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4313 quirk_relaxedordering_disable);
4314
4315 /*
4316 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
4317 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4318 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4319 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4320 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4321 * November 10, 2010). As a result, on this platform we can't use Relaxed
4322 * Ordering for Upstream TLPs.
4323 */
4324 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4325 quirk_relaxedordering_disable);
4326 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4327 quirk_relaxedordering_disable);
4328 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4329 quirk_relaxedordering_disable);
4330
4331 /*
4332 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4333 * values for the Attribute as were supplied in the header of the
4334 * corresponding Request, except as explicitly allowed when IDO is used."
4335 *
4336 * If a non-compliant device generates a completion with a different
4337 * attribute than the request, the receiver may accept it (which itself
4338 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4339 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4340 * device access timeout.
4341 *
4342 * If the non-compliant device generates completions with zero attributes
4343 * (instead of copying the attributes from the request), we can work around
4344 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4345 * upstream devices so they always generate requests with zero attributes.
4346 *
4347 * This affects other devices under the same Root Port, but since these
4348 * attributes are performance hints, there should be no functional problem.
4349 *
4350 * Note that Configuration Space accesses are never supposed to have TLP
4351 * Attributes, so we're safe waiting till after any Configuration Space
4352 * accesses to do the Root Port fixup.
4353 */
quirk_disable_root_port_attributes(struct pci_dev * pdev)4354 static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4355 {
4356 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
4357
4358 if (!root_port) {
4359 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
4360 return;
4361 }
4362
4363 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4364 dev_name(&pdev->dev));
4365 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4366 PCI_EXP_DEVCTL_RELAX_EN |
4367 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4368 }
4369
4370 /*
4371 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4372 * Completion it generates.
4373 */
quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev * pdev)4374 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4375 {
4376 /*
4377 * This mask/compare operation selects for Physical Function 4 on a
4378 * T5. We only need to fix up the Root Port once for any of the
4379 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4380 * 0x54xx so we use that one.
4381 */
4382 if ((pdev->device & 0xff00) == 0x5400)
4383 quirk_disable_root_port_attributes(pdev);
4384 }
4385 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4386 quirk_chelsio_T5_disable_root_port_attributes);
4387
4388 /*
4389 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4390 * by a device
4391 * @acs_ctrl_req: Bitmask of desired ACS controls
4392 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by
4393 * the hardware design
4394 *
4395 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
4396 * in @acs_ctrl_ena, i.e., the device provides all the access controls the
4397 * caller desires. Return 0 otherwise.
4398 */
pci_acs_ctrl_enabled(u16 acs_ctrl_req,u16 acs_ctrl_ena)4399 static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena)
4400 {
4401 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req)
4402 return 1;
4403 return 0;
4404 }
4405
4406 /*
4407 * AMD has indicated that the devices below do not support peer-to-peer
4408 * in any system where they are found in the southbridge with an AMD
4409 * IOMMU in the system. Multifunction devices that do not support
4410 * peer-to-peer between functions can claim to support a subset of ACS.
4411 * Such devices effectively enable request redirect (RR) and completion
4412 * redirect (CR) since all transactions are redirected to the upstream
4413 * root complex.
4414 *
4415 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
4416 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
4417 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
4418 *
4419 * 1002:4385 SBx00 SMBus Controller
4420 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4421 * 1002:4383 SBx00 Azalia (Intel HDA)
4422 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4423 * 1002:4384 SBx00 PCI to PCI Bridge
4424 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4425 *
4426 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4427 *
4428 * 1022:780f [AMD] FCH PCI Bridge
4429 * 1022:7809 [AMD] FCH USB OHCI Controller
4430 */
pci_quirk_amd_sb_acs(struct pci_dev * dev,u16 acs_flags)4431 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4432 {
4433 #ifdef CONFIG_ACPI
4434 struct acpi_table_header *header = NULL;
4435 acpi_status status;
4436
4437 /* Targeting multifunction devices on the SB (appears on root bus) */
4438 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4439 return -ENODEV;
4440
4441 /* The IVRS table describes the AMD IOMMU */
4442 status = acpi_get_table("IVRS", 0, &header);
4443 if (ACPI_FAILURE(status))
4444 return -ENODEV;
4445
4446 acpi_put_table(header);
4447
4448 /* Filter out flags not applicable to multifunction */
4449 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4450
4451 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR);
4452 #else
4453 return -ENODEV;
4454 #endif
4455 }
4456
pci_quirk_cavium_acs_match(struct pci_dev * dev)4457 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4458 {
4459 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4460 return false;
4461
4462 switch (dev->device) {
4463 /*
4464 * Effectively selects all downstream ports for whole ThunderX1
4465 * (which represents 8 SoCs).
4466 */
4467 case 0xa000 ... 0xa7ff: /* ThunderX1 */
4468 case 0xaf84: /* ThunderX2 */
4469 case 0xb884: /* ThunderX3 */
4470 return true;
4471 default:
4472 return false;
4473 }
4474 }
4475
pci_quirk_cavium_acs(struct pci_dev * dev,u16 acs_flags)4476 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4477 {
4478 if (!pci_quirk_cavium_acs_match(dev))
4479 return -ENOTTY;
4480
4481 /*
4482 * Cavium Root Ports don't advertise an ACS capability. However,
4483 * the RTL internally implements similar protection as if ACS had
4484 * Source Validation, Request Redirection, Completion Redirection,
4485 * and Upstream Forwarding features enabled. Assert that the
4486 * hardware implements and enables equivalent ACS functionality for
4487 * these flags.
4488 */
4489 return pci_acs_ctrl_enabled(acs_flags,
4490 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4491 }
4492
pci_quirk_xgene_acs(struct pci_dev * dev,u16 acs_flags)4493 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4494 {
4495 /*
4496 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4497 * transactions with others, allowing masking out these bits as if they
4498 * were unimplemented in the ACS capability.
4499 */
4500 return pci_acs_ctrl_enabled(acs_flags,
4501 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4502 }
4503
4504 /*
4505 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4506 * transactions and validate bus numbers in requests, but do not provide an
4507 * actual PCIe ACS capability. This is the list of device IDs known to fall
4508 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4509 */
4510 static const u16 pci_quirk_intel_pch_acs_ids[] = {
4511 /* Ibexpeak PCH */
4512 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4513 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4514 /* Cougarpoint PCH */
4515 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4516 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4517 /* Pantherpoint PCH */
4518 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4519 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4520 /* Lynxpoint-H PCH */
4521 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4522 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4523 /* Lynxpoint-LP PCH */
4524 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4525 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4526 /* Wildcat PCH */
4527 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4528 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4529 /* Patsburg (X79) PCH */
4530 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4531 /* Wellsburg (X99) PCH */
4532 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4533 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4534 /* Lynx Point (9 series) PCH */
4535 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4536 };
4537
pci_quirk_intel_pch_acs_match(struct pci_dev * dev)4538 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4539 {
4540 int i;
4541
4542 /* Filter out a few obvious non-matches first */
4543 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4544 return false;
4545
4546 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4547 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4548 return true;
4549
4550 return false;
4551 }
4552
pci_quirk_intel_pch_acs(struct pci_dev * dev,u16 acs_flags)4553 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4554 {
4555 if (!pci_quirk_intel_pch_acs_match(dev))
4556 return -ENOTTY;
4557
4558 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
4559 return pci_acs_ctrl_enabled(acs_flags,
4560 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4561
4562 return pci_acs_ctrl_enabled(acs_flags, 0);
4563 }
4564
4565 /*
4566 * These QCOM Root Ports do provide ACS-like features to disable peer
4567 * transactions and validate bus numbers in requests, but do not provide an
4568 * actual PCIe ACS capability. Hardware supports source validation but it
4569 * will report the issue as Completer Abort instead of ACS Violation.
4570 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4571 * Complex with unique segment numbers. It is not possible for one Root
4572 * Port to pass traffic to another Root Port. All PCIe transactions are
4573 * terminated inside the Root Port.
4574 */
pci_quirk_qcom_rp_acs(struct pci_dev * dev,u16 acs_flags)4575 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4576 {
4577 return pci_acs_ctrl_enabled(acs_flags,
4578 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4579 }
4580
4581 /*
4582 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4583 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4584 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4585 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4586 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4587 * control register is at offset 8 instead of 6 and we should probably use
4588 * dword accesses to them. This applies to the following PCI Device IDs, as
4589 * found in volume 1 of the datasheet[2]:
4590 *
4591 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4592 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4593 *
4594 * N.B. This doesn't fix what lspci shows.
4595 *
4596 * The 100 series chipset specification update includes this as errata #23[3].
4597 *
4598 * The 200 series chipset (Union Point) has the same bug according to the
4599 * specification update (Intel 200 Series Chipset Family Platform Controller
4600 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4601 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4602 * chipset include:
4603 *
4604 * 0xa290-0xa29f PCI Express Root port #{0-16}
4605 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4606 *
4607 * Mobile chipsets are also affected, 7th & 8th Generation
4608 * Specification update confirms ACS errata 22, status no fix: (7th Generation
4609 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4610 * Processor Family I/O for U Quad Core Platforms Specification Update,
4611 * August 2017, Revision 002, Document#: 334660-002)[6]
4612 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4613 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4614 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4615 *
4616 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4617 *
4618 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4619 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4620 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4621 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4622 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4623 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4624 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4625 */
pci_quirk_intel_spt_pch_acs_match(struct pci_dev * dev)4626 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4627 {
4628 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4629 return false;
4630
4631 switch (dev->device) {
4632 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4633 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4634 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4635 return true;
4636 }
4637
4638 return false;
4639 }
4640
4641 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4642
pci_quirk_intel_spt_pch_acs(struct pci_dev * dev,u16 acs_flags)4643 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4644 {
4645 int pos;
4646 u32 cap, ctrl;
4647
4648 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4649 return -ENOTTY;
4650
4651 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4652 if (!pos)
4653 return -ENOTTY;
4654
4655 /* see pci_acs_flags_enabled() */
4656 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4657 acs_flags &= (cap | PCI_ACS_EC);
4658
4659 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4660
4661 return pci_acs_ctrl_enabled(acs_flags, ctrl);
4662 }
4663
pci_quirk_mf_endpoint_acs(struct pci_dev * dev,u16 acs_flags)4664 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4665 {
4666 /*
4667 * SV, TB, and UF are not relevant to multifunction endpoints.
4668 *
4669 * Multifunction devices are only required to implement RR, CR, and DT
4670 * in their ACS capability if they support peer-to-peer transactions.
4671 * Devices matching this quirk have been verified by the vendor to not
4672 * perform peer-to-peer with other functions, allowing us to mask out
4673 * these bits as if they were unimplemented in the ACS capability.
4674 */
4675 return pci_acs_ctrl_enabled(acs_flags,
4676 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4677 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4678 }
4679
pci_quirk_rciep_acs(struct pci_dev * dev,u16 acs_flags)4680 static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags)
4681 {
4682 /*
4683 * Intel RCiEP's are required to allow p2p only on translated
4684 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16,
4685 * "Root-Complex Peer to Peer Considerations".
4686 */
4687 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END)
4688 return -ENOTTY;
4689
4690 return pci_acs_ctrl_enabled(acs_flags,
4691 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4692 }
4693
pci_quirk_brcm_acs(struct pci_dev * dev,u16 acs_flags)4694 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
4695 {
4696 /*
4697 * iProc PAXB Root Ports don't advertise an ACS capability, but
4698 * they do not allow peer-to-peer transactions between Root Ports.
4699 * Allow each Root Port to be in a separate IOMMU group by masking
4700 * SV/RR/CR/UF bits.
4701 */
4702 return pci_acs_ctrl_enabled(acs_flags,
4703 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4704 }
4705
4706 static const struct pci_dev_acs_enabled {
4707 u16 vendor;
4708 u16 device;
4709 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4710 } pci_dev_acs_enabled[] = {
4711 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4712 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4713 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4714 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4715 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4716 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4717 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4718 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4719 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4720 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4721 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4722 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4723 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4724 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4725 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4726 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4727 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4728 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4729 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4730 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4731 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4732 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4733 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4734 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4735 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4736 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4737 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4738 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4739 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4740 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4741 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4742 /* 82580 */
4743 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4744 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4745 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4746 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4747 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4748 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4749 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4750 /* 82576 */
4751 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4752 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4753 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4754 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4755 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4756 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4757 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4758 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4759 /* 82575 */
4760 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4761 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4762 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4763 /* I350 */
4764 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4765 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4766 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4767 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4768 /* 82571 (Quads omitted due to non-ACS switch) */
4769 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4770 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4771 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4772 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4773 /* I219 */
4774 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4775 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4776 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs },
4777 /* QCOM QDF2xxx root ports */
4778 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
4779 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
4780 /* Intel PCH root ports */
4781 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4782 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4783 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4784 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4785 /* Cavium ThunderX */
4786 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4787 /* Cavium multi-function devices */
4788 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs },
4789 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs },
4790 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },
4791 /* APM X-Gene */
4792 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
4793 /* Ampere Computing */
4794 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
4795 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
4796 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
4797 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
4798 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
4799 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
4800 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
4801 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
4802 /* Broadcom multi-function device */
4803 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs },
4804 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs },
4805 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs },
4806 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs },
4807 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
4808 { 0 }
4809 };
4810
4811 /*
4812 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
4813 * @dev: PCI device
4814 * @acs_flags: Bitmask of desired ACS controls
4815 *
4816 * Returns:
4817 * -ENOTTY: No quirk applies to this device; we can't tell whether the
4818 * device provides the desired controls
4819 * 0: Device does not provide all the desired controls
4820 * >0: Device provides all the controls in @acs_flags
4821 */
pci_dev_specific_acs_enabled(struct pci_dev * dev,u16 acs_flags)4822 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4823 {
4824 const struct pci_dev_acs_enabled *i;
4825 int ret;
4826
4827 /*
4828 * Allow devices that do not expose standard PCIe ACS capabilities
4829 * or control to indicate their support here. Multi-function express
4830 * devices which do not allow internal peer-to-peer between functions,
4831 * but do not implement PCIe ACS may wish to return true here.
4832 */
4833 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4834 if ((i->vendor == dev->vendor ||
4835 i->vendor == (u16)PCI_ANY_ID) &&
4836 (i->device == dev->device ||
4837 i->device == (u16)PCI_ANY_ID)) {
4838 ret = i->acs_enabled(dev, acs_flags);
4839 if (ret >= 0)
4840 return ret;
4841 }
4842 }
4843
4844 return -ENOTTY;
4845 }
4846
4847 /* Config space offset of Root Complex Base Address register */
4848 #define INTEL_LPC_RCBA_REG 0xf0
4849 /* 31:14 RCBA address */
4850 #define INTEL_LPC_RCBA_MASK 0xffffc000
4851 /* RCBA Enable */
4852 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
4853
4854 /* Backbone Scratch Pad Register */
4855 #define INTEL_BSPR_REG 0x1104
4856 /* Backbone Peer Non-Posted Disable */
4857 #define INTEL_BSPR_REG_BPNPD (1 << 8)
4858 /* Backbone Peer Posted Disable */
4859 #define INTEL_BSPR_REG_BPPD (1 << 9)
4860
4861 /* Upstream Peer Decode Configuration Register */
4862 #define INTEL_UPDCR_REG 0x1014
4863 /* 5:0 Peer Decode Enable bits */
4864 #define INTEL_UPDCR_REG_MASK 0x3f
4865
pci_quirk_enable_intel_lpc_acs(struct pci_dev * dev)4866 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4867 {
4868 u32 rcba, bspr, updcr;
4869 void __iomem *rcba_mem;
4870
4871 /*
4872 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4873 * are D28:F* and therefore get probed before LPC, thus we can't
4874 * use pci_get_slot()/pci_read_config_dword() here.
4875 */
4876 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4877 INTEL_LPC_RCBA_REG, &rcba);
4878 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4879 return -EINVAL;
4880
4881 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4882 PAGE_ALIGN(INTEL_UPDCR_REG));
4883 if (!rcba_mem)
4884 return -ENOMEM;
4885
4886 /*
4887 * The BSPR can disallow peer cycles, but it's set by soft strap and
4888 * therefore read-only. If both posted and non-posted peer cycles are
4889 * disallowed, we're ok. If either are allowed, then we need to use
4890 * the UPDCR to disable peer decodes for each port. This provides the
4891 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4892 */
4893 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4894 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4895 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4896 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4897 if (updcr & INTEL_UPDCR_REG_MASK) {
4898 pci_info(dev, "Disabling UPDCR peer decodes\n");
4899 updcr &= ~INTEL_UPDCR_REG_MASK;
4900 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4901 }
4902 }
4903
4904 iounmap(rcba_mem);
4905 return 0;
4906 }
4907
4908 /* Miscellaneous Port Configuration register */
4909 #define INTEL_MPC_REG 0xd8
4910 /* MPC: Invalid Receive Bus Number Check Enable */
4911 #define INTEL_MPC_REG_IRBNCE (1 << 26)
4912
pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev * dev)4913 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4914 {
4915 u32 mpc;
4916
4917 /*
4918 * When enabled, the IRBNCE bit of the MPC register enables the
4919 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4920 * ensures that requester IDs fall within the bus number range
4921 * of the bridge. Enable if not already.
4922 */
4923 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4924 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4925 pci_info(dev, "Enabling MPC IRBNCE\n");
4926 mpc |= INTEL_MPC_REG_IRBNCE;
4927 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4928 }
4929 }
4930
pci_quirk_enable_intel_pch_acs(struct pci_dev * dev)4931 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4932 {
4933 if (!pci_quirk_intel_pch_acs_match(dev))
4934 return -ENOTTY;
4935
4936 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4937 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
4938 return 0;
4939 }
4940
4941 pci_quirk_enable_intel_rp_mpc_acs(dev);
4942
4943 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4944
4945 pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
4946
4947 return 0;
4948 }
4949
pci_quirk_enable_intel_spt_pch_acs(struct pci_dev * dev)4950 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
4951 {
4952 int pos;
4953 u32 cap, ctrl;
4954
4955 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4956 return -ENOTTY;
4957
4958 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4959 if (!pos)
4960 return -ENOTTY;
4961
4962 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4963 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4964
4965 ctrl |= (cap & PCI_ACS_SV);
4966 ctrl |= (cap & PCI_ACS_RR);
4967 ctrl |= (cap & PCI_ACS_CR);
4968 ctrl |= (cap & PCI_ACS_UF);
4969
4970 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4971
4972 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
4973
4974 return 0;
4975 }
4976
pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev * dev)4977 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
4978 {
4979 int pos;
4980 u32 cap, ctrl;
4981
4982 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4983 return -ENOTTY;
4984
4985 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4986 if (!pos)
4987 return -ENOTTY;
4988
4989 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4990 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4991
4992 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
4993
4994 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4995
4996 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
4997
4998 return 0;
4999 }
5000
5001 static const struct pci_dev_acs_ops {
5002 u16 vendor;
5003 u16 device;
5004 int (*enable_acs)(struct pci_dev *dev);
5005 int (*disable_acs_redir)(struct pci_dev *dev);
5006 } pci_dev_acs_ops[] = {
5007 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5008 .enable_acs = pci_quirk_enable_intel_pch_acs,
5009 },
5010 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5011 .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
5012 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
5013 },
5014 };
5015
pci_dev_specific_enable_acs(struct pci_dev * dev)5016 int pci_dev_specific_enable_acs(struct pci_dev *dev)
5017 {
5018 const struct pci_dev_acs_ops *p;
5019 int i, ret;
5020
5021 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5022 p = &pci_dev_acs_ops[i];
5023 if ((p->vendor == dev->vendor ||
5024 p->vendor == (u16)PCI_ANY_ID) &&
5025 (p->device == dev->device ||
5026 p->device == (u16)PCI_ANY_ID) &&
5027 p->enable_acs) {
5028 ret = p->enable_acs(dev);
5029 if (ret >= 0)
5030 return ret;
5031 }
5032 }
5033
5034 return -ENOTTY;
5035 }
5036
pci_dev_specific_disable_acs_redir(struct pci_dev * dev)5037 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
5038 {
5039 const struct pci_dev_acs_ops *p;
5040 int i, ret;
5041
5042 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5043 p = &pci_dev_acs_ops[i];
5044 if ((p->vendor == dev->vendor ||
5045 p->vendor == (u16)PCI_ANY_ID) &&
5046 (p->device == dev->device ||
5047 p->device == (u16)PCI_ANY_ID) &&
5048 p->disable_acs_redir) {
5049 ret = p->disable_acs_redir(dev);
5050 if (ret >= 0)
5051 return ret;
5052 }
5053 }
5054
5055 return -ENOTTY;
5056 }
5057
5058 /*
5059 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5060 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
5061 * Next Capability pointer in the MSI Capability Structure should point to
5062 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
5063 * the list.
5064 */
quirk_intel_qat_vf_cap(struct pci_dev * pdev)5065 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
5066 {
5067 int pos, i = 0;
5068 u8 next_cap;
5069 u16 reg16, *cap;
5070 struct pci_cap_saved_state *state;
5071
5072 /* Bail if the hardware bug is fixed */
5073 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
5074 return;
5075
5076 /* Bail if MSI Capability Structure is not found for some reason */
5077 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
5078 if (!pos)
5079 return;
5080
5081 /*
5082 * Bail if Next Capability pointer in the MSI Capability Structure
5083 * is not the expected incorrect 0x00.
5084 */
5085 pci_read_config_byte(pdev, pos + 1, &next_cap);
5086 if (next_cap)
5087 return;
5088
5089 /*
5090 * PCIe Capability Structure is expected to be at 0x50 and should
5091 * terminate the list (Next Capability pointer is 0x00). Verify
5092 * Capability Id and Next Capability pointer is as expected.
5093 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
5094 * to correctly set kernel data structures which have already been
5095 * set incorrectly due to the hardware bug.
5096 */
5097 pos = 0x50;
5098 pci_read_config_word(pdev, pos, ®16);
5099 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
5100 u32 status;
5101 #ifndef PCI_EXP_SAVE_REGS
5102 #define PCI_EXP_SAVE_REGS 7
5103 #endif
5104 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
5105
5106 pdev->pcie_cap = pos;
5107 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
5108 pdev->pcie_flags_reg = reg16;
5109 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
5110 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
5111
5112 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
5113 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
5114 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
5115 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
5116
5117 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
5118 return;
5119
5120 /* Save PCIe cap */
5121 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
5122 if (!state)
5123 return;
5124
5125 state->cap.cap_nr = PCI_CAP_ID_EXP;
5126 state->cap.cap_extended = 0;
5127 state->cap.size = size;
5128 cap = (u16 *)&state->cap.data[0];
5129 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
5130 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
5131 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
5132 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
5133 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
5134 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
5135 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
5136 hlist_add_head(&state->next, &pdev->saved_cap_space);
5137 }
5138 }
5139 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
5140
5141 /*
5142 * FLR may cause the following to devices to hang:
5143 *
5144 * AMD Starship/Matisse HD Audio Controller 0x1487
5145 * AMD Starship USB 3.0 Host Controller 0x148c
5146 * AMD Matisse USB 3.0 Host Controller 0x149c
5147 * Intel 82579LM Gigabit Ethernet Controller 0x1502
5148 * Intel 82579V Gigabit Ethernet Controller 0x1503
5149 *
5150 */
quirk_no_flr(struct pci_dev * dev)5151 static void quirk_no_flr(struct pci_dev *dev)
5152 {
5153 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
5154 }
5155 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);
5156 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr);
5157 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);
5158 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr);
5159 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
5160 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
5161
quirk_no_ext_tags(struct pci_dev * pdev)5162 static void quirk_no_ext_tags(struct pci_dev *pdev)
5163 {
5164 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
5165
5166 if (!bridge)
5167 return;
5168
5169 bridge->no_ext_tags = 1;
5170 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
5171
5172 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
5173 }
5174 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5175 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5176 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
5177 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
5178 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
5179 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
5180 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
5181
5182 #ifdef CONFIG_PCI_ATS
5183 /*
5184 * Some devices require additional driver setup to enable ATS. Don't use
5185 * ATS for those devices as ATS will be enabled before the driver has had a
5186 * chance to load and configure the device.
5187 */
quirk_amd_harvest_no_ats(struct pci_dev * pdev)5188 static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)
5189 {
5190 if ((pdev->device == 0x7312 && pdev->revision != 0x00) ||
5191 (pdev->device == 0x7340 && pdev->revision != 0xc5) ||
5192 (pdev->device == 0x7341 && pdev->revision != 0x00))
5193 return;
5194
5195 pci_info(pdev, "disabling ATS\n");
5196 pdev->ats_cap = 0;
5197 }
5198
5199 /* AMD Stoney platform GPU */
5200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
5201 /* AMD Iceland dGPU */
5202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
5203 /* AMD Navi10 dGPU */
5204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
5205 /* AMD Navi14 dGPU */
5206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
5207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
5208 #endif /* CONFIG_PCI_ATS */
5209
5210 /* Freescale PCIe doesn't support MSI in RC mode */
quirk_fsl_no_msi(struct pci_dev * pdev)5211 static void quirk_fsl_no_msi(struct pci_dev *pdev)
5212 {
5213 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
5214 pdev->no_msi = 1;
5215 }
5216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
5217
5218 /*
5219 * Although not allowed by the spec, some multi-function devices have
5220 * dependencies of one function (consumer) on another (supplier). For the
5221 * consumer to work in D0, the supplier must also be in D0. Create a
5222 * device link from the consumer to the supplier to enforce this
5223 * dependency. Runtime PM is allowed by default on the consumer to prevent
5224 * it from permanently keeping the supplier awake.
5225 */
pci_create_device_link(struct pci_dev * pdev,unsigned int consumer,unsigned int supplier,unsigned int class,unsigned int class_shift)5226 static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
5227 unsigned int supplier, unsigned int class,
5228 unsigned int class_shift)
5229 {
5230 struct pci_dev *supplier_pdev;
5231
5232 if (PCI_FUNC(pdev->devfn) != consumer)
5233 return;
5234
5235 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
5236 pdev->bus->number,
5237 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
5238 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
5239 pci_dev_put(supplier_pdev);
5240 return;
5241 }
5242
5243 if (device_link_add(&pdev->dev, &supplier_pdev->dev,
5244 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
5245 pci_info(pdev, "D0 power state depends on %s\n",
5246 pci_name(supplier_pdev));
5247 else
5248 pci_err(pdev, "Cannot enforce power dependency on %s\n",
5249 pci_name(supplier_pdev));
5250
5251 pm_runtime_allow(&pdev->dev);
5252 pci_dev_put(supplier_pdev);
5253 }
5254
5255 /*
5256 * Create device link for GPUs with integrated HDA controller for streaming
5257 * audio to attached displays.
5258 */
quirk_gpu_hda(struct pci_dev * hda)5259 static void quirk_gpu_hda(struct pci_dev *hda)
5260 {
5261 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16);
5262 }
5263 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5264 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5265 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
5266 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5267 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5268 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5269
5270 /*
5271 * Create device link for GPUs with integrated USB xHCI Host
5272 * controller to VGA.
5273 */
quirk_gpu_usb(struct pci_dev * usb)5274 static void quirk_gpu_usb(struct pci_dev *usb)
5275 {
5276 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16);
5277 }
5278 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5279 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5280 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5281 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5282
5283 /*
5284 * Create device link for GPUs with integrated Type-C UCSI controller
5285 * to VGA. Currently there is no class code defined for UCSI device over PCI
5286 * so using UNKNOWN class for now and it will be updated when UCSI
5287 * over PCI gets a class code.
5288 */
5289 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
quirk_gpu_usb_typec_ucsi(struct pci_dev * ucsi)5290 static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi)
5291 {
5292 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16);
5293 }
5294 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5295 PCI_CLASS_SERIAL_UNKNOWN, 8,
5296 quirk_gpu_usb_typec_ucsi);
5297 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5298 PCI_CLASS_SERIAL_UNKNOWN, 8,
5299 quirk_gpu_usb_typec_ucsi);
5300
5301 /*
5302 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
5303 * disabled. https://devtalk.nvidia.com/default/topic/1024022
5304 */
quirk_nvidia_hda(struct pci_dev * gpu)5305 static void quirk_nvidia_hda(struct pci_dev *gpu)
5306 {
5307 u8 hdr_type;
5308 u32 val;
5309
5310 /* There was no integrated HDA controller before MCP89 */
5311 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
5312 return;
5313
5314 /* Bit 25 at offset 0x488 enables the HDA controller */
5315 pci_read_config_dword(gpu, 0x488, &val);
5316 if (val & BIT(25))
5317 return;
5318
5319 pci_info(gpu, "Enabling HDA controller\n");
5320 pci_write_config_dword(gpu, 0x488, val | BIT(25));
5321
5322 /* The GPU becomes a multi-function device when the HDA is enabled */
5323 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type);
5324 gpu->multifunction = !!(hdr_type & 0x80);
5325 }
5326 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5327 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5328 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5329 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5330
5331 /*
5332 * Some IDT switches incorrectly flag an ACS Source Validation error on
5333 * completions for config read requests even though PCIe r4.0, sec
5334 * 6.12.1.1, says that completions are never affected by ACS Source
5335 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5336 *
5337 * Item #36 - Downstream port applies ACS Source Validation to Completions
5338 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5339 * completions are never affected by ACS Source Validation. However,
5340 * completions received by a downstream port of the PCIe switch from a
5341 * device that has not yet captured a PCIe bus number are incorrectly
5342 * dropped by ACS Source Validation by the switch downstream port.
5343 *
5344 * The workaround suggested by IDT is to issue a config write to the
5345 * downstream device before issuing the first config read. This allows the
5346 * downstream device to capture its bus and device numbers (see PCIe r4.0,
5347 * sec 2.2.9), thus avoiding the ACS error on the completion.
5348 *
5349 * However, we don't know when the device is ready to accept the config
5350 * write, so we do config reads until we receive a non-Config Request Retry
5351 * Status, then do the config write.
5352 *
5353 * To avoid hitting the erratum when doing the config reads, we disable ACS
5354 * SV around this process.
5355 */
pci_idt_bus_quirk(struct pci_bus * bus,int devfn,u32 * l,int timeout)5356 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
5357 {
5358 int pos;
5359 u16 ctrl = 0;
5360 bool found;
5361 struct pci_dev *bridge = bus->self;
5362
5363 pos = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ACS);
5364
5365 /* Disable ACS SV before initial config reads */
5366 if (pos) {
5367 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
5368 if (ctrl & PCI_ACS_SV)
5369 pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
5370 ctrl & ~PCI_ACS_SV);
5371 }
5372
5373 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
5374
5375 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
5376 if (found)
5377 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);
5378
5379 /* Re-enable ACS_SV if it was previously enabled */
5380 if (ctrl & PCI_ACS_SV)
5381 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);
5382
5383 return found;
5384 }
5385
5386 /*
5387 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
5388 * NT endpoints via the internal switch fabric. These IDs replace the
5389 * originating requestor ID TLPs which access host memory on peer NTB
5390 * ports. Therefore, all proxy IDs must be aliased to the NTB device
5391 * to permit access when the IOMMU is turned on.
5392 */
quirk_switchtec_ntb_dma_alias(struct pci_dev * pdev)5393 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
5394 {
5395 void __iomem *mmio;
5396 struct ntb_info_regs __iomem *mmio_ntb;
5397 struct ntb_ctrl_regs __iomem *mmio_ctrl;
5398 struct sys_info_regs __iomem *mmio_sys_info;
5399 u64 partition_map;
5400 u8 partition;
5401 int pp;
5402
5403 if (pci_enable_device(pdev)) {
5404 pci_err(pdev, "Cannot enable Switchtec device\n");
5405 return;
5406 }
5407
5408 mmio = pci_iomap(pdev, 0, 0);
5409 if (mmio == NULL) {
5410 pci_disable_device(pdev);
5411 pci_err(pdev, "Cannot iomap Switchtec device\n");
5412 return;
5413 }
5414
5415 pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
5416
5417 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
5418 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
5419 mmio_sys_info = mmio + SWITCHTEC_GAS_SYS_INFO_OFFSET;
5420
5421 partition = ioread8(&mmio_ntb->partition_id);
5422
5423 partition_map = ioread32(&mmio_ntb->ep_map);
5424 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
5425 partition_map &= ~(1ULL << partition);
5426
5427 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
5428 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
5429 u32 table_sz = 0;
5430 int te;
5431
5432 if (!(partition_map & (1ULL << pp)))
5433 continue;
5434
5435 pci_dbg(pdev, "Processing partition %d\n", pp);
5436
5437 mmio_peer_ctrl = &mmio_ctrl[pp];
5438
5439 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
5440 if (!table_sz) {
5441 pci_warn(pdev, "Partition %d table_sz 0\n", pp);
5442 continue;
5443 }
5444
5445 if (table_sz > 512) {
5446 pci_warn(pdev,
5447 "Invalid Switchtec partition %d table_sz %d\n",
5448 pp, table_sz);
5449 continue;
5450 }
5451
5452 for (te = 0; te < table_sz; te++) {
5453 u32 rid_entry;
5454 u8 devfn;
5455
5456 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
5457 devfn = (rid_entry >> 1) & 0xFF;
5458 pci_dbg(pdev,
5459 "Aliasing Partition %d Proxy ID %02x.%d\n",
5460 pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
5461 pci_add_dma_alias(pdev, devfn);
5462 }
5463 }
5464
5465 pci_iounmap(pdev, mmio);
5466 pci_disable_device(pdev);
5467 }
5468 #define SWITCHTEC_QUIRK(vid) \
5469 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
5470 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
5471
5472 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5473 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5474 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5475 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5476 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5477 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5478 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5479 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5480 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5481 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5482 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5483 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5484 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5485 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5486 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5487 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5488 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5489 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5490 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5491 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5492 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5493 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5494 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5495 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5496 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5497 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5498 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5499 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5500 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5501 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
5502
5503 /*
5504 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
5505 * not always reset the secondary Nvidia GPU between reboots if the system
5506 * is configured to use Hybrid Graphics mode. This results in the GPU
5507 * being left in whatever state it was in during the *previous* boot, which
5508 * causes spurious interrupts from the GPU, which in turn causes us to
5509 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly,
5510 * this also completely breaks nouveau.
5511 *
5512 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
5513 * clean state and fixes all these issues.
5514 *
5515 * When the machine is configured in Dedicated display mode, the issue
5516 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this
5517 * mode, so we can detect that and avoid resetting it.
5518 */
quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev * pdev)5519 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
5520 {
5521 void __iomem *map;
5522 int ret;
5523
5524 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
5525 pdev->subsystem_device != 0x222e ||
5526 !pdev->reset_fn)
5527 return;
5528
5529 if (pci_enable_device_mem(pdev))
5530 return;
5531
5532 /*
5533 * Based on nvkm_device_ctor() in
5534 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
5535 */
5536 map = pci_iomap(pdev, 0, 0x23000);
5537 if (!map) {
5538 pci_err(pdev, "Can't map MMIO space\n");
5539 goto out_disable;
5540 }
5541
5542 /*
5543 * Make sure the GPU looks like it's been POSTed before resetting
5544 * it.
5545 */
5546 if (ioread32(map + 0x2240c) & 0x2) {
5547 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
5548 ret = pci_reset_bus(pdev);
5549 if (ret < 0)
5550 pci_err(pdev, "Failed to reset GPU: %d\n", ret);
5551 }
5552
5553 iounmap(map);
5554 out_disable:
5555 pci_disable_device(pdev);
5556 }
5557 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
5558 PCI_CLASS_DISPLAY_VGA, 8,
5559 quirk_reset_lenovo_thinkpad_p50_nvgpu);
5560
5561 /*
5562 * Device [1b21:2142]
5563 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device.
5564 */
pci_fixup_no_d0_pme(struct pci_dev * dev)5565 static void pci_fixup_no_d0_pme(struct pci_dev *dev)
5566 {
5567 pci_info(dev, "PME# does not work under D0, disabling it\n");
5568 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
5569 }
5570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
5571
5572 /*
5573 * Device [12d8:0x400e] and [12d8:0x400f]
5574 * These devices advertise PME# support in all power states but don't
5575 * reliably assert it.
5576 */
pci_fixup_no_pme(struct pci_dev * dev)5577 static void pci_fixup_no_pme(struct pci_dev *dev)
5578 {
5579 pci_info(dev, "PME# is unreliable, disabling it\n");
5580 dev->pme_support = 0;
5581 }
5582 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_pme);
5583 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_pme);
5584
apex_pci_fixup_class(struct pci_dev * pdev)5585 static void apex_pci_fixup_class(struct pci_dev *pdev)
5586 {
5587 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class;
5588 }
5589 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
5590 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);
5591
nvidia_ion_ahci_fixup(struct pci_dev * pdev)5592 static void nvidia_ion_ahci_fixup(struct pci_dev *pdev)
5593 {
5594 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
5595 }
5596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
5597