1 /*
2 * Imagination Technologies Pulse Width Modulator driver
3 *
4 * Copyright (c) 2014-2015, Imagination Technologies
5 *
6 * Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/err.h>
15 #include <linux/io.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/pwm.h>
23 #include <linux/regmap.h>
24 #include <linux/slab.h>
25
26 /* PWM registers */
27 #define PWM_CTRL_CFG 0x0000
28 #define PWM_CTRL_CFG_NO_SUB_DIV 0
29 #define PWM_CTRL_CFG_SUB_DIV0 1
30 #define PWM_CTRL_CFG_SUB_DIV1 2
31 #define PWM_CTRL_CFG_SUB_DIV0_DIV1 3
32 #define PWM_CTRL_CFG_DIV_SHIFT(ch) ((ch) * 2 + 4)
33 #define PWM_CTRL_CFG_DIV_MASK 0x3
34
35 #define PWM_CH_CFG(ch) (0x4 + (ch) * 4)
36 #define PWM_CH_CFG_TMBASE_SHIFT 0
37 #define PWM_CH_CFG_DUTY_SHIFT 16
38
39 #define PERIP_PWM_PDM_CONTROL 0x0140
40 #define PERIP_PWM_PDM_CONTROL_CH_MASK 0x1
41 #define PERIP_PWM_PDM_CONTROL_CH_SHIFT(ch) ((ch) * 4)
42
43 #define IMG_PWM_PM_TIMEOUT 1000 /* ms */
44
45 /*
46 * PWM period is specified with a timebase register,
47 * in number of step periods. The PWM duty cycle is also
48 * specified in step periods, in the [0, $timebase] range.
49 * In other words, the timebase imposes the duty cycle
50 * resolution. Therefore, let's constraint the timebase to
51 * a minimum value to allow a sane range of duty cycle values.
52 * Imposing a minimum timebase, will impose a maximum PWM frequency.
53 *
54 * The value chosen is completely arbitrary.
55 */
56 #define MIN_TMBASE_STEPS 16
57
58 #define IMG_PWM_NPWM 4
59
60 struct img_pwm_soc_data {
61 u32 max_timebase;
62 };
63
64 struct img_pwm_chip {
65 struct device *dev;
66 struct pwm_chip chip;
67 struct clk *pwm_clk;
68 struct clk *sys_clk;
69 void __iomem *base;
70 struct regmap *periph_regs;
71 int max_period_ns;
72 int min_period_ns;
73 const struct img_pwm_soc_data *data;
74 u32 suspend_ctrl_cfg;
75 u32 suspend_ch_cfg[IMG_PWM_NPWM];
76 };
77
to_img_pwm_chip(struct pwm_chip * chip)78 static inline struct img_pwm_chip *to_img_pwm_chip(struct pwm_chip *chip)
79 {
80 return container_of(chip, struct img_pwm_chip, chip);
81 }
82
img_pwm_writel(struct img_pwm_chip * chip,u32 reg,u32 val)83 static inline void img_pwm_writel(struct img_pwm_chip *chip,
84 u32 reg, u32 val)
85 {
86 writel(val, chip->base + reg);
87 }
88
img_pwm_readl(struct img_pwm_chip * chip,u32 reg)89 static inline u32 img_pwm_readl(struct img_pwm_chip *chip,
90 u32 reg)
91 {
92 return readl(chip->base + reg);
93 }
94
img_pwm_config(struct pwm_chip * chip,struct pwm_device * pwm,int duty_ns,int period_ns)95 static int img_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
96 int duty_ns, int period_ns)
97 {
98 u32 val, div, duty, timebase;
99 unsigned long mul, output_clk_hz, input_clk_hz;
100 struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
101 unsigned int max_timebase = pwm_chip->data->max_timebase;
102 int ret;
103
104 if (period_ns < pwm_chip->min_period_ns ||
105 period_ns > pwm_chip->max_period_ns) {
106 dev_err(chip->dev, "configured period not in range\n");
107 return -ERANGE;
108 }
109
110 input_clk_hz = clk_get_rate(pwm_chip->pwm_clk);
111 output_clk_hz = DIV_ROUND_UP(NSEC_PER_SEC, period_ns);
112
113 mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz);
114 if (mul <= max_timebase) {
115 div = PWM_CTRL_CFG_NO_SUB_DIV;
116 timebase = DIV_ROUND_UP(mul, 1);
117 } else if (mul <= max_timebase * 8) {
118 div = PWM_CTRL_CFG_SUB_DIV0;
119 timebase = DIV_ROUND_UP(mul, 8);
120 } else if (mul <= max_timebase * 64) {
121 div = PWM_CTRL_CFG_SUB_DIV1;
122 timebase = DIV_ROUND_UP(mul, 64);
123 } else if (mul <= max_timebase * 512) {
124 div = PWM_CTRL_CFG_SUB_DIV0_DIV1;
125 timebase = DIV_ROUND_UP(mul, 512);
126 } else if (mul > max_timebase * 512) {
127 dev_err(chip->dev,
128 "failed to configure timebase steps/divider value\n");
129 return -EINVAL;
130 }
131
132 duty = DIV_ROUND_UP(timebase * duty_ns, period_ns);
133
134 ret = pm_runtime_get_sync(chip->dev);
135 if (ret < 0) {
136 pm_runtime_put_autosuspend(chip->dev);
137 return ret;
138 }
139
140 val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
141 val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));
142 val |= (div & PWM_CTRL_CFG_DIV_MASK) <<
143 PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm);
144 img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
145
146 val = (duty << PWM_CH_CFG_DUTY_SHIFT) |
147 (timebase << PWM_CH_CFG_TMBASE_SHIFT);
148 img_pwm_writel(pwm_chip, PWM_CH_CFG(pwm->hwpwm), val);
149
150 pm_runtime_mark_last_busy(chip->dev);
151 pm_runtime_put_autosuspend(chip->dev);
152
153 return 0;
154 }
155
img_pwm_enable(struct pwm_chip * chip,struct pwm_device * pwm)156 static int img_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
157 {
158 u32 val;
159 struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
160 int ret;
161
162 ret = pm_runtime_get_sync(chip->dev);
163 if (ret < 0)
164 return ret;
165
166 val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
167 val |= BIT(pwm->hwpwm);
168 img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
169
170 regmap_update_bits(pwm_chip->periph_regs, PERIP_PWM_PDM_CONTROL,
171 PERIP_PWM_PDM_CONTROL_CH_MASK <<
172 PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm), 0);
173
174 return 0;
175 }
176
img_pwm_disable(struct pwm_chip * chip,struct pwm_device * pwm)177 static void img_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
178 {
179 u32 val;
180 struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
181
182 val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
183 val &= ~BIT(pwm->hwpwm);
184 img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
185
186 pm_runtime_mark_last_busy(chip->dev);
187 pm_runtime_put_autosuspend(chip->dev);
188 }
189
190 static const struct pwm_ops img_pwm_ops = {
191 .config = img_pwm_config,
192 .enable = img_pwm_enable,
193 .disable = img_pwm_disable,
194 .owner = THIS_MODULE,
195 };
196
197 static const struct img_pwm_soc_data pistachio_pwm = {
198 .max_timebase = 255,
199 };
200
201 static const struct of_device_id img_pwm_of_match[] = {
202 {
203 .compatible = "img,pistachio-pwm",
204 .data = &pistachio_pwm,
205 },
206 { }
207 };
208 MODULE_DEVICE_TABLE(of, img_pwm_of_match);
209
img_pwm_runtime_suspend(struct device * dev)210 static int img_pwm_runtime_suspend(struct device *dev)
211 {
212 struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
213
214 clk_disable_unprepare(pwm_chip->pwm_clk);
215 clk_disable_unprepare(pwm_chip->sys_clk);
216
217 return 0;
218 }
219
img_pwm_runtime_resume(struct device * dev)220 static int img_pwm_runtime_resume(struct device *dev)
221 {
222 struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
223 int ret;
224
225 ret = clk_prepare_enable(pwm_chip->sys_clk);
226 if (ret < 0) {
227 dev_err(dev, "could not prepare or enable sys clock\n");
228 return ret;
229 }
230
231 ret = clk_prepare_enable(pwm_chip->pwm_clk);
232 if (ret < 0) {
233 dev_err(dev, "could not prepare or enable pwm clock\n");
234 clk_disable_unprepare(pwm_chip->sys_clk);
235 return ret;
236 }
237
238 return 0;
239 }
240
img_pwm_probe(struct platform_device * pdev)241 static int img_pwm_probe(struct platform_device *pdev)
242 {
243 int ret;
244 u64 val;
245 unsigned long clk_rate;
246 struct resource *res;
247 struct img_pwm_chip *pwm;
248 const struct of_device_id *of_dev_id;
249
250 pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
251 if (!pwm)
252 return -ENOMEM;
253
254 pwm->dev = &pdev->dev;
255
256 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
257 pwm->base = devm_ioremap_resource(&pdev->dev, res);
258 if (IS_ERR(pwm->base))
259 return PTR_ERR(pwm->base);
260
261 of_dev_id = of_match_device(img_pwm_of_match, &pdev->dev);
262 if (!of_dev_id)
263 return -ENODEV;
264 pwm->data = of_dev_id->data;
265
266 pwm->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
267 "img,cr-periph");
268 if (IS_ERR(pwm->periph_regs))
269 return PTR_ERR(pwm->periph_regs);
270
271 pwm->sys_clk = devm_clk_get(&pdev->dev, "sys");
272 if (IS_ERR(pwm->sys_clk)) {
273 dev_err(&pdev->dev, "failed to get system clock\n");
274 return PTR_ERR(pwm->sys_clk);
275 }
276
277 pwm->pwm_clk = devm_clk_get(&pdev->dev, "pwm");
278 if (IS_ERR(pwm->pwm_clk)) {
279 dev_err(&pdev->dev, "failed to get pwm clock\n");
280 return PTR_ERR(pwm->pwm_clk);
281 }
282
283 platform_set_drvdata(pdev, pwm);
284
285 pm_runtime_set_autosuspend_delay(&pdev->dev, IMG_PWM_PM_TIMEOUT);
286 pm_runtime_use_autosuspend(&pdev->dev);
287 pm_runtime_enable(&pdev->dev);
288 if (!pm_runtime_enabled(&pdev->dev)) {
289 ret = img_pwm_runtime_resume(&pdev->dev);
290 if (ret)
291 goto err_pm_disable;
292 }
293
294 clk_rate = clk_get_rate(pwm->pwm_clk);
295 if (!clk_rate) {
296 dev_err(&pdev->dev, "pwm clock has no frequency\n");
297 ret = -EINVAL;
298 goto err_suspend;
299 }
300
301 /* The maximum input clock divider is 512 */
302 val = (u64)NSEC_PER_SEC * 512 * pwm->data->max_timebase;
303 do_div(val, clk_rate);
304 pwm->max_period_ns = val;
305
306 val = (u64)NSEC_PER_SEC * MIN_TMBASE_STEPS;
307 do_div(val, clk_rate);
308 pwm->min_period_ns = val;
309
310 pwm->chip.dev = &pdev->dev;
311 pwm->chip.ops = &img_pwm_ops;
312 pwm->chip.base = -1;
313 pwm->chip.npwm = IMG_PWM_NPWM;
314
315 ret = pwmchip_add(&pwm->chip);
316 if (ret < 0) {
317 dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret);
318 goto err_suspend;
319 }
320
321 return 0;
322
323 err_suspend:
324 if (!pm_runtime_enabled(&pdev->dev))
325 img_pwm_runtime_suspend(&pdev->dev);
326 err_pm_disable:
327 pm_runtime_disable(&pdev->dev);
328 pm_runtime_dont_use_autosuspend(&pdev->dev);
329 return ret;
330 }
331
img_pwm_remove(struct platform_device * pdev)332 static int img_pwm_remove(struct platform_device *pdev)
333 {
334 struct img_pwm_chip *pwm_chip = platform_get_drvdata(pdev);
335
336 pm_runtime_disable(&pdev->dev);
337 if (!pm_runtime_status_suspended(&pdev->dev))
338 img_pwm_runtime_suspend(&pdev->dev);
339
340 return pwmchip_remove(&pwm_chip->chip);
341 }
342
343 #ifdef CONFIG_PM_SLEEP
img_pwm_suspend(struct device * dev)344 static int img_pwm_suspend(struct device *dev)
345 {
346 struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
347 int i, ret;
348
349 if (pm_runtime_status_suspended(dev)) {
350 ret = img_pwm_runtime_resume(dev);
351 if (ret)
352 return ret;
353 }
354
355 for (i = 0; i < pwm_chip->chip.npwm; i++)
356 pwm_chip->suspend_ch_cfg[i] = img_pwm_readl(pwm_chip,
357 PWM_CH_CFG(i));
358
359 pwm_chip->suspend_ctrl_cfg = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
360
361 img_pwm_runtime_suspend(dev);
362
363 return 0;
364 }
365
img_pwm_resume(struct device * dev)366 static int img_pwm_resume(struct device *dev)
367 {
368 struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
369 int ret;
370 int i;
371
372 ret = img_pwm_runtime_resume(dev);
373 if (ret)
374 return ret;
375
376 for (i = 0; i < pwm_chip->chip.npwm; i++)
377 img_pwm_writel(pwm_chip, PWM_CH_CFG(i),
378 pwm_chip->suspend_ch_cfg[i]);
379
380 img_pwm_writel(pwm_chip, PWM_CTRL_CFG, pwm_chip->suspend_ctrl_cfg);
381
382 for (i = 0; i < pwm_chip->chip.npwm; i++)
383 if (pwm_chip->suspend_ctrl_cfg & BIT(i))
384 regmap_update_bits(pwm_chip->periph_regs,
385 PERIP_PWM_PDM_CONTROL,
386 PERIP_PWM_PDM_CONTROL_CH_MASK <<
387 PERIP_PWM_PDM_CONTROL_CH_SHIFT(i),
388 0);
389
390 if (pm_runtime_status_suspended(dev))
391 img_pwm_runtime_suspend(dev);
392
393 return 0;
394 }
395 #endif /* CONFIG_PM */
396
397 static const struct dev_pm_ops img_pwm_pm_ops = {
398 SET_RUNTIME_PM_OPS(img_pwm_runtime_suspend,
399 img_pwm_runtime_resume,
400 NULL)
401 SET_SYSTEM_SLEEP_PM_OPS(img_pwm_suspend, img_pwm_resume)
402 };
403
404 static struct platform_driver img_pwm_driver = {
405 .driver = {
406 .name = "img-pwm",
407 .pm = &img_pwm_pm_ops,
408 .of_match_table = img_pwm_of_match,
409 },
410 .probe = img_pwm_probe,
411 .remove = img_pwm_remove,
412 };
413 module_platform_driver(img_pwm_driver);
414
415 MODULE_AUTHOR("Sai Masarapu <Sai.Masarapu@imgtec.com>");
416 MODULE_DESCRIPTION("Imagination Technologies PWM DAC driver");
417 MODULE_LICENSE("GPL v2");
418