1 /*
2 * MediaTek display pulse-width-modulation controller driver.
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: YH Huang <yh.huang@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/clk.h>
17 #include <linux/err.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/platform_device.h>
23 #include <linux/pwm.h>
24 #include <linux/slab.h>
25
26 #define DISP_PWM_EN 0x00
27
28 #define PWM_CLKDIV_SHIFT 16
29 #define PWM_CLKDIV_MAX 0x3ff
30 #define PWM_CLKDIV_MASK (PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT)
31
32 #define PWM_PERIOD_BIT_WIDTH 12
33 #define PWM_PERIOD_MASK ((1 << PWM_PERIOD_BIT_WIDTH) - 1)
34
35 #define PWM_HIGH_WIDTH_SHIFT 16
36 #define PWM_HIGH_WIDTH_MASK (0x1fff << PWM_HIGH_WIDTH_SHIFT)
37
38 struct mtk_pwm_data {
39 u32 enable_mask;
40 unsigned int con0;
41 u32 con0_sel;
42 unsigned int con1;
43
44 bool has_commit;
45 unsigned int commit;
46 unsigned int commit_mask;
47
48 unsigned int bls_debug;
49 u32 bls_debug_mask;
50 };
51
52 struct mtk_disp_pwm {
53 struct pwm_chip chip;
54 const struct mtk_pwm_data *data;
55 struct clk *clk_main;
56 struct clk *clk_mm;
57 void __iomem *base;
58 };
59
to_mtk_disp_pwm(struct pwm_chip * chip)60 static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip)
61 {
62 return container_of(chip, struct mtk_disp_pwm, chip);
63 }
64
mtk_disp_pwm_update_bits(struct mtk_disp_pwm * mdp,u32 offset,u32 mask,u32 data)65 static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
66 u32 mask, u32 data)
67 {
68 void __iomem *address = mdp->base + offset;
69 u32 value;
70
71 value = readl(address);
72 value &= ~mask;
73 value |= data;
74 writel(value, address);
75 }
76
mtk_disp_pwm_config(struct pwm_chip * chip,struct pwm_device * pwm,int duty_ns,int period_ns)77 static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
78 int duty_ns, int period_ns)
79 {
80 struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
81 u32 clk_div, period, high_width, value;
82 u64 div, rate;
83 int err;
84
85 err = clk_prepare_enable(mdp->clk_main);
86 if (err < 0) {
87 dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
88 return err;
89 }
90
91 err = clk_prepare_enable(mdp->clk_mm);
92 if (err < 0) {
93 dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
94 clk_disable_unprepare(mdp->clk_main);
95 return err;
96 }
97
98 /*
99 * Find period, high_width and clk_div to suit duty_ns and period_ns.
100 * Calculate proper div value to keep period value in the bound.
101 *
102 * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE
103 * duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE
104 *
105 * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
106 * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
107 */
108 rate = clk_get_rate(mdp->clk_main);
109 clk_div = div_u64(rate * period_ns, NSEC_PER_SEC) >>
110 PWM_PERIOD_BIT_WIDTH;
111 if (clk_div > PWM_CLKDIV_MAX) {
112 clk_disable_unprepare(mdp->clk_mm);
113 clk_disable_unprepare(mdp->clk_main);
114 return -EINVAL;
115 }
116
117 div = NSEC_PER_SEC * (clk_div + 1);
118 period = div64_u64(rate * period_ns, div);
119 if (period > 0)
120 period--;
121
122 high_width = div64_u64(rate * duty_ns, div);
123 value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);
124
125 if (mdp->data->bls_debug && !mdp->data->has_commit) {
126 /*
127 * For MT2701, disable double buffer before writing register
128 * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
129 */
130 mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
131 mdp->data->bls_debug_mask,
132 mdp->data->bls_debug_mask);
133 mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
134 mdp->data->con0_sel,
135 mdp->data->con0_sel);
136 }
137
138 mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
139 PWM_CLKDIV_MASK,
140 clk_div << PWM_CLKDIV_SHIFT);
141 mtk_disp_pwm_update_bits(mdp, mdp->data->con1,
142 PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK,
143 value);
144
145 if (mdp->data->has_commit) {
146 mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
147 mdp->data->commit_mask,
148 mdp->data->commit_mask);
149 mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
150 mdp->data->commit_mask,
151 0x0);
152 }
153
154 clk_disable_unprepare(mdp->clk_mm);
155 clk_disable_unprepare(mdp->clk_main);
156
157 return 0;
158 }
159
mtk_disp_pwm_enable(struct pwm_chip * chip,struct pwm_device * pwm)160 static int mtk_disp_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
161 {
162 struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
163 int err;
164
165 err = clk_prepare_enable(mdp->clk_main);
166 if (err < 0) {
167 dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
168 return err;
169 }
170
171 err = clk_prepare_enable(mdp->clk_mm);
172 if (err < 0) {
173 dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
174 clk_disable_unprepare(mdp->clk_main);
175 return err;
176 }
177
178 mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
179 mdp->data->enable_mask);
180
181 return 0;
182 }
183
mtk_disp_pwm_disable(struct pwm_chip * chip,struct pwm_device * pwm)184 static void mtk_disp_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
185 {
186 struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
187
188 mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
189 0x0);
190
191 clk_disable_unprepare(mdp->clk_mm);
192 clk_disable_unprepare(mdp->clk_main);
193 }
194
195 static const struct pwm_ops mtk_disp_pwm_ops = {
196 .config = mtk_disp_pwm_config,
197 .enable = mtk_disp_pwm_enable,
198 .disable = mtk_disp_pwm_disable,
199 .owner = THIS_MODULE,
200 };
201
mtk_disp_pwm_probe(struct platform_device * pdev)202 static int mtk_disp_pwm_probe(struct platform_device *pdev)
203 {
204 struct mtk_disp_pwm *mdp;
205 struct resource *r;
206 int ret;
207
208 mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL);
209 if (!mdp)
210 return -ENOMEM;
211
212 mdp->data = of_device_get_match_data(&pdev->dev);
213
214 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
215 mdp->base = devm_ioremap_resource(&pdev->dev, r);
216 if (IS_ERR(mdp->base))
217 return PTR_ERR(mdp->base);
218
219 mdp->clk_main = devm_clk_get(&pdev->dev, "main");
220 if (IS_ERR(mdp->clk_main))
221 return PTR_ERR(mdp->clk_main);
222
223 mdp->clk_mm = devm_clk_get(&pdev->dev, "mm");
224 if (IS_ERR(mdp->clk_mm))
225 return PTR_ERR(mdp->clk_mm);
226
227 mdp->chip.dev = &pdev->dev;
228 mdp->chip.ops = &mtk_disp_pwm_ops;
229 mdp->chip.base = -1;
230 mdp->chip.npwm = 1;
231
232 ret = pwmchip_add(&mdp->chip);
233 if (ret < 0) {
234 dev_err(&pdev->dev, "pwmchip_add() failed: %pe\n", ERR_PTR(ret));
235 return ret;
236 }
237
238 platform_set_drvdata(pdev, mdp);
239
240 return 0;
241 }
242
mtk_disp_pwm_remove(struct platform_device * pdev)243 static int mtk_disp_pwm_remove(struct platform_device *pdev)
244 {
245 struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev);
246
247 pwmchip_remove(&mdp->chip);
248
249 return 0;
250 }
251
252 static const struct mtk_pwm_data mt2701_pwm_data = {
253 .enable_mask = BIT(16),
254 .con0 = 0xa8,
255 .con0_sel = 0x2,
256 .con1 = 0xac,
257 .has_commit = false,
258 .bls_debug = 0xb0,
259 .bls_debug_mask = 0x3,
260 };
261
262 static const struct mtk_pwm_data mt8173_pwm_data = {
263 .enable_mask = BIT(0),
264 .con0 = 0x10,
265 .con0_sel = 0x0,
266 .con1 = 0x14,
267 .has_commit = true,
268 .commit = 0x8,
269 .commit_mask = 0x1,
270 };
271
272 static const struct of_device_id mtk_disp_pwm_of_match[] = {
273 { .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
274 { .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
275 { .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
276 { }
277 };
278 MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);
279
280 static struct platform_driver mtk_disp_pwm_driver = {
281 .driver = {
282 .name = "mediatek-disp-pwm",
283 .of_match_table = mtk_disp_pwm_of_match,
284 },
285 .probe = mtk_disp_pwm_probe,
286 .remove = mtk_disp_pwm_remove,
287 };
288 module_platform_driver(mtk_disp_pwm_driver);
289
290 MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>");
291 MODULE_DESCRIPTION("MediaTek SoC display PWM driver");
292 MODULE_LICENSE("GPL v2");
293